1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * see notice in hfc_multi.c |
4 | */ |
5 | |
6 | #define DEBUG_HFCMULTI_FIFO 0x00010000 |
7 | #define DEBUG_HFCMULTI_CRC 0x00020000 |
8 | #define DEBUG_HFCMULTI_INIT 0x00040000 |
9 | #define DEBUG_HFCMULTI_PLXSD 0x00080000 |
10 | #define DEBUG_HFCMULTI_MODE 0x00100000 |
11 | #define DEBUG_HFCMULTI_MSG 0x00200000 |
12 | #define DEBUG_HFCMULTI_STATE 0x00400000 |
13 | #define DEBUG_HFCMULTI_FILL 0x00800000 |
14 | #define DEBUG_HFCMULTI_SYNC 0x01000000 |
15 | #define DEBUG_HFCMULTI_DTMF 0x02000000 |
16 | #define DEBUG_HFCMULTI_LOCK 0x80000000 |
17 | |
18 | #define PCI_ENA_REGIO 0x01 |
19 | #define PCI_ENA_MEMIO 0x02 |
20 | |
21 | #define XHFC_IRQ 4 /* SIU_IRQ2 */ |
22 | #define XHFC_MEMBASE 0xFE000000 |
23 | #define XHFC_MEMSIZE 0x00001000 |
24 | #define XHFC_OFFSET 0x00001000 |
25 | #define PA_XHFC_A0 0x0020 /* PA10 */ |
26 | #define PB_XHFC_IRQ1 0x00000100 /* PB23 */ |
27 | #define PB_XHFC_IRQ2 0x00000200 /* PB22 */ |
28 | #define PB_XHFC_IRQ3 0x00000400 /* PB21 */ |
29 | #define PB_XHFC_IRQ4 0x00000800 /* PB20 */ |
30 | |
31 | /* |
32 | * NOTE: some registers are assigned multiple times due to different modes |
33 | * also registers are assigned differen for HFC-4s/8s and HFC-E1 |
34 | */ |
35 | |
36 | /* |
37 | #define MAX_FRAME_SIZE 2048 |
38 | */ |
39 | |
40 | struct hfc_chan { |
41 | struct dchannel *dch; /* link if channel is a D-channel */ |
42 | struct bchannel *bch; /* link if channel is a B-channel */ |
43 | int port; /* the interface port this */ |
44 | /* channel is associated with */ |
45 | int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */ |
46 | int los, ais, slip_tx, slip_rx, rdi; /* current alarms */ |
47 | int jitter; |
48 | u_long cfg; /* port configuration */ |
49 | int sync; /* sync state (used by E1) */ |
50 | u_int protocol; /* current protocol */ |
51 | int slot_tx; /* current pcm slot */ |
52 | int bank_tx; /* current pcm bank */ |
53 | int slot_rx; |
54 | int bank_rx; |
55 | int conf; /* conference setting of TX slot */ |
56 | int txpending; /* if there is currently data in */ |
57 | /* the FIFO 0=no, 1=yes, 2=splloop */ |
58 | int Zfill; /* rx-fifo level on last hfcmulti_tx */ |
59 | int rx_off; /* set to turn fifo receive off */ |
60 | int coeff_count; /* curren coeff block */ |
61 | s32 *coeff; /* memory pointer to 8 coeff blocks */ |
62 | }; |
63 | |
64 | |
65 | struct hfcm_hw { |
66 | u_char r_ctrl; |
67 | u_char r_irq_ctrl; |
68 | u_char r_cirm; |
69 | u_char r_ram_sz; |
70 | u_char r_pcm_md0; |
71 | u_char r_irqmsk_misc; |
72 | u_char r_dtmf; |
73 | u_char r_st_sync; |
74 | u_char r_sci_msk; |
75 | u_char r_tx0, r_tx1; |
76 | u_char a_st_ctrl0[8]; |
77 | u_char r_bert_wd_md; |
78 | timer_t timer; |
79 | }; |
80 | |
81 | |
82 | /* for each stack these flags are used (cfg) */ |
83 | #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */ |
84 | #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */ |
85 | #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */ |
86 | #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */ |
87 | #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */ |
88 | #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */ |
89 | #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */ |
90 | #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */ |
91 | #define HFC_CFG_DTMF 9 /* enable DTMF-detection */ |
92 | #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */ |
93 | /* use double frame instead. */ |
94 | |
95 | #define HFC_TYPE_E1 1 /* controller is HFC-E1 */ |
96 | #define HFC_TYPE_4S 4 /* controller is HFC-4S */ |
97 | #define HFC_TYPE_8S 8 /* controller is HFC-8S */ |
98 | #define HFC_TYPE_XHFC 5 /* controller is XHFC */ |
99 | |
100 | #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */ |
101 | #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */ |
102 | #define HFC_CHIP_REVISION0 2 /* old fifo handling */ |
103 | #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */ |
104 | #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */ |
105 | #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */ |
106 | #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */ |
107 | #define HFC_CHIP_CONF 7 /* conference handling is enabled */ |
108 | #define HFC_CHIP_ULAW 8 /* ULAW mode */ |
109 | #define HFC_CHIP_CLOCK2 9 /* double clock mode */ |
110 | #define HFC_CHIP_E1CLOCK_GET 10 /* always get clock from E1 interface */ |
111 | #define HFC_CHIP_E1CLOCK_PUT 11 /* always put clock from E1 interface */ |
112 | #define HFC_CHIP_WATCHDOG 12 /* whether we should send signals */ |
113 | /* to the watchdog */ |
114 | #define HFC_CHIP_B410P 13 /* whether we have a b410p with echocan in */ |
115 | /* hw */ |
116 | #define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */ |
117 | #define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */ |
118 | |
119 | #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */ |
120 | #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */ |
121 | #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */ |
122 | #define HFC_IO_MODE_EMBSD 0x03 /* direct access */ |
123 | |
124 | /* table entry in the PCI devices list */ |
125 | struct hm_map { |
126 | char *vendor_name; |
127 | char *card_name; |
128 | int type; |
129 | int ports; |
130 | int clock2; |
131 | int leds; |
132 | int opticalsupport; |
133 | int dip_type; |
134 | int io_mode; |
135 | int irq; |
136 | }; |
137 | |
138 | struct hfc_multi { |
139 | struct list_head list; |
140 | struct hm_map *mtyp; |
141 | int id; |
142 | int pcm; /* id of pcm bus */ |
143 | int ctype; /* controller type */ |
144 | int ports; |
145 | |
146 | u_int irq; /* irq used by card */ |
147 | u_int irqcnt; |
148 | struct pci_dev *pci_dev; |
149 | int io_mode; /* selects mode */ |
150 | #ifdef HFC_REGISTER_DEBUG |
151 | void (*HFC_outb)(struct hfc_multi *hc, u_char reg, |
152 | u_char val, const char *function, int line); |
153 | void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, |
154 | u_char val, const char *function, int line); |
155 | u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg, |
156 | const char *function, int line); |
157 | u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg, |
158 | const char *function, int line); |
159 | u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg, |
160 | const char *function, int line); |
161 | u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg, |
162 | const char *function, int line); |
163 | void (*HFC_wait)(struct hfc_multi *hc, |
164 | const char *function, int line); |
165 | void (*HFC_wait_nodebug)(struct hfc_multi *hc, |
166 | const char *function, int line); |
167 | #else |
168 | void (*HFC_outb)(struct hfc_multi *hc, u_char reg, |
169 | u_char val); |
170 | void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, |
171 | u_char val); |
172 | u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg); |
173 | u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg); |
174 | u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg); |
175 | u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg); |
176 | void (*HFC_wait)(struct hfc_multi *hc); |
177 | void (*HFC_wait_nodebug)(struct hfc_multi *hc); |
178 | #endif |
179 | void (*read_fifo)(struct hfc_multi *hc, u_char *data, |
180 | int len); |
181 | void (*write_fifo)(struct hfc_multi *hc, u_char *data, |
182 | int len); |
183 | u_long pci_origmembase, plx_origmembase; |
184 | void __iomem *pci_membase; /* PCI memory */ |
185 | void __iomem *plx_membase; /* PLX memory */ |
186 | u_long xhfc_origmembase; |
187 | u_char *xhfc_membase; |
188 | u_long *xhfc_memaddr, *xhfc_memdata; |
189 | #ifdef CONFIG_MISDN_HFCMULTI_8xx |
190 | struct immap *immap; |
191 | #endif |
192 | u_long pb_irqmsk; /* Portbit mask to check the IRQ line */ |
193 | u_long pci_iobase; /* PCI IO */ |
194 | struct hfcm_hw hw; /* remember data of write-only-registers */ |
195 | |
196 | u_long chip; /* chip configuration */ |
197 | int masterclk; /* port that provides master clock -1=off */ |
198 | unsigned char silence;/* silence byte */ |
199 | unsigned char silence_data[128];/* silence block */ |
200 | int dtmf; /* flag that dtmf is currently in process */ |
201 | int Flen; /* F-buffer size */ |
202 | int Zlen; /* Z-buffer size (must be int for calculation)*/ |
203 | int max_trans; /* maximum transparent fifo fill */ |
204 | int Zmin; /* Z-buffer offset */ |
205 | int DTMFbase; /* base address of DTMF coefficients */ |
206 | |
207 | u_int slots; /* number of PCM slots */ |
208 | u_int leds; /* type of leds */ |
209 | u_long ledstate; /* save last state of leds */ |
210 | int opticalsupport; /* has the e1 board */ |
211 | /* an optical Interface */ |
212 | |
213 | u_int bmask[32]; /* bitmask of bchannels for port */ |
214 | u_char dnum[32]; /* array of used dchannel numbers for port */ |
215 | u_char created[32]; /* what port is created */ |
216 | u_int activity_tx; /* if there is data TX / RX */ |
217 | u_int activity_rx; /* bitmask according to port number */ |
218 | /* (will be cleared after */ |
219 | /* showing led-states) */ |
220 | u_int flash[8]; /* counter for flashing 8 leds on activity */ |
221 | |
222 | u_long wdcount; /* every 500 ms we need to */ |
223 | /* send the watchdog a signal */ |
224 | u_char wdbyte; /* watchdog toggle byte */ |
225 | int e1_state; /* keep track of last state */ |
226 | int e1_getclock; /* if sync is retrieved from interface */ |
227 | int syncronized; /* keep track of existing sync interface */ |
228 | int e1_resync; /* resync jobs */ |
229 | |
230 | spinlock_t lock; /* the lock */ |
231 | |
232 | struct mISDNclock *iclock; /* isdn clock support */ |
233 | int iclock_on; |
234 | |
235 | /* |
236 | * the channel index is counted from 0, regardless where the channel |
237 | * is located on the hfc-channel. |
238 | * the bch->channel is equvalent to the hfc-channel |
239 | */ |
240 | struct hfc_chan chan[32]; |
241 | signed char slot_owner[256]; /* owner channel of slot */ |
242 | }; |
243 | |
244 | /* PLX GPIOs */ |
245 | #define PLX_GPIO4_DIR_BIT 13 |
246 | #define PLX_GPIO4_BIT 14 |
247 | #define PLX_GPIO5_DIR_BIT 16 |
248 | #define PLX_GPIO5_BIT 17 |
249 | #define PLX_GPIO6_DIR_BIT 19 |
250 | #define PLX_GPIO6_BIT 20 |
251 | #define PLX_GPIO7_DIR_BIT 22 |
252 | #define PLX_GPIO7_BIT 23 |
253 | #define PLX_GPIO8_DIR_BIT 25 |
254 | #define PLX_GPIO8_BIT 26 |
255 | |
256 | #define PLX_GPIO4 (1 << PLX_GPIO4_BIT) |
257 | #define PLX_GPIO5 (1 << PLX_GPIO5_BIT) |
258 | #define PLX_GPIO6 (1 << PLX_GPIO6_BIT) |
259 | #define PLX_GPIO7 (1 << PLX_GPIO7_BIT) |
260 | #define PLX_GPIO8 (1 << PLX_GPIO8_BIT) |
261 | |
262 | #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT) |
263 | #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT) |
264 | #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT) |
265 | #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT) |
266 | #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT) |
267 | |
268 | #define PLX_TERM_ON PLX_GPIO7 |
269 | #define PLX_SLAVE_EN_N PLX_GPIO5 |
270 | #define PLX_MASTER_EN PLX_GPIO6 |
271 | #define PLX_SYNC_O_EN PLX_GPIO4 |
272 | #define PLX_DSP_RES_N PLX_GPIO8 |
273 | /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */ |
274 | #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \ |
275 | | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N) |
276 | |
277 | /* PLX Interrupt Control/STATUS */ |
278 | #define PLX_INTCSR_LINTI1_ENABLE 0x01 |
279 | #define PLX_INTCSR_LINTI1_STATUS 0x04 |
280 | #define PLX_INTCSR_LINTI2_ENABLE 0x08 |
281 | #define PLX_INTCSR_LINTI2_STATUS 0x20 |
282 | #define PLX_INTCSR_PCIINT_ENABLE 0x40 |
283 | |
284 | /* PLX Registers */ |
285 | #define PLX_INTCSR 0x4c |
286 | #define PLX_CNTRL 0x50 |
287 | #define PLX_GPIOC 0x54 |
288 | |
289 | |
290 | /* |
291 | * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1 |
292 | */ |
293 | |
294 | /* write only registers */ |
295 | #define R_CIRM 0x00 |
296 | #define R_CTRL 0x01 |
297 | #define R_BRG_PCM_CFG 0x02 |
298 | #define R_RAM_ADDR0 0x08 |
299 | #define R_RAM_ADDR1 0x09 |
300 | #define R_RAM_ADDR2 0x0A |
301 | #define R_FIRST_FIFO 0x0B |
302 | #define R_RAM_SZ 0x0C |
303 | #define R_FIFO_MD 0x0D |
304 | #define R_INC_RES_FIFO 0x0E |
305 | #define R_FSM_IDX 0x0F |
306 | #define R_FIFO 0x0F |
307 | #define R_SLOT 0x10 |
308 | #define R_IRQMSK_MISC 0x11 |
309 | #define R_SCI_MSK 0x12 |
310 | #define R_IRQ_CTRL 0x13 |
311 | #define R_PCM_MD0 0x14 |
312 | #define R_PCM_MD1 0x15 |
313 | #define R_PCM_MD2 0x15 |
314 | #define R_SH0H 0x15 |
315 | #define R_SH1H 0x15 |
316 | #define R_SH0L 0x15 |
317 | #define R_SH1L 0x15 |
318 | #define R_SL_SEL0 0x15 |
319 | #define R_SL_SEL1 0x15 |
320 | #define R_SL_SEL2 0x15 |
321 | #define R_SL_SEL3 0x15 |
322 | #define R_SL_SEL4 0x15 |
323 | #define R_SL_SEL5 0x15 |
324 | #define R_SL_SEL6 0x15 |
325 | #define R_SL_SEL7 0x15 |
326 | #define R_ST_SEL 0x16 |
327 | #define R_ST_SYNC 0x17 |
328 | #define R_CONF_EN 0x18 |
329 | #define R_TI_WD 0x1A |
330 | #define R_BERT_WD_MD 0x1B |
331 | #define R_DTMF 0x1C |
332 | #define R_DTMF_N 0x1D |
333 | #define R_E1_WR_STA 0x20 |
334 | #define R_E1_RD_STA 0x20 |
335 | #define R_LOS0 0x22 |
336 | #define R_LOS1 0x23 |
337 | #define R_RX0 0x24 |
338 | #define R_RX_FR0 0x25 |
339 | #define R_RX_FR1 0x26 |
340 | #define R_TX0 0x28 |
341 | #define R_TX1 0x29 |
342 | #define R_TX_FR0 0x2C |
343 | |
344 | #define R_TX_FR1 0x2D |
345 | #define R_TX_FR2 0x2E |
346 | #define R_JATT_ATT 0x2F /* undocumented */ |
347 | #define A_ST_RD_STATE 0x30 |
348 | #define A_ST_WR_STATE 0x30 |
349 | #define R_RX_OFF 0x30 |
350 | #define A_ST_CTRL0 0x31 |
351 | #define R_SYNC_OUT 0x31 |
352 | #define A_ST_CTRL1 0x32 |
353 | #define A_ST_CTRL2 0x33 |
354 | #define A_ST_SQ_WR 0x34 |
355 | #define R_TX_OFF 0x34 |
356 | #define R_SYNC_CTRL 0x35 |
357 | #define A_ST_CLK_DLY 0x37 |
358 | #define R_PWM0 0x38 |
359 | #define R_PWM1 0x39 |
360 | #define A_ST_B1_TX 0x3C |
361 | #define A_ST_B2_TX 0x3D |
362 | #define A_ST_D_TX 0x3E |
363 | #define R_GPIO_OUT0 0x40 |
364 | #define R_GPIO_OUT1 0x41 |
365 | #define R_GPIO_EN0 0x42 |
366 | #define R_GPIO_EN1 0x43 |
367 | #define R_GPIO_SEL 0x44 |
368 | #define R_BRG_CTRL 0x45 |
369 | #define R_PWM_MD 0x46 |
370 | #define R_BRG_MD 0x47 |
371 | #define R_BRG_TIM0 0x48 |
372 | #define R_BRG_TIM1 0x49 |
373 | #define R_BRG_TIM2 0x4A |
374 | #define R_BRG_TIM3 0x4B |
375 | #define R_BRG_TIM_SEL01 0x4C |
376 | #define R_BRG_TIM_SEL23 0x4D |
377 | #define R_BRG_TIM_SEL45 0x4E |
378 | #define R_BRG_TIM_SEL67 0x4F |
379 | #define A_SL_CFG 0xD0 |
380 | #define A_CONF 0xD1 |
381 | #define A_CH_MSK 0xF4 |
382 | #define A_CON_HDLC 0xFA |
383 | #define A_SUBCH_CFG 0xFB |
384 | #define A_CHANNEL 0xFC |
385 | #define A_FIFO_SEQ 0xFD |
386 | #define A_IRQ_MSK 0xFF |
387 | |
388 | /* read only registers */ |
389 | #define A_Z12 0x04 |
390 | #define A_Z1L 0x04 |
391 | #define A_Z1 0x04 |
392 | #define A_Z1H 0x05 |
393 | #define A_Z2L 0x06 |
394 | #define A_Z2 0x06 |
395 | #define A_Z2H 0x07 |
396 | #define A_F1 0x0C |
397 | #define A_F12 0x0C |
398 | #define A_F2 0x0D |
399 | #define R_IRQ_OVIEW 0x10 |
400 | #define R_IRQ_MISC 0x11 |
401 | #define R_IRQ_STATECH 0x12 |
402 | #define R_CONF_OFLOW 0x14 |
403 | #define R_RAM_USE 0x15 |
404 | #define R_CHIP_ID 0x16 |
405 | #define R_BERT_STA 0x17 |
406 | #define R_F0_CNTL 0x18 |
407 | #define R_F0_CNTH 0x19 |
408 | #define R_BERT_EC 0x1A |
409 | #define R_BERT_ECL 0x1A |
410 | #define R_BERT_ECH 0x1B |
411 | #define R_STATUS 0x1C |
412 | #define R_CHIP_RV 0x1F |
413 | #define R_STATE 0x20 |
414 | #define R_SYNC_STA 0x24 |
415 | #define R_RX_SL0_0 0x25 |
416 | #define R_RX_SL0_1 0x26 |
417 | #define R_RX_SL0_2 0x27 |
418 | #define R_JATT_DIR 0x2b /* undocumented */ |
419 | #define R_SLIP 0x2c |
420 | #define A_ST_RD_STA 0x30 |
421 | #define R_FAS_EC 0x30 |
422 | #define R_FAS_ECL 0x30 |
423 | #define R_FAS_ECH 0x31 |
424 | #define R_VIO_EC 0x32 |
425 | #define R_VIO_ECL 0x32 |
426 | #define R_VIO_ECH 0x33 |
427 | #define A_ST_SQ_RD 0x34 |
428 | #define R_CRC_EC 0x34 |
429 | #define R_CRC_ECL 0x34 |
430 | #define R_CRC_ECH 0x35 |
431 | #define R_E_EC 0x36 |
432 | #define R_E_ECL 0x36 |
433 | #define R_E_ECH 0x37 |
434 | #define R_SA6_SA13_EC 0x38 |
435 | #define R_SA6_SA13_ECL 0x38 |
436 | #define R_SA6_SA13_ECH 0x39 |
437 | #define R_SA6_SA23_EC 0x3A |
438 | #define R_SA6_SA23_ECL 0x3A |
439 | #define R_SA6_SA23_ECH 0x3B |
440 | #define A_ST_B1_RX 0x3C |
441 | #define A_ST_B2_RX 0x3D |
442 | #define A_ST_D_RX 0x3E |
443 | #define A_ST_E_RX 0x3F |
444 | #define R_GPIO_IN0 0x40 |
445 | #define R_GPIO_IN1 0x41 |
446 | #define R_GPI_IN0 0x44 |
447 | #define R_GPI_IN1 0x45 |
448 | #define R_GPI_IN2 0x46 |
449 | #define R_GPI_IN3 0x47 |
450 | #define R_INT_DATA 0x88 |
451 | #define R_IRQ_FIFO_BL0 0xC8 |
452 | #define R_IRQ_FIFO_BL1 0xC9 |
453 | #define R_IRQ_FIFO_BL2 0xCA |
454 | #define R_IRQ_FIFO_BL3 0xCB |
455 | #define R_IRQ_FIFO_BL4 0xCC |
456 | #define R_IRQ_FIFO_BL5 0xCD |
457 | #define R_IRQ_FIFO_BL6 0xCE |
458 | #define R_IRQ_FIFO_BL7 0xCF |
459 | |
460 | /* read and write registers */ |
461 | #define A_FIFO_DATA0 0x80 |
462 | #define A_FIFO_DATA1 0x80 |
463 | #define A_FIFO_DATA2 0x80 |
464 | #define A_FIFO_DATA0_NOINC 0x84 |
465 | #define A_FIFO_DATA1_NOINC 0x84 |
466 | #define A_FIFO_DATA2_NOINC 0x84 |
467 | #define R_RAM_DATA 0xC0 |
468 | |
469 | |
470 | /* |
471 | * BIT SETTING FOR HFC-4S/8S AND HFC-E1 |
472 | */ |
473 | |
474 | /* chapter 2: universal bus interface */ |
475 | /* R_CIRM */ |
476 | #define V_IRQ_SEL 0x01 |
477 | #define V_SRES 0x08 |
478 | #define V_HFCRES 0x10 |
479 | #define V_PCMRES 0x20 |
480 | #define V_STRES 0x40 |
481 | #define V_ETRES 0x40 |
482 | #define V_RLD_EPR 0x80 |
483 | /* R_CTRL */ |
484 | #define V_FIFO_LPRIO 0x02 |
485 | #define V_SLOW_RD 0x04 |
486 | #define V_EXT_RAM 0x08 |
487 | #define V_CLK_OFF 0x20 |
488 | #define V_ST_CLK 0x40 |
489 | /* R_RAM_ADDR0 */ |
490 | #define V_RAM_ADDR2 0x01 |
491 | #define V_ADDR_RES 0x40 |
492 | #define V_ADDR_INC 0x80 |
493 | /* R_RAM_SZ */ |
494 | #define V_RAM_SZ 0x01 |
495 | #define V_PWM0_16KHZ 0x10 |
496 | #define V_PWM1_16KHZ 0x20 |
497 | #define V_FZ_MD 0x80 |
498 | /* R_CHIP_ID */ |
499 | #define V_PNP_IRQ 0x01 |
500 | #define V_CHIP_ID 0x10 |
501 | |
502 | /* chapter 3: data flow */ |
503 | /* R_FIRST_FIFO */ |
504 | #define V_FIRST_FIRO_DIR 0x01 |
505 | #define V_FIRST_FIFO_NUM 0x02 |
506 | /* R_FIFO_MD */ |
507 | #define V_FIFO_MD 0x01 |
508 | #define V_CSM_MD 0x04 |
509 | #define V_FSM_MD 0x08 |
510 | #define V_FIFO_SZ 0x10 |
511 | /* R_FIFO */ |
512 | #define V_FIFO_DIR 0x01 |
513 | #define V_FIFO_NUM 0x02 |
514 | #define V_REV 0x80 |
515 | /* R_SLOT */ |
516 | #define V_SL_DIR 0x01 |
517 | #define V_SL_NUM 0x02 |
518 | /* A_SL_CFG */ |
519 | #define V_CH_DIR 0x01 |
520 | #define V_CH_SEL 0x02 |
521 | #define V_ROUTING 0x40 |
522 | /* A_CON_HDLC */ |
523 | #define V_IFF 0x01 |
524 | #define V_HDLC_TRP 0x02 |
525 | #define V_TRP_IRQ 0x04 |
526 | #define V_DATA_FLOW 0x20 |
527 | /* A_SUBCH_CFG */ |
528 | #define V_BIT_CNT 0x01 |
529 | #define V_START_BIT 0x08 |
530 | #define V_LOOP_FIFO 0x40 |
531 | #define V_INV_DATA 0x80 |
532 | /* A_CHANNEL */ |
533 | #define V_CH_DIR0 0x01 |
534 | #define V_CH_NUM0 0x02 |
535 | /* A_FIFO_SEQ */ |
536 | #define V_NEXT_FIFO_DIR 0x01 |
537 | #define V_NEXT_FIFO_NUM 0x02 |
538 | #define V_SEQ_END 0x40 |
539 | |
540 | /* chapter 4: FIFO handling and HDLC controller */ |
541 | /* R_INC_RES_FIFO */ |
542 | #define V_INC_F 0x01 |
543 | #define V_RES_F 0x02 |
544 | #define V_RES_LOST 0x04 |
545 | |
546 | /* chapter 5: S/T interface */ |
547 | /* R_SCI_MSK */ |
548 | #define V_SCI_MSK_ST0 0x01 |
549 | #define V_SCI_MSK_ST1 0x02 |
550 | #define V_SCI_MSK_ST2 0x04 |
551 | #define V_SCI_MSK_ST3 0x08 |
552 | #define V_SCI_MSK_ST4 0x10 |
553 | #define V_SCI_MSK_ST5 0x20 |
554 | #define V_SCI_MSK_ST6 0x40 |
555 | #define V_SCI_MSK_ST7 0x80 |
556 | /* R_ST_SEL */ |
557 | #define V_ST_SEL 0x01 |
558 | #define V_MULT_ST 0x08 |
559 | /* R_ST_SYNC */ |
560 | #define V_SYNC_SEL 0x01 |
561 | #define V_AUTO_SYNC 0x08 |
562 | /* A_ST_WR_STA */ |
563 | #define V_ST_SET_STA 0x01 |
564 | #define V_ST_LD_STA 0x10 |
565 | #define V_ST_ACT 0x20 |
566 | #define V_SET_G2_G3 0x80 |
567 | /* A_ST_CTRL0 */ |
568 | #define V_B1_EN 0x01 |
569 | #define V_B2_EN 0x02 |
570 | #define V_ST_MD 0x04 |
571 | #define V_D_PRIO 0x08 |
572 | #define V_SQ_EN 0x10 |
573 | #define V_96KHZ 0x20 |
574 | #define V_TX_LI 0x40 |
575 | #define V_ST_STOP 0x80 |
576 | /* A_ST_CTRL1 */ |
577 | #define V_G2_G3_EN 0x01 |
578 | #define V_D_HI 0x04 |
579 | #define V_E_IGNO 0x08 |
580 | #define V_E_LO 0x10 |
581 | #define V_B12_SWAP 0x80 |
582 | /* A_ST_CTRL2 */ |
583 | #define V_B1_RX_EN 0x01 |
584 | #define V_B2_RX_EN 0x02 |
585 | #define V_ST_TRIS 0x40 |
586 | /* A_ST_CLK_DLY */ |
587 | #define V_ST_CK_DLY 0x01 |
588 | #define V_ST_SMPL 0x10 |
589 | /* A_ST_D_TX */ |
590 | #define V_ST_D_TX 0x40 |
591 | /* R_IRQ_STATECH */ |
592 | #define V_SCI_ST0 0x01 |
593 | #define V_SCI_ST1 0x02 |
594 | #define V_SCI_ST2 0x04 |
595 | #define V_SCI_ST3 0x08 |
596 | #define V_SCI_ST4 0x10 |
597 | #define V_SCI_ST5 0x20 |
598 | #define V_SCI_ST6 0x40 |
599 | #define V_SCI_ST7 0x80 |
600 | /* A_ST_RD_STA */ |
601 | #define V_ST_STA 0x01 |
602 | #define V_FR_SYNC_ST 0x10 |
603 | #define V_TI2_EXP 0x20 |
604 | #define V_INFO0 0x40 |
605 | #define V_G2_G3 0x80 |
606 | /* A_ST_SQ_RD */ |
607 | #define V_ST_SQ 0x01 |
608 | #define V_MF_RX_RDY 0x10 |
609 | #define V_MF_TX_RDY 0x80 |
610 | /* A_ST_D_RX */ |
611 | #define V_ST_D_RX 0x40 |
612 | /* A_ST_E_RX */ |
613 | #define V_ST_E_RX 0x40 |
614 | |
615 | /* chapter 5: E1 interface */ |
616 | /* R_E1_WR_STA */ |
617 | /* R_E1_RD_STA */ |
618 | #define V_E1_SET_STA 0x01 |
619 | #define V_E1_LD_STA 0x10 |
620 | /* R_RX0 */ |
621 | #define V_RX_CODE 0x01 |
622 | #define V_RX_FBAUD 0x04 |
623 | #define V_RX_CMI 0x08 |
624 | #define V_RX_INV_CMI 0x10 |
625 | #define V_RX_INV_CLK 0x20 |
626 | #define V_RX_INV_DATA 0x40 |
627 | #define V_AIS_ITU 0x80 |
628 | /* R_RX_FR0 */ |
629 | #define V_NO_INSYNC 0x01 |
630 | #define V_AUTO_RESYNC 0x02 |
631 | #define V_AUTO_RECO 0x04 |
632 | #define V_SWORD_COND 0x08 |
633 | #define V_SYNC_LOSS 0x10 |
634 | #define V_XCRC_SYNC 0x20 |
635 | #define V_MF_RESYNC 0x40 |
636 | #define V_RESYNC 0x80 |
637 | /* R_RX_FR1 */ |
638 | #define V_RX_MF 0x01 |
639 | #define V_RX_MF_SYNC 0x02 |
640 | #define V_RX_SL0_RAM 0x04 |
641 | #define V_ERR_SIM 0x20 |
642 | #define V_RES_NMF 0x40 |
643 | /* R_TX0 */ |
644 | #define V_TX_CODE 0x01 |
645 | #define V_TX_FBAUD 0x04 |
646 | #define V_TX_CMI_CODE 0x08 |
647 | #define V_TX_INV_CMI_CODE 0x10 |
648 | #define V_TX_INV_CLK 0x20 |
649 | #define V_TX_INV_DATA 0x40 |
650 | #define V_OUT_EN 0x80 |
651 | /* R_TX1 */ |
652 | #define V_INV_CLK 0x01 |
653 | #define V_EXCHG_DATA_LI 0x02 |
654 | #define V_AIS_OUT 0x04 |
655 | #define V_ATX 0x20 |
656 | #define V_NTRI 0x40 |
657 | #define V_AUTO_ERR_RES 0x80 |
658 | /* R_TX_FR0 */ |
659 | #define V_TRP_FAS 0x01 |
660 | #define V_TRP_NFAS 0x02 |
661 | #define V_TRP_RAL 0x04 |
662 | #define V_TRP_SA 0x08 |
663 | /* R_TX_FR1 */ |
664 | #define V_TX_FAS 0x01 |
665 | #define V_TX_NFAS 0x02 |
666 | #define V_TX_RAL 0x04 |
667 | #define V_TX_SA 0x08 |
668 | /* R_TX_FR2 */ |
669 | #define V_TX_MF 0x01 |
670 | #define V_TRP_SL0 0x02 |
671 | #define V_TX_SL0_RAM 0x04 |
672 | #define V_TX_E 0x10 |
673 | #define V_NEG_E 0x20 |
674 | #define V_XS12_ON 0x40 |
675 | #define V_XS15_ON 0x80 |
676 | /* R_RX_OFF */ |
677 | #define V_RX_SZ 0x01 |
678 | #define V_RX_INIT 0x04 |
679 | /* R_SYNC_OUT */ |
680 | #define V_SYNC_E1_RX 0x01 |
681 | #define V_IPATS0 0x20 |
682 | #define V_IPATS1 0x40 |
683 | #define V_IPATS2 0x80 |
684 | /* R_TX_OFF */ |
685 | #define V_TX_SZ 0x01 |
686 | #define V_TX_INIT 0x04 |
687 | /* R_SYNC_CTRL */ |
688 | #define V_EXT_CLK_SYNC 0x01 |
689 | #define V_SYNC_OFFS 0x02 |
690 | #define V_PCM_SYNC 0x04 |
691 | #define V_NEG_CLK 0x08 |
692 | #define V_HCLK 0x10 |
693 | /* |
694 | #define V_JATT_AUTO_DEL 0x20 |
695 | #define V_JATT_AUTO 0x40 |
696 | */ |
697 | #define V_JATT_OFF 0x80 |
698 | /* R_STATE */ |
699 | #define V_E1_STA 0x01 |
700 | #define V_ALT_FR_RX 0x40 |
701 | #define V_ALT_FR_TX 0x80 |
702 | /* R_SYNC_STA */ |
703 | #define V_RX_STA 0x01 |
704 | #define V_FR_SYNC_E1 0x04 |
705 | #define V_SIG_LOS 0x08 |
706 | #define V_MFA_STA 0x10 |
707 | #define V_AIS 0x40 |
708 | #define V_NO_MF_SYNC 0x80 |
709 | /* R_RX_SL0_0 */ |
710 | #define V_SI_FAS 0x01 |
711 | #define V_SI_NFAS 0x02 |
712 | #define V_A 0x04 |
713 | #define V_CRC_OK 0x08 |
714 | #define V_TX_E1 0x10 |
715 | #define V_TX_E2 0x20 |
716 | #define V_RX_E1 0x40 |
717 | #define V_RX_E2 0x80 |
718 | /* R_SLIP */ |
719 | #define V_SLIP_RX 0x01 |
720 | #define V_FOSLIP_RX 0x08 |
721 | #define V_SLIP_TX 0x10 |
722 | #define V_FOSLIP_TX 0x80 |
723 | |
724 | /* chapter 6: PCM interface */ |
725 | /* R_PCM_MD0 */ |
726 | #define V_PCM_MD 0x01 |
727 | #define V_C4_POL 0x02 |
728 | #define V_F0_NEG 0x04 |
729 | #define V_F0_LEN 0x08 |
730 | #define V_PCM_ADDR 0x10 |
731 | /* R_SL_SEL0 */ |
732 | #define V_SL_SEL0 0x01 |
733 | #define V_SH_SEL0 0x80 |
734 | /* R_SL_SEL1 */ |
735 | #define V_SL_SEL1 0x01 |
736 | #define V_SH_SEL1 0x80 |
737 | /* R_SL_SEL2 */ |
738 | #define V_SL_SEL2 0x01 |
739 | #define V_SH_SEL2 0x80 |
740 | /* R_SL_SEL3 */ |
741 | #define V_SL_SEL3 0x01 |
742 | #define V_SH_SEL3 0x80 |
743 | /* R_SL_SEL4 */ |
744 | #define V_SL_SEL4 0x01 |
745 | #define V_SH_SEL4 0x80 |
746 | /* R_SL_SEL5 */ |
747 | #define V_SL_SEL5 0x01 |
748 | #define V_SH_SEL5 0x80 |
749 | /* R_SL_SEL6 */ |
750 | #define V_SL_SEL6 0x01 |
751 | #define V_SH_SEL6 0x80 |
752 | /* R_SL_SEL7 */ |
753 | #define V_SL_SEL7 0x01 |
754 | #define V_SH_SEL7 0x80 |
755 | /* R_PCM_MD1 */ |
756 | #define V_ODEC_CON 0x01 |
757 | #define V_PLL_ADJ 0x04 |
758 | #define V_PCM_DR 0x10 |
759 | #define V_PCM_LOOP 0x40 |
760 | /* R_PCM_MD2 */ |
761 | #define V_SYNC_PLL 0x02 |
762 | #define V_SYNC_SRC 0x04 |
763 | #define V_SYNC_OUT 0x08 |
764 | #define V_ICR_FR_TIME 0x40 |
765 | #define V_EN_PLL 0x80 |
766 | |
767 | /* chapter 7: pulse width modulation */ |
768 | /* R_PWM_MD */ |
769 | #define V_EXT_IRQ_EN 0x08 |
770 | #define V_PWM0_MD 0x10 |
771 | #define V_PWM1_MD 0x40 |
772 | |
773 | /* chapter 8: multiparty audio conferences */ |
774 | /* R_CONF_EN */ |
775 | #define V_CONF_EN 0x01 |
776 | #define V_ULAW 0x80 |
777 | /* A_CONF */ |
778 | #define V_CONF_NUM 0x01 |
779 | #define V_NOISE_SUPPR 0x08 |
780 | #define V_ATT_LEV 0x20 |
781 | #define V_CONF_SL 0x80 |
782 | /* R_CONF_OFLOW */ |
783 | #define V_CONF_OFLOW0 0x01 |
784 | #define V_CONF_OFLOW1 0x02 |
785 | #define V_CONF_OFLOW2 0x04 |
786 | #define V_CONF_OFLOW3 0x08 |
787 | #define V_CONF_OFLOW4 0x10 |
788 | #define V_CONF_OFLOW5 0x20 |
789 | #define V_CONF_OFLOW6 0x40 |
790 | #define V_CONF_OFLOW7 0x80 |
791 | |
792 | /* chapter 9: DTMF contoller */ |
793 | /* R_DTMF0 */ |
794 | #define V_DTMF_EN 0x01 |
795 | #define V_HARM_SEL 0x02 |
796 | #define V_DTMF_RX_CH 0x04 |
797 | #define V_DTMF_STOP 0x08 |
798 | #define V_CHBL_SEL 0x10 |
799 | #define V_RST_DTMF 0x40 |
800 | #define V_ULAW_SEL 0x80 |
801 | |
802 | /* chapter 10: BERT */ |
803 | /* R_BERT_WD_MD */ |
804 | #define V_PAT_SEQ 0x01 |
805 | #define V_BERT_ERR 0x08 |
806 | #define V_AUTO_WD_RES 0x20 |
807 | #define V_WD_RES 0x80 |
808 | /* R_BERT_STA */ |
809 | #define V_BERT_SYNC_SRC 0x01 |
810 | #define V_BERT_SYNC 0x10 |
811 | #define V_BERT_INV_DATA 0x20 |
812 | |
813 | /* chapter 11: auxiliary interface */ |
814 | /* R_BRG_PCM_CFG */ |
815 | #define V_BRG_EN 0x01 |
816 | #define V_BRG_MD 0x02 |
817 | #define V_PCM_CLK 0x20 |
818 | #define V_ADDR_WRDLY 0x40 |
819 | /* R_BRG_CTRL */ |
820 | #define V_BRG_CS 0x01 |
821 | #define V_BRG_ADDR 0x08 |
822 | #define V_BRG_CS_SRC 0x80 |
823 | /* R_BRG_MD */ |
824 | #define V_BRG_MD0 0x01 |
825 | #define V_BRG_MD1 0x02 |
826 | #define V_BRG_MD2 0x04 |
827 | #define V_BRG_MD3 0x08 |
828 | #define V_BRG_MD4 0x10 |
829 | #define V_BRG_MD5 0x20 |
830 | #define V_BRG_MD6 0x40 |
831 | #define V_BRG_MD7 0x80 |
832 | /* R_BRG_TIM0 */ |
833 | #define V_BRG_TIM0_IDLE 0x01 |
834 | #define V_BRG_TIM0_CLK 0x10 |
835 | /* R_BRG_TIM1 */ |
836 | #define V_BRG_TIM1_IDLE 0x01 |
837 | #define V_BRG_TIM1_CLK 0x10 |
838 | /* R_BRG_TIM2 */ |
839 | #define V_BRG_TIM2_IDLE 0x01 |
840 | #define V_BRG_TIM2_CLK 0x10 |
841 | /* R_BRG_TIM3 */ |
842 | #define V_BRG_TIM3_IDLE 0x01 |
843 | #define V_BRG_TIM3_CLK 0x10 |
844 | /* R_BRG_TIM_SEL01 */ |
845 | #define V_BRG_WR_SEL0 0x01 |
846 | #define V_BRG_RD_SEL0 0x04 |
847 | #define V_BRG_WR_SEL1 0x10 |
848 | #define V_BRG_RD_SEL1 0x40 |
849 | /* R_BRG_TIM_SEL23 */ |
850 | #define V_BRG_WR_SEL2 0x01 |
851 | #define V_BRG_RD_SEL2 0x04 |
852 | #define V_BRG_WR_SEL3 0x10 |
853 | #define V_BRG_RD_SEL3 0x40 |
854 | /* R_BRG_TIM_SEL45 */ |
855 | #define V_BRG_WR_SEL4 0x01 |
856 | #define V_BRG_RD_SEL4 0x04 |
857 | #define V_BRG_WR_SEL5 0x10 |
858 | #define V_BRG_RD_SEL5 0x40 |
859 | /* R_BRG_TIM_SEL67 */ |
860 | #define V_BRG_WR_SEL6 0x01 |
861 | #define V_BRG_RD_SEL6 0x04 |
862 | #define V_BRG_WR_SEL7 0x10 |
863 | #define V_BRG_RD_SEL7 0x40 |
864 | |
865 | /* chapter 12: clock, reset, interrupt, timer and watchdog */ |
866 | /* R_IRQMSK_MISC */ |
867 | #define V_STA_IRQMSK 0x01 |
868 | #define V_TI_IRQMSK 0x02 |
869 | #define V_PROC_IRQMSK 0x04 |
870 | #define V_DTMF_IRQMSK 0x08 |
871 | #define V_IRQ1S_MSK 0x10 |
872 | #define V_SA6_IRQMSK 0x20 |
873 | #define V_RX_EOMF_MSK 0x40 |
874 | #define V_TX_EOMF_MSK 0x80 |
875 | /* R_IRQ_CTRL */ |
876 | #define V_FIFO_IRQ 0x01 |
877 | #define V_GLOB_IRQ_EN 0x08 |
878 | #define V_IRQ_POL 0x10 |
879 | /* R_TI_WD */ |
880 | #define V_EV_TS 0x01 |
881 | #define V_WD_TS 0x10 |
882 | /* A_IRQ_MSK */ |
883 | #define V_IRQ 0x01 |
884 | #define V_BERT_EN 0x02 |
885 | #define V_MIX_IRQ 0x04 |
886 | /* R_IRQ_OVIEW */ |
887 | #define V_IRQ_FIFO_BL0 0x01 |
888 | #define V_IRQ_FIFO_BL1 0x02 |
889 | #define V_IRQ_FIFO_BL2 0x04 |
890 | #define V_IRQ_FIFO_BL3 0x08 |
891 | #define V_IRQ_FIFO_BL4 0x10 |
892 | #define V_IRQ_FIFO_BL5 0x20 |
893 | #define V_IRQ_FIFO_BL6 0x40 |
894 | #define V_IRQ_FIFO_BL7 0x80 |
895 | /* R_IRQ_MISC */ |
896 | #define V_STA_IRQ 0x01 |
897 | #define V_TI_IRQ 0x02 |
898 | #define V_IRQ_PROC 0x04 |
899 | #define V_DTMF_IRQ 0x08 |
900 | #define V_IRQ1S 0x10 |
901 | #define V_SA6_IRQ 0x20 |
902 | #define V_RX_EOMF 0x40 |
903 | #define V_TX_EOMF 0x80 |
904 | /* R_STATUS */ |
905 | #define V_BUSY 0x01 |
906 | #define V_PROC 0x02 |
907 | #define V_DTMF_STA 0x04 |
908 | #define V_LOST_STA 0x08 |
909 | #define V_SYNC_IN 0x10 |
910 | #define V_EXT_IRQSTA 0x20 |
911 | #define V_MISC_IRQSTA 0x40 |
912 | #define V_FR_IRQSTA 0x80 |
913 | /* R_IRQ_FIFO_BL0 */ |
914 | #define V_IRQ_FIFO0_TX 0x01 |
915 | #define V_IRQ_FIFO0_RX 0x02 |
916 | #define V_IRQ_FIFO1_TX 0x04 |
917 | #define V_IRQ_FIFO1_RX 0x08 |
918 | #define V_IRQ_FIFO2_TX 0x10 |
919 | #define V_IRQ_FIFO2_RX 0x20 |
920 | #define V_IRQ_FIFO3_TX 0x40 |
921 | #define V_IRQ_FIFO3_RX 0x80 |
922 | /* R_IRQ_FIFO_BL1 */ |
923 | #define V_IRQ_FIFO4_TX 0x01 |
924 | #define V_IRQ_FIFO4_RX 0x02 |
925 | #define V_IRQ_FIFO5_TX 0x04 |
926 | #define V_IRQ_FIFO5_RX 0x08 |
927 | #define V_IRQ_FIFO6_TX 0x10 |
928 | #define V_IRQ_FIFO6_RX 0x20 |
929 | #define V_IRQ_FIFO7_TX 0x40 |
930 | #define V_IRQ_FIFO7_RX 0x80 |
931 | /* R_IRQ_FIFO_BL2 */ |
932 | #define V_IRQ_FIFO8_TX 0x01 |
933 | #define V_IRQ_FIFO8_RX 0x02 |
934 | #define V_IRQ_FIFO9_TX 0x04 |
935 | #define V_IRQ_FIFO9_RX 0x08 |
936 | #define V_IRQ_FIFO10_TX 0x10 |
937 | #define V_IRQ_FIFO10_RX 0x20 |
938 | #define V_IRQ_FIFO11_TX 0x40 |
939 | #define V_IRQ_FIFO11_RX 0x80 |
940 | /* R_IRQ_FIFO_BL3 */ |
941 | #define V_IRQ_FIFO12_TX 0x01 |
942 | #define V_IRQ_FIFO12_RX 0x02 |
943 | #define V_IRQ_FIFO13_TX 0x04 |
944 | #define V_IRQ_FIFO13_RX 0x08 |
945 | #define V_IRQ_FIFO14_TX 0x10 |
946 | #define V_IRQ_FIFO14_RX 0x20 |
947 | #define V_IRQ_FIFO15_TX 0x40 |
948 | #define V_IRQ_FIFO15_RX 0x80 |
949 | /* R_IRQ_FIFO_BL4 */ |
950 | #define V_IRQ_FIFO16_TX 0x01 |
951 | #define V_IRQ_FIFO16_RX 0x02 |
952 | #define V_IRQ_FIFO17_TX 0x04 |
953 | #define V_IRQ_FIFO17_RX 0x08 |
954 | #define V_IRQ_FIFO18_TX 0x10 |
955 | #define V_IRQ_FIFO18_RX 0x20 |
956 | #define V_IRQ_FIFO19_TX 0x40 |
957 | #define V_IRQ_FIFO19_RX 0x80 |
958 | /* R_IRQ_FIFO_BL5 */ |
959 | #define V_IRQ_FIFO20_TX 0x01 |
960 | #define V_IRQ_FIFO20_RX 0x02 |
961 | #define V_IRQ_FIFO21_TX 0x04 |
962 | #define V_IRQ_FIFO21_RX 0x08 |
963 | #define V_IRQ_FIFO22_TX 0x10 |
964 | #define V_IRQ_FIFO22_RX 0x20 |
965 | #define V_IRQ_FIFO23_TX 0x40 |
966 | #define V_IRQ_FIFO23_RX 0x80 |
967 | /* R_IRQ_FIFO_BL6 */ |
968 | #define V_IRQ_FIFO24_TX 0x01 |
969 | #define V_IRQ_FIFO24_RX 0x02 |
970 | #define V_IRQ_FIFO25_TX 0x04 |
971 | #define V_IRQ_FIFO25_RX 0x08 |
972 | #define V_IRQ_FIFO26_TX 0x10 |
973 | #define V_IRQ_FIFO26_RX 0x20 |
974 | #define V_IRQ_FIFO27_TX 0x40 |
975 | #define V_IRQ_FIFO27_RX 0x80 |
976 | /* R_IRQ_FIFO_BL7 */ |
977 | #define V_IRQ_FIFO28_TX 0x01 |
978 | #define V_IRQ_FIFO28_RX 0x02 |
979 | #define V_IRQ_FIFO29_TX 0x04 |
980 | #define V_IRQ_FIFO29_RX 0x08 |
981 | #define V_IRQ_FIFO30_TX 0x10 |
982 | #define V_IRQ_FIFO30_RX 0x20 |
983 | #define V_IRQ_FIFO31_TX 0x40 |
984 | #define V_IRQ_FIFO31_RX 0x80 |
985 | |
986 | /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */ |
987 | /* R_GPIO_OUT0 */ |
988 | #define V_GPIO_OUT0 0x01 |
989 | #define V_GPIO_OUT1 0x02 |
990 | #define V_GPIO_OUT2 0x04 |
991 | #define V_GPIO_OUT3 0x08 |
992 | #define V_GPIO_OUT4 0x10 |
993 | #define V_GPIO_OUT5 0x20 |
994 | #define V_GPIO_OUT6 0x40 |
995 | #define V_GPIO_OUT7 0x80 |
996 | /* R_GPIO_OUT1 */ |
997 | #define V_GPIO_OUT8 0x01 |
998 | #define V_GPIO_OUT9 0x02 |
999 | #define V_GPIO_OUT10 0x04 |
1000 | #define V_GPIO_OUT11 0x08 |
1001 | #define V_GPIO_OUT12 0x10 |
1002 | #define V_GPIO_OUT13 0x20 |
1003 | #define V_GPIO_OUT14 0x40 |
1004 | #define V_GPIO_OUT15 0x80 |
1005 | /* R_GPIO_EN0 */ |
1006 | #define V_GPIO_EN0 0x01 |
1007 | #define V_GPIO_EN1 0x02 |
1008 | #define V_GPIO_EN2 0x04 |
1009 | #define V_GPIO_EN3 0x08 |
1010 | #define V_GPIO_EN4 0x10 |
1011 | #define V_GPIO_EN5 0x20 |
1012 | #define V_GPIO_EN6 0x40 |
1013 | #define V_GPIO_EN7 0x80 |
1014 | /* R_GPIO_EN1 */ |
1015 | #define V_GPIO_EN8 0x01 |
1016 | #define V_GPIO_EN9 0x02 |
1017 | #define V_GPIO_EN10 0x04 |
1018 | #define V_GPIO_EN11 0x08 |
1019 | #define V_GPIO_EN12 0x10 |
1020 | #define V_GPIO_EN13 0x20 |
1021 | #define V_GPIO_EN14 0x40 |
1022 | #define V_GPIO_EN15 0x80 |
1023 | /* R_GPIO_SEL */ |
1024 | #define V_GPIO_SEL0 0x01 |
1025 | #define V_GPIO_SEL1 0x02 |
1026 | #define V_GPIO_SEL2 0x04 |
1027 | #define V_GPIO_SEL3 0x08 |
1028 | #define V_GPIO_SEL4 0x10 |
1029 | #define V_GPIO_SEL5 0x20 |
1030 | #define V_GPIO_SEL6 0x40 |
1031 | #define V_GPIO_SEL7 0x80 |
1032 | /* R_GPIO_IN0 */ |
1033 | #define V_GPIO_IN0 0x01 |
1034 | #define V_GPIO_IN1 0x02 |
1035 | #define V_GPIO_IN2 0x04 |
1036 | #define V_GPIO_IN3 0x08 |
1037 | #define V_GPIO_IN4 0x10 |
1038 | #define V_GPIO_IN5 0x20 |
1039 | #define V_GPIO_IN6 0x40 |
1040 | #define V_GPIO_IN7 0x80 |
1041 | /* R_GPIO_IN1 */ |
1042 | #define V_GPIO_IN8 0x01 |
1043 | #define V_GPIO_IN9 0x02 |
1044 | #define V_GPIO_IN10 0x04 |
1045 | #define V_GPIO_IN11 0x08 |
1046 | #define V_GPIO_IN12 0x10 |
1047 | #define V_GPIO_IN13 0x20 |
1048 | #define V_GPIO_IN14 0x40 |
1049 | #define V_GPIO_IN15 0x80 |
1050 | /* R_GPI_IN0 */ |
1051 | #define V_GPI_IN0 0x01 |
1052 | #define V_GPI_IN1 0x02 |
1053 | #define V_GPI_IN2 0x04 |
1054 | #define V_GPI_IN3 0x08 |
1055 | #define V_GPI_IN4 0x10 |
1056 | #define V_GPI_IN5 0x20 |
1057 | #define V_GPI_IN6 0x40 |
1058 | #define V_GPI_IN7 0x80 |
1059 | /* R_GPI_IN1 */ |
1060 | #define V_GPI_IN8 0x01 |
1061 | #define V_GPI_IN9 0x02 |
1062 | #define V_GPI_IN10 0x04 |
1063 | #define V_GPI_IN11 0x08 |
1064 | #define V_GPI_IN12 0x10 |
1065 | #define V_GPI_IN13 0x20 |
1066 | #define V_GPI_IN14 0x40 |
1067 | #define V_GPI_IN15 0x80 |
1068 | /* R_GPI_IN2 */ |
1069 | #define V_GPI_IN16 0x01 |
1070 | #define V_GPI_IN17 0x02 |
1071 | #define V_GPI_IN18 0x04 |
1072 | #define V_GPI_IN19 0x08 |
1073 | #define V_GPI_IN20 0x10 |
1074 | #define V_GPI_IN21 0x20 |
1075 | #define V_GPI_IN22 0x40 |
1076 | #define V_GPI_IN23 0x80 |
1077 | /* R_GPI_IN3 */ |
1078 | #define V_GPI_IN24 0x01 |
1079 | #define V_GPI_IN25 0x02 |
1080 | #define V_GPI_IN26 0x04 |
1081 | #define V_GPI_IN27 0x08 |
1082 | #define V_GPI_IN28 0x10 |
1083 | #define V_GPI_IN29 0x20 |
1084 | #define V_GPI_IN30 0x40 |
1085 | #define V_GPI_IN31 0x80 |
1086 | |
1087 | /* map of all registers, used for debugging */ |
1088 | |
1089 | #ifdef HFC_REGISTER_DEBUG |
1090 | struct hfc_register_names { |
1091 | char *name; |
1092 | u_char reg; |
1093 | } hfc_register_names[] = { |
1094 | /* write registers */ |
1095 | {"R_CIRM" , 0x00}, |
1096 | {"R_CTRL" , 0x01}, |
1097 | {"R_BRG_PCM_CFG " , 0x02}, |
1098 | {"R_RAM_ADDR0" , 0x08}, |
1099 | {"R_RAM_ADDR1" , 0x09}, |
1100 | {"R_RAM_ADDR2" , 0x0A}, |
1101 | {"R_FIRST_FIFO" , 0x0B}, |
1102 | {"R_RAM_SZ" , 0x0C}, |
1103 | {"R_FIFO_MD" , 0x0D}, |
1104 | {"R_INC_RES_FIFO" , 0x0E}, |
1105 | {"R_FIFO / R_FSM_IDX" , 0x0F}, |
1106 | {"R_SLOT" , 0x10}, |
1107 | {"R_IRQMSK_MISC" , 0x11}, |
1108 | {"R_SCI_MSK" , 0x12}, |
1109 | {"R_IRQ_CTRL" , 0x13}, |
1110 | {"R_PCM_MD0" , 0x14}, |
1111 | {"R_0x15" , 0x15}, |
1112 | {"R_ST_SEL" , 0x16}, |
1113 | {"R_ST_SYNC" , 0x17}, |
1114 | {"R_CONF_EN" , 0x18}, |
1115 | {"R_TI_WD" , 0x1A}, |
1116 | {"R_BERT_WD_MD" , 0x1B}, |
1117 | {"R_DTMF" , 0x1C}, |
1118 | {"R_DTMF_N" , 0x1D}, |
1119 | {"R_E1_XX_STA" , 0x20}, |
1120 | {"R_LOS0" , 0x22}, |
1121 | {"R_LOS1" , 0x23}, |
1122 | {"R_RX0" , 0x24}, |
1123 | {"R_RX_FR0" , 0x25}, |
1124 | {"R_RX_FR1" , 0x26}, |
1125 | {"R_TX0" , 0x28}, |
1126 | {"R_TX1" , 0x29}, |
1127 | {"R_TX_FR0" , 0x2C}, |
1128 | {"R_TX_FR1" , 0x2D}, |
1129 | {"R_TX_FR2" , 0x2E}, |
1130 | {"R_JATT_ATT" , 0x2F}, |
1131 | {"A_ST_xx_STA/R_RX_OFF" , 0x30}, |
1132 | {"A_ST_CTRL0/R_SYNC_OUT" , 0x31}, |
1133 | {"A_ST_CTRL1" , 0x32}, |
1134 | {"A_ST_CTRL2" , 0x33}, |
1135 | {"A_ST_SQ_WR" , 0x34}, |
1136 | {"R_TX_OFF" , 0x34}, |
1137 | {"R_SYNC_CTRL" , 0x35}, |
1138 | {"A_ST_CLK_DLY" , 0x37}, |
1139 | {"R_PWM0" , 0x38}, |
1140 | {"R_PWM1" , 0x39}, |
1141 | {"A_ST_B1_TX" , 0x3C}, |
1142 | {"A_ST_B2_TX" , 0x3D}, |
1143 | {"A_ST_D_TX" , 0x3E}, |
1144 | {"R_GPIO_OUT0" , 0x40}, |
1145 | {"R_GPIO_OUT1" , 0x41}, |
1146 | {"R_GPIO_EN0" , 0x42}, |
1147 | {"R_GPIO_EN1" , 0x43}, |
1148 | {"R_GPIO_SEL" , 0x44}, |
1149 | {"R_BRG_CTRL" , 0x45}, |
1150 | {"R_PWM_MD" , 0x46}, |
1151 | {"R_BRG_MD" , 0x47}, |
1152 | {"R_BRG_TIM0" , 0x48}, |
1153 | {"R_BRG_TIM1" , 0x49}, |
1154 | {"R_BRG_TIM2" , 0x4A}, |
1155 | {"R_BRG_TIM3" , 0x4B}, |
1156 | {"R_BRG_TIM_SEL01" , 0x4C}, |
1157 | {"R_BRG_TIM_SEL23" , 0x4D}, |
1158 | {"R_BRG_TIM_SEL45" , 0x4E}, |
1159 | {"R_BRG_TIM_SEL67" , 0x4F}, |
1160 | {"A_FIFO_DATA0-2" , 0x80}, |
1161 | {"A_FIFO_DATA0-2_NOINC" , 0x84}, |
1162 | {"R_RAM_DATA" , 0xC0}, |
1163 | {"A_SL_CFG" , 0xD0}, |
1164 | {"A_CONF" , 0xD1}, |
1165 | {"A_CH_MSK" , 0xF4}, |
1166 | {"A_CON_HDLC" , 0xFA}, |
1167 | {"A_SUBCH_CFG" , 0xFB}, |
1168 | {"A_CHANNEL" , 0xFC}, |
1169 | {"A_FIFO_SEQ" , 0xFD}, |
1170 | {"A_IRQ_MSK" , 0xFF}, |
1171 | {NULL, 0}, |
1172 | |
1173 | /* read registers */ |
1174 | {"A_Z1" , 0x04}, |
1175 | {"A_Z1H" , 0x05}, |
1176 | {"A_Z2" , 0x06}, |
1177 | {"A_Z2H" , 0x07}, |
1178 | {"A_F1" , 0x0C}, |
1179 | {"A_F2" , 0x0D}, |
1180 | {"R_IRQ_OVIEW" , 0x10}, |
1181 | {"R_IRQ_MISC" , 0x11}, |
1182 | {"R_IRQ_STATECH" , 0x12}, |
1183 | {"R_CONF_OFLOW" , 0x14}, |
1184 | {"R_RAM_USE" , 0x15}, |
1185 | {"R_CHIP_ID" , 0x16}, |
1186 | {"R_BERT_STA" , 0x17}, |
1187 | {"R_F0_CNTL" , 0x18}, |
1188 | {"R_F0_CNTH" , 0x19}, |
1189 | {"R_BERT_ECL" , 0x1A}, |
1190 | {"R_BERT_ECH" , 0x1B}, |
1191 | {"R_STATUS" , 0x1C}, |
1192 | {"R_CHIP_RV" , 0x1F}, |
1193 | {"R_STATE" , 0x20}, |
1194 | {"R_SYNC_STA" , 0x24}, |
1195 | {"R_RX_SL0_0" , 0x25}, |
1196 | {"R_RX_SL0_1" , 0x26}, |
1197 | {"R_RX_SL0_2" , 0x27}, |
1198 | {"R_JATT_DIR" , 0x2b}, |
1199 | {"R_SLIP" , 0x2c}, |
1200 | {"A_ST_RD_STA" , 0x30}, |
1201 | {"R_FAS_ECL" , 0x30}, |
1202 | {"R_FAS_ECH" , 0x31}, |
1203 | {"R_VIO_ECL" , 0x32}, |
1204 | {"R_VIO_ECH" , 0x33}, |
1205 | {"R_CRC_ECL / A_ST_SQ_RD" , 0x34}, |
1206 | {"R_CRC_ECH" , 0x35}, |
1207 | {"R_E_ECL" , 0x36}, |
1208 | {"R_E_ECH" , 0x37}, |
1209 | {"R_SA6_SA13_ECL" , 0x38}, |
1210 | {"R_SA6_SA13_ECH" , 0x39}, |
1211 | {"R_SA6_SA23_ECL" , 0x3A}, |
1212 | {"R_SA6_SA23_ECH" , 0x3B}, |
1213 | {"A_ST_B1_RX" , 0x3C}, |
1214 | {"A_ST_B2_RX" , 0x3D}, |
1215 | {"A_ST_D_RX" , 0x3E}, |
1216 | {"A_ST_E_RX" , 0x3F}, |
1217 | {"R_GPIO_IN0" , 0x40}, |
1218 | {"R_GPIO_IN1" , 0x41}, |
1219 | {"R_GPI_IN0" , 0x44}, |
1220 | {"R_GPI_IN1" , 0x45}, |
1221 | {"R_GPI_IN2" , 0x46}, |
1222 | {"R_GPI_IN3" , 0x47}, |
1223 | {"A_FIFO_DATA0-2" , 0x80}, |
1224 | {"A_FIFO_DATA0-2_NOINC" , 0x84}, |
1225 | {"R_INT_DATA" , 0x88}, |
1226 | {"R_RAM_DATA" , 0xC0}, |
1227 | {"R_IRQ_FIFO_BL0" , 0xC8}, |
1228 | {"R_IRQ_FIFO_BL1" , 0xC9}, |
1229 | {"R_IRQ_FIFO_BL2" , 0xCA}, |
1230 | {"R_IRQ_FIFO_BL3" , 0xCB}, |
1231 | {"R_IRQ_FIFO_BL4" , 0xCC}, |
1232 | {"R_IRQ_FIFO_BL5" , 0xCD}, |
1233 | {"R_IRQ_FIFO_BL6" , 0xCE}, |
1234 | {"R_IRQ_FIFO_BL7" , 0xCF}, |
1235 | }; |
1236 | #endif /* HFC_REGISTER_DEBUG */ |
1237 | |