1/*
2 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
3 *
4 * Authors: Inha Song <ideal.song@samsung.com>
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * Samsung Exynos SoC series Low Power Audio Subsystem driver.
8 *
9 * This module provides regmap for the Top SFR region and instantiates
10 * devices for IP blocks like DMAC, I2S, UART.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 and
14 * only version 2 as published by the Free Software Foundation.
15 */
16
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/mfd/syscon.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/regmap.h>
27#include <linux/soc/samsung/exynos-regs-pmu.h>
28#include <linux/types.h>
29
30/* LPASS Top register definitions */
31#define SFR_LPASS_CORE_SW_RESET 0x08
32#define LPASS_SB_SW_RESET BIT(11)
33#define LPASS_UART_SW_RESET BIT(10)
34#define LPASS_PCM_SW_RESET BIT(9)
35#define LPASS_I2S_SW_RESET BIT(8)
36#define LPASS_WDT1_SW_RESET BIT(4)
37#define LPASS_WDT0_SW_RESET BIT(3)
38#define LPASS_TIMER_SW_RESET BIT(2)
39#define LPASS_MEM_SW_RESET BIT(1)
40#define LPASS_DMA_SW_RESET BIT(0)
41
42#define SFR_LPASS_INTR_CA5_MASK 0x48
43#define SFR_LPASS_INTR_CPU_MASK 0x58
44#define LPASS_INTR_APM BIT(9)
45#define LPASS_INTR_MIF BIT(8)
46#define LPASS_INTR_TIMER BIT(7)
47#define LPASS_INTR_DMA BIT(6)
48#define LPASS_INTR_GPIO BIT(5)
49#define LPASS_INTR_I2S BIT(4)
50#define LPASS_INTR_PCM BIT(3)
51#define LPASS_INTR_SLIMBUS BIT(2)
52#define LPASS_INTR_UART BIT(1)
53#define LPASS_INTR_SFR BIT(0)
54
55struct exynos_lpass {
56 /* pointer to the LPASS TOP regmap */
57 struct regmap *top;
58 struct clk *sfr0_clk;
59};
60
61static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
62{
63 unsigned int val = 0;
64
65 regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
66
67 val &= ~mask;
68 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
69
70 usleep_range(100, 150);
71
72 val |= mask;
73 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
74}
75
76static void exynos_lpass_enable(struct exynos_lpass *lpass)
77{
78 clk_prepare_enable(lpass->sfr0_clk);
79
80 /* Unmask SFR, DMA and I2S interrupt */
81 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
82 LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
83
84 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
85 LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
86 LPASS_INTR_UART);
87
88 exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
89 exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
90 exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
91 exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
92}
93
94static void exynos_lpass_disable(struct exynos_lpass *lpass)
95{
96 /* Mask any unmasked IP interrupt sources */
97 regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
98 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
99
100 clk_disable_unprepare(lpass->sfr0_clk);
101}
102
103static const struct regmap_config exynos_lpass_reg_conf = {
104 .reg_bits = 32,
105 .reg_stride = 4,
106 .val_bits = 32,
107 .max_register = 0xfc,
108 .fast_io = true,
109};
110
111static int exynos_lpass_probe(struct platform_device *pdev)
112{
113 struct device *dev = &pdev->dev;
114 struct exynos_lpass *lpass;
115 void __iomem *base_top;
116 struct resource *res;
117
118 lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
119 if (!lpass)
120 return -ENOMEM;
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123 base_top = devm_ioremap_resource(dev, res);
124 if (IS_ERR(base_top))
125 return PTR_ERR(base_top);
126
127 lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
128 if (IS_ERR(lpass->sfr0_clk))
129 return PTR_ERR(lpass->sfr0_clk);
130
131 lpass->top = regmap_init_mmio(dev, base_top,
132 &exynos_lpass_reg_conf);
133 if (IS_ERR(lpass->top)) {
134 dev_err(dev, "LPASS top regmap initialization failed\n");
135 return PTR_ERR(lpass->top);
136 }
137
138 platform_set_drvdata(pdev, lpass);
139 pm_runtime_set_active(dev);
140 pm_runtime_enable(dev);
141 exynos_lpass_enable(lpass);
142
143 return devm_of_platform_populate(dev);
144}
145
146static int exynos_lpass_remove(struct platform_device *pdev)
147{
148 struct exynos_lpass *lpass = platform_get_drvdata(pdev);
149
150 exynos_lpass_disable(lpass);
151 pm_runtime_disable(&pdev->dev);
152 if (!pm_runtime_status_suspended(&pdev->dev))
153 exynos_lpass_disable(lpass);
154 regmap_exit(lpass->top);
155
156 return 0;
157}
158
159static int __maybe_unused exynos_lpass_suspend(struct device *dev)
160{
161 struct exynos_lpass *lpass = dev_get_drvdata(dev);
162
163 exynos_lpass_disable(lpass);
164
165 return 0;
166}
167
168static int __maybe_unused exynos_lpass_resume(struct device *dev)
169{
170 struct exynos_lpass *lpass = dev_get_drvdata(dev);
171
172 exynos_lpass_enable(lpass);
173
174 return 0;
175}
176
177static const struct dev_pm_ops lpass_pm_ops = {
178 SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
179 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
180 pm_runtime_force_resume)
181};
182
183static const struct of_device_id exynos_lpass_of_match[] = {
184 { .compatible = "samsung,exynos5433-lpass" },
185 { },
186};
187MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
188
189static struct platform_driver exynos_lpass_driver = {
190 .driver = {
191 .name = "exynos-lpass",
192 .pm = &lpass_pm_ops,
193 .of_match_table = exynos_lpass_of_match,
194 },
195 .probe = exynos_lpass_probe,
196 .remove = exynos_lpass_remove,
197};
198module_platform_driver(exynos_lpass_driver);
199
200MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
201MODULE_LICENSE("GPL v2");
202