1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Driver for Realtek PCI-Express card reader |
3 | * |
4 | * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. |
5 | * |
6 | * Author: |
7 | * Rui FENG <rui_feng@realsil.com.cn> |
8 | * Wei WANG <wei_wang@realsil.com.cn> |
9 | */ |
10 | #ifndef RTS5261_H |
11 | #define RTS5261_H |
12 | |
13 | /*New add*/ |
14 | #define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000) |
15 | #define rts5261_reg_to_aspm(reg) \ |
16 | (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01)) |
17 | #define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04) |
18 | #define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03) |
19 | #define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03) |
20 | #define rts5261_reg_to_rtd3(reg) ((reg) & 0x08) |
21 | #define rts5261_reg_check_mmc_support(reg) ((reg) & 0x10) |
22 | |
23 | #define RTS5261_AUTOLOAD_CFG0 0xFF7B |
24 | #define RTS5261_AUTOLOAD_CFG1 0xFF7C |
25 | #define RTS5261_AUTOLOAD_CFG2 0xFF7D |
26 | #define RTS5261_AUTOLOAD_CFG3 0xFF7E |
27 | #define RTS5261_AUTOLOAD_CFG4 0xFF7F |
28 | #define RTS5261_FORCE_PRSNT_LOW (1 << 6) |
29 | #define RTS5261_AUX_CLK_16M_EN (1 << 5) |
30 | |
31 | #define RTS5261_REG_VREF 0xFE97 |
32 | #define RTS5261_PWD_SUSPND_EN (1 << 4) |
33 | |
34 | #define RTS5261_PAD_H3L1 0xFF79 |
35 | #define PAD_GPIO_H3L1 (1 << 3) |
36 | |
37 | /* SSC_CTL2 0xFC12 */ |
38 | #define RTS5261_SSC_DEPTH_MASK 0x07 |
39 | #define RTS5261_SSC_DEPTH_DISALBE 0x00 |
40 | #define RTS5261_SSC_DEPTH_8M 0x01 |
41 | #define RTS5261_SSC_DEPTH_4M 0x02 |
42 | #define RTS5261_SSC_DEPTH_2M 0x03 |
43 | #define RTS5261_SSC_DEPTH_1M 0x04 |
44 | #define RTS5261_SSC_DEPTH_512K 0x05 |
45 | #define RTS5261_SSC_DEPTH_256K 0x06 |
46 | #define RTS5261_SSC_DEPTH_128K 0x07 |
47 | |
48 | /* efuse control register*/ |
49 | #define RTS5261_EFUSE_CTL 0xFC30 |
50 | #define RTS5261_EFUSE_ENABLE 0x80 |
51 | /* EFUSE_MODE: 0=READ 1=PROGRAM */ |
52 | #define RTS5261_EFUSE_MODE_MASK 0x40 |
53 | #define RTS5261_EFUSE_PROGRAM 0x40 |
54 | |
55 | #define RTS5261_EFUSE_ADDR 0xFC31 |
56 | #define RTS5261_EFUSE_ADDR_MASK 0x3F |
57 | |
58 | #define RTS5261_EFUSE_WRITE_DATA 0xFC32 |
59 | #define RTS5261_EFUSE_READ_DATA 0xFC34 |
60 | |
61 | /* DMACTL 0xFE2C */ |
62 | #define RTS5261_DMA_PACK_SIZE_MASK 0xF0 |
63 | |
64 | /* FW status register */ |
65 | #define RTS5261_FW_STATUS 0xFF56 |
66 | #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) |
67 | |
68 | /* FW control register */ |
69 | #define RTS5261_FW_CTL 0xFF5F |
70 | #define RTS5261_INFORM_RTD3_COLD (0x01<<5) |
71 | |
72 | #define RTS5261_REG_FPDCTL 0xFF60 |
73 | |
74 | #define RTS5261_REG_LDO12_CFG 0xFF6E |
75 | #define RTS5261_LDO12_VO_TUNE_MASK (0x07<<1) |
76 | #define RTS5261_LDO12_115 (0x03<<1) |
77 | #define RTS5261_LDO12_120 (0x04<<1) |
78 | #define RTS5261_LDO12_125 (0x05<<1) |
79 | #define RTS5261_LDO12_130 (0x06<<1) |
80 | #define RTS5261_LDO12_135 (0x07<<1) |
81 | |
82 | /* LDO control register */ |
83 | #define RTS5261_CARD_PWR_CTL 0xFD50 |
84 | #define RTS5261_SD_CLK_ISO (0x01<<7) |
85 | #define RTS5261_PAD_SD_DAT_FW_CTRL (0x01<<6) |
86 | #define RTS5261_PUPDC (0x01<<5) |
87 | #define RTS5261_SD_CMD_ISO (0x01<<4) |
88 | #define RTS5261_SD_DAT_ISO_MASK (0x0F<<0) |
89 | |
90 | #define RTS5261_LDO1233318_POW_CTL 0xFF70 |
91 | #define RTS5261_LDO3318_POWERON (0x01<<3) |
92 | #define RTS5261_LDO3_POWERON (0x01<<2) |
93 | #define RTS5261_LDO2_POWERON (0x01<<1) |
94 | #define RTS5261_LDO1_POWERON (0x01<<0) |
95 | #define RTS5261_LDO_POWERON_MASK (0x0F<<0) |
96 | |
97 | #define RTS5261_DV3318_CFG 0xFF71 |
98 | #define RTS5261_DV3318_TUNE_MASK (0x07<<4) |
99 | #define RTS5261_DV3318_18 (0x02<<4) |
100 | #define RTS5261_DV3318_19 (0x04<<4) |
101 | #define RTS5261_DV3318_33 (0x07<<4) |
102 | |
103 | /* CRD6603-433 190319 request changed */ |
104 | #define RTS5261_LDO1_OCP_THD_740 (0x00<<5) |
105 | #define RTS5261_LDO1_OCP_THD_800 (0x01<<5) |
106 | #define RTS5261_LDO1_OCP_THD_860 (0x02<<5) |
107 | #define RTS5261_LDO1_OCP_THD_920 (0x03<<5) |
108 | #define RTS5261_LDO1_OCP_THD_980 (0x04<<5) |
109 | #define RTS5261_LDO1_OCP_THD_1040 (0x05<<5) |
110 | #define RTS5261_LDO1_OCP_THD_1100 (0x06<<5) |
111 | #define RTS5261_LDO1_OCP_THD_1160 (0x07<<5) |
112 | |
113 | #define RTS5261_LDO1_LMT_THD_450 (0x00<<2) |
114 | #define RTS5261_LDO1_LMT_THD_1000 (0x01<<2) |
115 | #define RTS5261_LDO1_LMT_THD_1500 (0x02<<2) |
116 | #define RTS5261_LDO1_LMT_THD_2000 (0x03<<2) |
117 | |
118 | #define RTS5261_LDO1_CFG1 0xFF73 |
119 | #define RTS5261_LDO1_TUNE_MASK (0x07<<1) |
120 | #define RTS5261_LDO1_18 (0x05<<1) |
121 | #define RTS5261_LDO1_33 (0x07<<1) |
122 | #define RTS5261_LDO1_PWD_MASK (0x01<<0) |
123 | |
124 | #define RTS5261_LDO2_CFG0 0xFF74 |
125 | #define RTS5261_LDO2_OCP_THD_MASK (0x07<<5) |
126 | #define RTS5261_LDO2_OCP_EN (0x01<<4) |
127 | #define RTS5261_LDO2_OCP_LMT_THD_MASK (0x03<<2) |
128 | #define RTS5261_LDO2_OCP_LMT_EN (0x01<<1) |
129 | |
130 | #define RTS5261_LDO2_OCP_THD_620 (0x00<<5) |
131 | #define RTS5261_LDO2_OCP_THD_650 (0x01<<5) |
132 | #define RTS5261_LDO2_OCP_THD_680 (0x02<<5) |
133 | #define RTS5261_LDO2_OCP_THD_720 (0x03<<5) |
134 | #define RTS5261_LDO2_OCP_THD_750 (0x04<<5) |
135 | #define RTS5261_LDO2_OCP_THD_780 (0x05<<5) |
136 | #define RTS5261_LDO2_OCP_THD_810 (0x06<<5) |
137 | #define RTS5261_LDO2_OCP_THD_840 (0x07<<5) |
138 | |
139 | #define RTS5261_LDO2_CFG1 0xFF75 |
140 | #define RTS5261_LDO2_TUNE_MASK (0x07<<1) |
141 | #define RTS5261_LDO2_18 (0x05<<1) |
142 | #define RTS5261_LDO2_33 (0x07<<1) |
143 | #define RTS5261_LDO2_PWD_MASK (0x01<<0) |
144 | |
145 | #define RTS5261_LDO3_CFG0 0xFF76 |
146 | #define RTS5261_LDO3_OCP_THD_MASK (0x07<<5) |
147 | #define RTS5261_LDO3_OCP_EN (0x01<<4) |
148 | #define RTS5261_LDO3_OCP_LMT_THD_MASK (0x03<<2) |
149 | #define RTS5261_LDO3_OCP_LMT_EN (0x01<<1) |
150 | |
151 | #define RTS5261_LDO3_OCP_THD_620 (0x00<<5) |
152 | #define RTS5261_LDO3_OCP_THD_650 (0x01<<5) |
153 | #define RTS5261_LDO3_OCP_THD_680 (0x02<<5) |
154 | #define RTS5261_LDO3_OCP_THD_720 (0x03<<5) |
155 | #define RTS5261_LDO3_OCP_THD_750 (0x04<<5) |
156 | #define RTS5261_LDO3_OCP_THD_780 (0x05<<5) |
157 | #define RTS5261_LDO3_OCP_THD_810 (0x06<<5) |
158 | #define RTS5261_LDO3_OCP_THD_840 (0x07<<5) |
159 | |
160 | #define RTS5261_LDO3_CFG1 0xFF77 |
161 | #define RTS5261_LDO3_TUNE_MASK (0x07<<1) |
162 | #define RTS5261_LDO3_18 (0x05<<1) |
163 | #define RTS5261_LDO3_33 (0x07<<1) |
164 | #define RTS5261_LDO3_PWD_MASK (0x01<<0) |
165 | |
166 | #define RTS5261_REG_PME_FORCE_CTL 0xFF78 |
167 | #define FORCE_PM_CONTROL 0x20 |
168 | #define FORCE_PM_VALUE 0x10 |
169 | #define REG_EFUSE_BYPASS 0x08 |
170 | #define REG_EFUSE_POR 0x04 |
171 | #define REG_EFUSE_POWER_MASK 0x03 |
172 | #define REG_EFUSE_POWERON 0x03 |
173 | #define REG_EFUSE_POWEROFF 0x00 |
174 | |
175 | |
176 | /* Single LUN, support SD/SD EXPRESS */ |
177 | #define DEFAULT_SINGLE 0 |
178 | #define SD_LUN 1 |
179 | #define SD_EXPRESS_LUN 2 |
180 | |
181 | /* For Change_FPGA_SSCClock Function */ |
182 | #define MULTIPLY_BY_1 0x00 |
183 | #define MULTIPLY_BY_2 0x01 |
184 | #define MULTIPLY_BY_3 0x02 |
185 | #define MULTIPLY_BY_4 0x03 |
186 | #define MULTIPLY_BY_5 0x04 |
187 | #define MULTIPLY_BY_6 0x05 |
188 | #define MULTIPLY_BY_7 0x06 |
189 | #define MULTIPLY_BY_8 0x07 |
190 | #define MULTIPLY_BY_9 0x08 |
191 | #define MULTIPLY_BY_10 0x09 |
192 | |
193 | #define DIVIDE_BY_2 0x01 |
194 | #define DIVIDE_BY_3 0x02 |
195 | #define DIVIDE_BY_4 0x03 |
196 | #define DIVIDE_BY_5 0x04 |
197 | #define DIVIDE_BY_6 0x05 |
198 | #define DIVIDE_BY_7 0x06 |
199 | #define DIVIDE_BY_8 0x07 |
200 | #define DIVIDE_BY_9 0x08 |
201 | #define DIVIDE_BY_10 0x09 |
202 | |
203 | int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, |
204 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); |
205 | |
206 | #endif /* RTS5261_H */ |
207 | |