1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright 2014 IBM Corp. |
4 | */ |
5 | |
6 | #ifndef _CXL_H_ |
7 | #define _CXL_H_ |
8 | |
9 | #include <linux/interrupt.h> |
10 | #include <linux/semaphore.h> |
11 | #include <linux/device.h> |
12 | #include <linux/types.h> |
13 | #include <linux/cdev.h> |
14 | #include <linux/pid.h> |
15 | #include <linux/io.h> |
16 | #include <linux/pci.h> |
17 | #include <linux/fs.h> |
18 | #include <asm/cputable.h> |
19 | #include <asm/mmu.h> |
20 | #include <asm/reg.h> |
21 | #include <misc/cxl-base.h> |
22 | |
23 | #include <misc/cxl.h> |
24 | #include <uapi/misc/cxl.h> |
25 | |
26 | extern uint cxl_verbose; |
27 | |
28 | struct property; |
29 | |
30 | #define CXL_TIMEOUT 5 |
31 | |
32 | /* |
33 | * Bump version each time a user API change is made, whether it is |
34 | * backwards compatible ot not. |
35 | */ |
36 | #define CXL_API_VERSION 3 |
37 | #define CXL_API_VERSION_COMPATIBLE 1 |
38 | |
39 | /* |
40 | * Opaque types to avoid accidentally passing registers for the wrong MMIO |
41 | * |
42 | * At the end of the day, I'm not married to using typedef here, but it might |
43 | * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and |
44 | * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write. |
45 | * |
46 | * I'm quite happy if these are changed back to #defines before upstreaming, it |
47 | * should be little more than a regexp search+replace operation in this file. |
48 | */ |
49 | typedef struct { |
50 | const int x; |
51 | } cxl_p1_reg_t; |
52 | typedef struct { |
53 | const int x; |
54 | } cxl_p1n_reg_t; |
55 | typedef struct { |
56 | const int x; |
57 | } cxl_p2n_reg_t; |
58 | #define cxl_reg_off(reg) \ |
59 | (reg.x) |
60 | |
61 | /* Memory maps. Ref CXL Appendix A */ |
62 | |
63 | /* PSL Privilege 1 Memory Map */ |
64 | /* Configuration and Control area - CAIA 1&2 */ |
65 | static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000}; |
66 | static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008}; |
67 | static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010}; |
68 | static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018}; |
69 | static const cxl_p1_reg_t CXL_PSL_Control = {0x0020}; |
70 | /* Downloading */ |
71 | static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060}; |
72 | static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068}; |
73 | |
74 | /* PSL Lookaside Buffer Management Area - CAIA 1 */ |
75 | static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080}; |
76 | static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088}; |
77 | static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090}; |
78 | static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0}; |
79 | static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8}; |
80 | static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0}; |
81 | |
82 | /* 0x00C0:7EFF Implementation dependent area */ |
83 | /* PSL registers - CAIA 1 */ |
84 | static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100}; |
85 | static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108}; |
86 | static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110}; |
87 | static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118}; |
88 | static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128}; |
89 | static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140}; |
90 | static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148}; |
91 | static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150}; |
92 | static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158}; |
93 | static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170}; |
94 | /* PSL registers - CAIA 2 */ |
95 | static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020}; |
96 | static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110}; |
97 | static const cxl_p1_reg_t CXL_XSL9_DBG = {0x0130}; |
98 | static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140}; |
99 | static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168}; |
100 | static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300}; |
101 | static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308}; |
102 | static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310}; |
103 | static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320}; |
104 | static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348}; |
105 | static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350}; |
106 | static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340}; |
107 | static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368}; |
108 | static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378}; |
109 | static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380}; |
110 | static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388}; |
111 | static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390}; |
112 | static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398}; |
113 | static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588}; |
114 | static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590}; |
115 | |
116 | /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */ |
117 | /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */ |
118 | |
119 | /* PSL Slice Privilege 1 Memory Map */ |
120 | /* Configuration Area - CAIA 1&2 */ |
121 | static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00}; |
122 | static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08}; |
123 | static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10}; |
124 | static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18}; |
125 | static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20}; |
126 | static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28}; |
127 | /* Memory Management and Lookaside Buffer Management - CAIA 1*/ |
128 | static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30}; |
129 | /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */ |
130 | static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38}; |
131 | /* Pointer Area - CAIA 1&2 */ |
132 | static const cxl_p1n_reg_t CXL_HAURP_An = {0x80}; |
133 | static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88}; |
134 | static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90}; |
135 | /* Control Area - CAIA 1&2 */ |
136 | static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0}; |
137 | static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8}; |
138 | static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0}; |
139 | static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8}; |
140 | /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */ |
141 | static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0}; |
142 | static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8}; |
143 | /* 0xC0:FF Implementation Dependent Area - CAIA 1 */ |
144 | static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0}; |
145 | static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8}; |
146 | static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0}; |
147 | static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8}; |
148 | |
149 | /* PSL Slice Privilege 2 Memory Map */ |
150 | /* Configuration and Control Area - CAIA 1&2 */ |
151 | static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000}; |
152 | static const cxl_p2n_reg_t CXL_CSRP_An = {0x008}; |
153 | /* Configuration and Control Area - CAIA 1 */ |
154 | static const cxl_p2n_reg_t CXL_AURP0_An = {0x010}; |
155 | static const cxl_p2n_reg_t CXL_AURP1_An = {0x018}; |
156 | static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020}; |
157 | static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028}; |
158 | /* Configuration and Control Area - CAIA 1 */ |
159 | static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030}; |
160 | /* Segment Lookaside Buffer Management - CAIA 1 */ |
161 | static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040}; |
162 | static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048}; |
163 | static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050}; |
164 | /* Interrupt Registers - CAIA 1&2 */ |
165 | static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060}; |
166 | static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068}; |
167 | static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070}; |
168 | static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078}; |
169 | static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080}; |
170 | static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088}; |
171 | /* AFU Registers - CAIA 1&2 */ |
172 | static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090}; |
173 | static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098}; |
174 | /* Work Element Descriptor - CAIA 1&2 */ |
175 | static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0}; |
176 | /* 0x0C0:FFF Implementation Dependent Area */ |
177 | |
178 | #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL |
179 | #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL |
180 | #define CXL_PSL_SPAP_Size_Shift 4 |
181 | #define CXL_PSL_SPAP_V 0x0000000000000001ULL |
182 | |
183 | /****** CXL_PSL_Control ****************************************************/ |
184 | #define CXL_PSL_Control_tb (0x1ull << (63-63)) |
185 | #define CXL_PSL_Control_Fr (0x1ull << (63-31)) |
186 | #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29)) |
187 | #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29)) |
188 | |
189 | /****** CXL_PSL_DLCNTL *****************************************************/ |
190 | #define CXL_PSL_DLCNTL_D (0x1ull << (63-28)) |
191 | #define CXL_PSL_DLCNTL_C (0x1ull << (63-29)) |
192 | #define CXL_PSL_DLCNTL_E (0x1ull << (63-30)) |
193 | #define CXL_PSL_DLCNTL_S (0x1ull << (63-31)) |
194 | #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E) |
195 | #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S) |
196 | |
197 | /****** CXL_PSL_SR_An ******************************************************/ |
198 | #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */ |
199 | #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */ |
200 | #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */ |
201 | #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */ |
202 | #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */ |
203 | #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */ |
204 | #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */ |
205 | #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */ |
206 | #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */ |
207 | #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */ |
208 | #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */ |
209 | #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */ |
210 | #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */ |
211 | #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */ |
212 | #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */ |
213 | |
214 | /****** CXL_PSL_ID_An ****************************************************/ |
215 | #define CXL_PSL_ID_An_F (1ull << (63-31)) |
216 | #define CXL_PSL_ID_An_L (1ull << (63-30)) |
217 | |
218 | /****** CXL_PSL_SERR_An ****************************************************/ |
219 | #define CXL_PSL_SERR_An_afuto (1ull << (63-0)) |
220 | #define CXL_PSL_SERR_An_afudis (1ull << (63-1)) |
221 | #define CXL_PSL_SERR_An_afuov (1ull << (63-2)) |
222 | #define CXL_PSL_SERR_An_badsrc (1ull << (63-3)) |
223 | #define CXL_PSL_SERR_An_badctx (1ull << (63-4)) |
224 | #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5)) |
225 | #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6)) |
226 | #define CXL_PSL_SERR_An_afupar (1ull << (63-7)) |
227 | #define CXL_PSL_SERR_An_afudup (1ull << (63-8)) |
228 | #define CXL_PSL_SERR_An_IRQS ( \ |
229 | CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \ |
230 | CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \ |
231 | CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup) |
232 | #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32)) |
233 | #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33)) |
234 | #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34)) |
235 | #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35)) |
236 | #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36)) |
237 | #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37)) |
238 | #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38)) |
239 | #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39)) |
240 | #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40)) |
241 | #define CXL_PSL_SERR_An_IRQ_MASKS ( \ |
242 | CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \ |
243 | CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \ |
244 | CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask) |
245 | |
246 | #define CXL_PSL_SERR_An_AE (1ull << (63-30)) |
247 | |
248 | /****** CXL_PSL_SCNTL_An ****************************************************/ |
249 | #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15)) |
250 | /* Programming Modes: */ |
251 | #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31)) |
252 | #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31)) |
253 | #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31)) |
254 | #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31)) |
255 | #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31)) |
256 | #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31)) |
257 | /* Purge Status (ro) */ |
258 | #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39)) |
259 | #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39)) |
260 | #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39)) |
261 | /* Purge */ |
262 | #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48)) |
263 | /* Suspend Status (ro) */ |
264 | #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55)) |
265 | #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55)) |
266 | #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55)) |
267 | /* Suspend Control */ |
268 | #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63)) |
269 | |
270 | /* AFU Slice Enable Status (ro) */ |
271 | #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2)) |
272 | #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2)) |
273 | #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2)) |
274 | /* AFU Slice Enable */ |
275 | #define CXL_AFU_Cntl_An_E (0x1ull << (63-3)) |
276 | /* AFU Slice Reset status (ro) */ |
277 | #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5)) |
278 | #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5)) |
279 | #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5)) |
280 | /* AFU Slice Reset */ |
281 | #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7)) |
282 | |
283 | /****** CXL_SSTP0/1_An ******************************************************/ |
284 | /* These top bits are for the segment that CONTAINS the segment table */ |
285 | #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT |
286 | #define CXL_SSTP0_An_KS (1ull << (63-2)) |
287 | #define CXL_SSTP0_An_KP (1ull << (63-3)) |
288 | #define CXL_SSTP0_An_N (1ull << (63-4)) |
289 | #define CXL_SSTP0_An_L (1ull << (63-5)) |
290 | #define CXL_SSTP0_An_C (1ull << (63-6)) |
291 | #define CXL_SSTP0_An_TA (1ull << (63-7)) |
292 | #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */ |
293 | /* And finally, the virtual address & size of the segment table: */ |
294 | #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */ |
295 | #define CXL_SSTP0_An_SegTableSize_MASK \ |
296 | (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT) |
297 | #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1) |
298 | #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1)) |
299 | #define CXL_SSTP1_An_V (1ull << (63-63)) |
300 | |
301 | /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/ |
302 | /* write: */ |
303 | #define CXL_SLBIE_C PPC_BIT(36) /* Class */ |
304 | #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */ |
305 | #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38) |
306 | #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */ |
307 | /* read: */ |
308 | #define CXL_SLBIE_MAX PPC_BITMASK(24, 31) |
309 | #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63) |
310 | |
311 | /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/ |
312 | #define CXL_TLB_SLB_P (1ull) /* Pending (read) */ |
313 | |
314 | /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/ |
315 | #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */ |
316 | #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */ |
317 | #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */ |
318 | |
319 | /****** CXL_PSL_AFUSEL ******************************************************/ |
320 | #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */ |
321 | |
322 | /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/ |
323 | #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */ |
324 | #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */ |
325 | #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */ |
326 | #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */ |
327 | #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR) |
328 | #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ |
329 | #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ |
330 | #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ |
331 | #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC) |
332 | /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */ |
333 | #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */ |
334 | #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */ |
335 | #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */ |
336 | #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */ |
337 | #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */ |
338 | |
339 | /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/ |
340 | #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */ |
341 | #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */ |
342 | #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */ |
343 | #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */ |
344 | #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */ |
345 | #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC) |
346 | /* |
347 | * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1 |
348 | * Status (0:7) Encoding |
349 | */ |
350 | #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL |
351 | #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */ |
352 | #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */ |
353 | #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */ |
354 | #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */ |
355 | #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */ |
356 | #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */ |
357 | #define CXL_PSL9_DSISR_An_URTCH 0x00000000000000B4ULL /* Unsupported Radix Tree Configuration 0b10110100 */ |
358 | |
359 | /****** CXL_PSL_TFC_An ******************************************************/ |
360 | #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */ |
361 | #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */ |
362 | #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */ |
363 | #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */ |
364 | |
365 | /****** CXL_PSL_DEBUG *****************************************************/ |
366 | #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */ |
367 | |
368 | /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/ |
369 | #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */ |
370 | #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */ |
371 | #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */ |
372 | #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */ |
373 | #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */ |
374 | #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */ |
375 | |
376 | /* cxl_process_element->software_status */ |
377 | #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */ |
378 | #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */ |
379 | #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */ |
380 | #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */ |
381 | |
382 | /****** CXL_PSL_RXCTL_An (Implementation Specific) ************************** |
383 | * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to |
384 | * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x |
385 | * of the hang pulse frequency. |
386 | */ |
387 | #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL |
388 | |
389 | /* SPA->sw_command_status */ |
390 | #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL |
391 | #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL |
392 | #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL |
393 | #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL |
394 | #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL |
395 | #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL |
396 | #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL |
397 | #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL |
398 | #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL |
399 | #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL |
400 | #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL |
401 | #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL |
402 | #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL |
403 | #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL |
404 | #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL |
405 | #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL |
406 | |
407 | #define CXL_MAX_SLICES 4 |
408 | #define MAX_AFU_MMIO_REGS 3 |
409 | |
410 | #define CXL_MODE_TIME_SLICED 0x4 |
411 | #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED) |
412 | |
413 | #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */ |
414 | #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS) |
415 | #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS) |
416 | |
417 | #define CXL_PSL9_TRACEID_MAX 0xAU |
418 | #define CXL_PSL9_TRACESTATE_FIN 0x3U |
419 | |
420 | enum cxl_context_status { |
421 | CLOSED, |
422 | OPENED, |
423 | STARTED |
424 | }; |
425 | |
426 | enum prefault_modes { |
427 | CXL_PREFAULT_NONE, |
428 | CXL_PREFAULT_WED, |
429 | CXL_PREFAULT_ALL, |
430 | }; |
431 | |
432 | enum cxl_attrs { |
433 | CXL_ADAPTER_ATTRS, |
434 | CXL_AFU_MASTER_ATTRS, |
435 | CXL_AFU_ATTRS, |
436 | }; |
437 | |
438 | struct cxl_sste { |
439 | __be64 esid_data; |
440 | __be64 vsid_data; |
441 | }; |
442 | |
443 | #define to_cxl_adapter(d) container_of(d, struct cxl, dev) |
444 | #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev) |
445 | |
446 | struct cxl_afu_native { |
447 | void __iomem *p1n_mmio; |
448 | void __iomem *afu_desc_mmio; |
449 | irq_hw_number_t psl_hwirq; |
450 | unsigned int psl_virq; |
451 | struct mutex spa_mutex; |
452 | /* |
453 | * Only the first part of the SPA is used for the process element |
454 | * linked list. The only other part that software needs to worry about |
455 | * is sw_command_status, which we store a separate pointer to. |
456 | * Everything else in the SPA is only used by hardware |
457 | */ |
458 | struct cxl_process_element *spa; |
459 | __be64 *sw_command_status; |
460 | unsigned int spa_size; |
461 | int spa_order; |
462 | int spa_max_procs; |
463 | u64 pp_offset; |
464 | }; |
465 | |
466 | struct cxl_afu_guest { |
467 | struct cxl_afu *parent; |
468 | u64 handle; |
469 | phys_addr_t p2n_phys; |
470 | u64 p2n_size; |
471 | int max_ints; |
472 | bool handle_err; |
473 | struct delayed_work work_err; |
474 | int previous_state; |
475 | }; |
476 | |
477 | struct cxl_afu { |
478 | struct cxl_afu_native *native; |
479 | struct cxl_afu_guest *guest; |
480 | irq_hw_number_t serr_hwirq; |
481 | unsigned int serr_virq; |
482 | char *psl_irq_name; |
483 | char *err_irq_name; |
484 | void __iomem *p2n_mmio; |
485 | phys_addr_t psn_phys; |
486 | u64 pp_size; |
487 | |
488 | struct cxl *adapter; |
489 | struct device dev; |
490 | struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d; |
491 | struct device *chardev_s, *chardev_m, *chardev_d; |
492 | struct idr contexts_idr; |
493 | struct dentry *debugfs; |
494 | struct mutex contexts_lock; |
495 | spinlock_t afu_cntl_lock; |
496 | |
497 | /* -1: AFU deconfigured/locked, >= 0: number of readers */ |
498 | atomic_t configured_state; |
499 | |
500 | /* AFU error buffer fields and bin attribute for sysfs */ |
501 | u64 eb_len, eb_offset; |
502 | struct bin_attribute attr_eb; |
503 | |
504 | /* pointer to the vphb */ |
505 | struct pci_controller *phb; |
506 | |
507 | int pp_irqs; |
508 | int irqs_max; |
509 | int num_procs; |
510 | int max_procs_virtualised; |
511 | int slice; |
512 | int modes_supported; |
513 | int current_mode; |
514 | int crs_num; |
515 | u64 crs_len; |
516 | u64 crs_offset; |
517 | struct list_head crs; |
518 | enum prefault_modes prefault_mode; |
519 | bool psa; |
520 | bool pp_psa; |
521 | bool enabled; |
522 | }; |
523 | |
524 | |
525 | struct cxl_irq_name { |
526 | struct list_head list; |
527 | char *name; |
528 | }; |
529 | |
530 | struct irq_avail { |
531 | irq_hw_number_t offset; |
532 | irq_hw_number_t range; |
533 | unsigned long *bitmap; |
534 | }; |
535 | |
536 | /* |
537 | * This is a cxl context. If the PSL is in dedicated mode, there will be one |
538 | * of these per AFU. If in AFU directed there can be lots of these. |
539 | */ |
540 | struct cxl_context { |
541 | struct cxl_afu *afu; |
542 | |
543 | /* Problem state MMIO */ |
544 | phys_addr_t psn_phys; |
545 | u64 psn_size; |
546 | |
547 | /* Used to unmap any mmaps when force detaching */ |
548 | struct address_space *mapping; |
549 | struct mutex mapping_lock; |
550 | struct page *ff_page; |
551 | bool mmio_err_ff; |
552 | bool kernelapi; |
553 | |
554 | spinlock_t sste_lock; /* Protects segment table entries */ |
555 | struct cxl_sste *sstp; |
556 | u64 sstp0, sstp1; |
557 | unsigned int sst_size, sst_lru; |
558 | |
559 | wait_queue_head_t wq; |
560 | /* use mm context associated with this pid for ds faults */ |
561 | struct pid *pid; |
562 | spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */ |
563 | /* Only used in PR mode */ |
564 | u64 process_token; |
565 | |
566 | /* driver private data */ |
567 | void *priv; |
568 | |
569 | unsigned long *irq_bitmap; /* Accessed from IRQ context */ |
570 | struct cxl_irq_ranges irqs; |
571 | struct list_head irq_names; |
572 | u64 fault_addr; |
573 | u64 fault_dsisr; |
574 | u64 afu_err; |
575 | |
576 | /* |
577 | * This status and it's lock pretects start and detach context |
578 | * from racing. It also prevents detach from racing with |
579 | * itself |
580 | */ |
581 | enum cxl_context_status status; |
582 | struct mutex status_mutex; |
583 | |
584 | |
585 | /* XXX: Is it possible to need multiple work items at once? */ |
586 | struct work_struct fault_work; |
587 | u64 dsisr; |
588 | u64 dar; |
589 | |
590 | struct cxl_process_element *elem; |
591 | |
592 | /* |
593 | * pe is the process element handle, assigned by this driver when the |
594 | * context is initialized. |
595 | * |
596 | * external_pe is the PE shown outside of cxl. |
597 | * On bare-metal, pe=external_pe, because we decide what the handle is. |
598 | * In a guest, we only find out about the pe used by pHyp when the |
599 | * context is attached, and that's the value we want to report outside |
600 | * of cxl. |
601 | */ |
602 | int pe; |
603 | int external_pe; |
604 | |
605 | u32 irq_count; |
606 | bool pe_inserted; |
607 | bool master; |
608 | bool kernel; |
609 | bool pending_irq; |
610 | bool pending_fault; |
611 | bool pending_afu_err; |
612 | |
613 | /* Used by AFU drivers for driver specific event delivery */ |
614 | struct cxl_afu_driver_ops *afu_driver_ops; |
615 | atomic_t afu_driver_events; |
616 | |
617 | struct rcu_head rcu; |
618 | |
619 | struct mm_struct *mm; |
620 | |
621 | u16 tidr; |
622 | bool assign_tidr; |
623 | }; |
624 | |
625 | struct cxl_irq_info; |
626 | |
627 | struct cxl_service_layer_ops { |
628 | int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev); |
629 | int (*invalidate_all)(struct cxl *adapter); |
630 | int (*afu_regs_init)(struct cxl_afu *afu); |
631 | int (*sanitise_afu_regs)(struct cxl_afu *afu); |
632 | int (*register_serr_irq)(struct cxl_afu *afu); |
633 | void (*release_serr_irq)(struct cxl_afu *afu); |
634 | irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info); |
635 | irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info); |
636 | int (*activate_dedicated_process)(struct cxl_afu *afu); |
637 | int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr); |
638 | int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr); |
639 | void (*update_dedicated_ivtes)(struct cxl_context *ctx); |
640 | void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir); |
641 | void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir); |
642 | void (*psl_irq_dump_registers)(struct cxl_context *ctx); |
643 | void (*err_irq_dump_registers)(struct cxl *adapter); |
644 | void (*debugfs_stop_trace)(struct cxl *adapter); |
645 | void (*write_timebase_ctrl)(struct cxl *adapter); |
646 | u64 (*timebase_read)(struct cxl *adapter); |
647 | int capi_mode; |
648 | bool needs_reset_before_disable; |
649 | }; |
650 | |
651 | struct cxl_native { |
652 | u64 afu_desc_off; |
653 | u64 afu_desc_size; |
654 | void __iomem *p1_mmio; |
655 | void __iomem *p2_mmio; |
656 | irq_hw_number_t err_hwirq; |
657 | unsigned int err_virq; |
658 | u64 ps_off; |
659 | bool no_data_cache; /* set if no data cache on the card */ |
660 | const struct cxl_service_layer_ops *sl_ops; |
661 | }; |
662 | |
663 | struct cxl_guest { |
664 | struct platform_device *pdev; |
665 | int irq_nranges; |
666 | struct cdev cdev; |
667 | irq_hw_number_t irq_base_offset; |
668 | struct irq_avail *irq_avail; |
669 | spinlock_t irq_alloc_lock; |
670 | u64 handle; |
671 | char *status; |
672 | u16 vendor; |
673 | u16 device; |
674 | u16 subsystem_vendor; |
675 | u16 subsystem; |
676 | }; |
677 | |
678 | struct cxl { |
679 | struct cxl_native *native; |
680 | struct cxl_guest *guest; |
681 | spinlock_t afu_list_lock; |
682 | struct cxl_afu *afu[CXL_MAX_SLICES]; |
683 | struct device dev; |
684 | struct dentry *trace; |
685 | struct dentry *psl_err_chk; |
686 | struct dentry *debugfs; |
687 | char *irq_name; |
688 | struct bin_attribute cxl_attr; |
689 | int adapter_num; |
690 | int user_irqs; |
691 | u64 ps_size; |
692 | u16 psl_rev; |
693 | u16 base_image; |
694 | u8 vsec_status; |
695 | u8 caia_major; |
696 | u8 caia_minor; |
697 | u8 slices; |
698 | bool user_image_loaded; |
699 | bool perst_loads_image; |
700 | bool perst_select_user; |
701 | bool perst_same_image; |
702 | bool psl_timebase_synced; |
703 | bool tunneled_ops_supported; |
704 | |
705 | /* |
706 | * number of contexts mapped on to this card. Possible values are: |
707 | * >0: Number of contexts mapped and new one can be mapped. |
708 | * 0: No active contexts and new ones can be mapped. |
709 | * -1: No contexts mapped and new ones cannot be mapped. |
710 | */ |
711 | atomic_t contexts_num; |
712 | }; |
713 | |
714 | int cxl_pci_alloc_one_irq(struct cxl *adapter); |
715 | void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq); |
716 | int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num); |
717 | void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter); |
718 | int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq); |
719 | int cxl_update_image_control(struct cxl *adapter); |
720 | int cxl_pci_reset(struct cxl *adapter); |
721 | void cxl_pci_release_afu(struct device *dev); |
722 | ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); |
723 | |
724 | /* common == phyp + powernv - CAIA 1&2 */ |
725 | struct cxl_process_element_common { |
726 | __be32 tid; |
727 | __be32 pid; |
728 | __be64 csrp; |
729 | union { |
730 | struct { |
731 | __be64 aurp0; |
732 | __be64 aurp1; |
733 | __be64 sstp0; |
734 | __be64 sstp1; |
735 | } psl8; /* CAIA 1 */ |
736 | struct { |
737 | u8 reserved2[8]; |
738 | u8 reserved3[8]; |
739 | u8 reserved4[8]; |
740 | u8 reserved5[8]; |
741 | } psl9; /* CAIA 2 */ |
742 | } u; |
743 | __be64 amr; |
744 | u8 reserved6[4]; |
745 | __be64 wed; |
746 | } __packed; |
747 | |
748 | /* just powernv - CAIA 1&2 */ |
749 | struct cxl_process_element { |
750 | __be64 sr; |
751 | __be64 SPOffset; |
752 | union { |
753 | __be64 sdr; /* CAIA 1 */ |
754 | u8 reserved1[8]; /* CAIA 2 */ |
755 | } u; |
756 | __be64 haurp; |
757 | __be32 ctxtime; |
758 | __be16 ivte_offsets[4]; |
759 | __be16 ivte_ranges[4]; |
760 | __be32 lpid; |
761 | struct cxl_process_element_common common; |
762 | __be32 software_state; |
763 | } __packed; |
764 | |
765 | static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu) |
766 | { |
767 | struct pci_dev *pdev; |
768 | |
769 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
770 | pdev = to_pci_dev(cxl->dev.parent); |
771 | return !pci_channel_offline(pdev); |
772 | } |
773 | return true; |
774 | } |
775 | |
776 | static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) |
777 | { |
778 | WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); |
779 | return cxl->native->p1_mmio + cxl_reg_off(reg); |
780 | } |
781 | |
782 | static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val) |
783 | { |
784 | if (likely(cxl_adapter_link_ok(cxl, NULL))) |
785 | out_be64(_cxl_p1_addr(cxl, reg), val); |
786 | } |
787 | |
788 | static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg) |
789 | { |
790 | if (likely(cxl_adapter_link_ok(cxl, NULL))) |
791 | return in_be64(_cxl_p1_addr(cxl, reg)); |
792 | else |
793 | return ~0ULL; |
794 | } |
795 | |
796 | static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) |
797 | { |
798 | WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE)); |
799 | return afu->native->p1n_mmio + cxl_reg_off(reg); |
800 | } |
801 | |
802 | static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val) |
803 | { |
804 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
805 | out_be64(_cxl_p1n_addr(afu, reg), val); |
806 | } |
807 | |
808 | static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg) |
809 | { |
810 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
811 | return in_be64(_cxl_p1n_addr(afu, reg)); |
812 | else |
813 | return ~0ULL; |
814 | } |
815 | |
816 | static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) |
817 | { |
818 | return afu->p2n_mmio + cxl_reg_off(reg); |
819 | } |
820 | |
821 | static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val) |
822 | { |
823 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
824 | out_be64(_cxl_p2n_addr(afu, reg), val); |
825 | } |
826 | |
827 | static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg) |
828 | { |
829 | if (likely(cxl_adapter_link_ok(afu->adapter, afu))) |
830 | return in_be64(_cxl_p2n_addr(afu, reg)); |
831 | else |
832 | return ~0ULL; |
833 | } |
834 | |
835 | static inline bool cxl_is_power8(void) |
836 | { |
837 | if ((pvr_version_is(PVR_POWER8E)) || |
838 | (pvr_version_is(PVR_POWER8NVL)) || |
839 | (pvr_version_is(PVR_POWER8)) || |
840 | (pvr_version_is(PVR_HX_C2000))) |
841 | return true; |
842 | return false; |
843 | } |
844 | |
845 | static inline bool cxl_is_power9(void) |
846 | { |
847 | if (pvr_version_is(PVR_POWER9)) |
848 | return true; |
849 | return false; |
850 | } |
851 | |
852 | ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, |
853 | loff_t off, size_t count); |
854 | |
855 | |
856 | struct cxl_calls { |
857 | void (*cxl_slbia)(struct mm_struct *mm); |
858 | struct module *owner; |
859 | }; |
860 | int register_cxl_calls(struct cxl_calls *calls); |
861 | void unregister_cxl_calls(struct cxl_calls *calls); |
862 | int cxl_update_properties(struct device_node *dn, struct property *new_prop); |
863 | |
864 | void cxl_remove_adapter_nr(struct cxl *adapter); |
865 | |
866 | void cxl_release_spa(struct cxl_afu *afu); |
867 | |
868 | dev_t cxl_get_dev(void); |
869 | int cxl_file_init(void); |
870 | void cxl_file_exit(void); |
871 | int cxl_register_adapter(struct cxl *adapter); |
872 | int cxl_register_afu(struct cxl_afu *afu); |
873 | int cxl_chardev_d_afu_add(struct cxl_afu *afu); |
874 | int cxl_chardev_m_afu_add(struct cxl_afu *afu); |
875 | int cxl_chardev_s_afu_add(struct cxl_afu *afu); |
876 | void cxl_chardev_afu_remove(struct cxl_afu *afu); |
877 | |
878 | void cxl_context_detach_all(struct cxl_afu *afu); |
879 | void cxl_context_free(struct cxl_context *ctx); |
880 | void cxl_context_detach(struct cxl_context *ctx); |
881 | |
882 | int cxl_sysfs_adapter_add(struct cxl *adapter); |
883 | void cxl_sysfs_adapter_remove(struct cxl *adapter); |
884 | int cxl_sysfs_afu_add(struct cxl_afu *afu); |
885 | void cxl_sysfs_afu_remove(struct cxl_afu *afu); |
886 | int cxl_sysfs_afu_m_add(struct cxl_afu *afu); |
887 | void cxl_sysfs_afu_m_remove(struct cxl_afu *afu); |
888 | |
889 | struct cxl *cxl_alloc_adapter(void); |
890 | struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice); |
891 | int cxl_afu_select_best_mode(struct cxl_afu *afu); |
892 | |
893 | int cxl_native_register_psl_irq(struct cxl_afu *afu); |
894 | void cxl_native_release_psl_irq(struct cxl_afu *afu); |
895 | int cxl_native_register_psl_err_irq(struct cxl *adapter); |
896 | void cxl_native_release_psl_err_irq(struct cxl *adapter); |
897 | int cxl_native_register_serr_irq(struct cxl_afu *afu); |
898 | void cxl_native_release_serr_irq(struct cxl_afu *afu); |
899 | int afu_register_irqs(struct cxl_context *ctx, u32 count); |
900 | void afu_release_irqs(struct cxl_context *ctx, void *cookie); |
901 | void afu_irq_name_free(struct cxl_context *ctx); |
902 | |
903 | int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr); |
904 | int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr); |
905 | int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu); |
906 | int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu); |
907 | int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr); |
908 | int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr); |
909 | void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx); |
910 | void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx); |
911 | |
912 | #ifdef CONFIG_DEBUG_FS |
913 | |
914 | void cxl_debugfs_init(void); |
915 | void cxl_debugfs_exit(void); |
916 | void cxl_debugfs_adapter_add(struct cxl *adapter); |
917 | void cxl_debugfs_adapter_remove(struct cxl *adapter); |
918 | void cxl_debugfs_afu_add(struct cxl_afu *afu); |
919 | void cxl_debugfs_afu_remove(struct cxl_afu *afu); |
920 | void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir); |
921 | void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir); |
922 | void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir); |
923 | void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir); |
924 | |
925 | #else /* CONFIG_DEBUG_FS */ |
926 | |
927 | static inline void __init cxl_debugfs_init(void) |
928 | { |
929 | } |
930 | |
931 | static inline void cxl_debugfs_exit(void) |
932 | { |
933 | } |
934 | |
935 | static inline void cxl_debugfs_adapter_add(struct cxl *adapter) |
936 | { |
937 | } |
938 | |
939 | static inline void cxl_debugfs_adapter_remove(struct cxl *adapter) |
940 | { |
941 | } |
942 | |
943 | static inline void cxl_debugfs_afu_add(struct cxl_afu *afu) |
944 | { |
945 | } |
946 | |
947 | static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu) |
948 | { |
949 | } |
950 | |
951 | static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, |
952 | struct dentry *dir) |
953 | { |
954 | } |
955 | |
956 | static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, |
957 | struct dentry *dir) |
958 | { |
959 | } |
960 | |
961 | static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir) |
962 | { |
963 | } |
964 | |
965 | static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir) |
966 | { |
967 | } |
968 | |
969 | #endif /* CONFIG_DEBUG_FS */ |
970 | |
971 | void cxl_handle_fault(struct work_struct *work); |
972 | void cxl_prefault(struct cxl_context *ctx, u64 wed); |
973 | int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar); |
974 | |
975 | struct cxl *get_cxl_adapter(int num); |
976 | int cxl_alloc_sst(struct cxl_context *ctx); |
977 | void cxl_dump_debug_buffer(void *addr, size_t size); |
978 | |
979 | void init_cxl_native(void); |
980 | |
981 | struct cxl_context *cxl_context_alloc(void); |
982 | int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master); |
983 | void cxl_context_set_mapping(struct cxl_context *ctx, |
984 | struct address_space *mapping); |
985 | void cxl_context_free(struct cxl_context *ctx); |
986 | int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); |
987 | unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, |
988 | irq_handler_t handler, void *cookie, const char *name); |
989 | void cxl_unmap_irq(unsigned int virq, void *cookie); |
990 | int __detach_context(struct cxl_context *ctx); |
991 | |
992 | /* |
993 | * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined |
994 | * in PAPR. |
995 | * Field pid_tid is now 'reserved' because it's no more used on bare-metal. |
996 | * On a guest environment, PSL_PID_An is located on the upper 32 bits and |
997 | * PSL_TID_An register in the lower 32 bits. |
998 | */ |
999 | struct cxl_irq_info { |
1000 | u64 dsisr; |
1001 | u64 dar; |
1002 | u64 dsr; |
1003 | u64 reserved; |
1004 | u64 afu_err; |
1005 | u64 errstat; |
1006 | u64 proc_handle; |
1007 | u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */ |
1008 | }; |
1009 | |
1010 | void cxl_assign_psn_space(struct cxl_context *ctx); |
1011 | int cxl_invalidate_all_psl9(struct cxl *adapter); |
1012 | int cxl_invalidate_all_psl8(struct cxl *adapter); |
1013 | irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info); |
1014 | irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info); |
1015 | irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info); |
1016 | int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler, |
1017 | void *cookie, irq_hw_number_t *dest_hwirq, |
1018 | unsigned int *dest_virq, const char *name); |
1019 | |
1020 | int cxl_check_error(struct cxl_afu *afu); |
1021 | int cxl_afu_slbia(struct cxl_afu *afu); |
1022 | int cxl_data_cache_flush(struct cxl *adapter); |
1023 | int cxl_afu_disable(struct cxl_afu *afu); |
1024 | int cxl_psl_purge(struct cxl_afu *afu); |
1025 | int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, |
1026 | u32 *phb_index, u64 *capp_unit_id); |
1027 | int cxl_slot_is_switched(struct pci_dev *dev); |
1028 | int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg); |
1029 | u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9); |
1030 | |
1031 | void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx); |
1032 | void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx); |
1033 | void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter); |
1034 | void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter); |
1035 | int cxl_pci_vphb_add(struct cxl_afu *afu); |
1036 | void cxl_pci_vphb_remove(struct cxl_afu *afu); |
1037 | void cxl_release_mapping(struct cxl_context *ctx); |
1038 | |
1039 | extern struct pci_driver cxl_pci_driver; |
1040 | extern struct platform_driver cxl_of_driver; |
1041 | int afu_allocate_irqs(struct cxl_context *ctx, u32 count); |
1042 | |
1043 | int afu_open(struct inode *inode, struct file *file); |
1044 | int afu_release(struct inode *inode, struct file *file); |
1045 | long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
1046 | int afu_mmap(struct file *file, struct vm_area_struct *vm); |
1047 | __poll_t afu_poll(struct file *file, struct poll_table_struct *poll); |
1048 | ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off); |
1049 | extern const struct file_operations afu_fops; |
1050 | |
1051 | struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev); |
1052 | void cxl_guest_remove_adapter(struct cxl *adapter); |
1053 | int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np); |
1054 | int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np); |
1055 | ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len); |
1056 | ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len); |
1057 | int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np); |
1058 | void cxl_guest_remove_afu(struct cxl_afu *afu); |
1059 | int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np); |
1060 | int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np); |
1061 | int cxl_guest_add_chardev(struct cxl *adapter); |
1062 | void cxl_guest_remove_chardev(struct cxl *adapter); |
1063 | void cxl_guest_reload_module(struct cxl *adapter); |
1064 | int cxl_of_probe(struct platform_device *pdev); |
1065 | |
1066 | struct cxl_backend_ops { |
1067 | struct module *module; |
1068 | int (*adapter_reset)(struct cxl *adapter); |
1069 | int (*alloc_one_irq)(struct cxl *adapter); |
1070 | void (*release_one_irq)(struct cxl *adapter, int hwirq); |
1071 | int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs, |
1072 | struct cxl *adapter, unsigned int num); |
1073 | void (*release_irq_ranges)(struct cxl_irq_ranges *irqs, |
1074 | struct cxl *adapter); |
1075 | int (*setup_irq)(struct cxl *adapter, unsigned int hwirq, |
1076 | unsigned int virq); |
1077 | irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx, |
1078 | u64 dsisr, u64 errstat); |
1079 | irqreturn_t (*psl_interrupt)(int irq, void *data); |
1080 | int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); |
1081 | void (*irq_wait)(struct cxl_context *ctx); |
1082 | int (*attach_process)(struct cxl_context *ctx, bool kernel, |
1083 | u64 wed, u64 amr); |
1084 | int (*detach_process)(struct cxl_context *ctx); |
1085 | void (*update_ivtes)(struct cxl_context *ctx); |
1086 | bool (*support_attributes)(const char *attr_name, enum cxl_attrs type); |
1087 | bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu); |
1088 | void (*release_afu)(struct device *dev); |
1089 | ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf, |
1090 | loff_t off, size_t count); |
1091 | int (*afu_check_and_enable)(struct cxl_afu *afu); |
1092 | int (*afu_activate_mode)(struct cxl_afu *afu, int mode); |
1093 | int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode); |
1094 | int (*afu_reset)(struct cxl_afu *afu); |
1095 | int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val); |
1096 | int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val); |
1097 | int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val); |
1098 | int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val); |
1099 | int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val); |
1100 | int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val); |
1101 | int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val); |
1102 | ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count); |
1103 | }; |
1104 | extern const struct cxl_backend_ops cxl_native_ops; |
1105 | extern const struct cxl_backend_ops cxl_guest_ops; |
1106 | extern const struct cxl_backend_ops *cxl_ops; |
1107 | |
1108 | /* check if the given pci_dev is on the cxl vphb bus */ |
1109 | bool cxl_pci_is_vphb_device(struct pci_dev *dev); |
1110 | |
1111 | /* decode AFU error bits in the PSL register PSL_SERR_An */ |
1112 | void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr); |
1113 | |
1114 | /* |
1115 | * Increments the number of attached contexts on an adapter. |
1116 | * In case an adapter_context_lock is taken the return -EBUSY. |
1117 | */ |
1118 | int cxl_adapter_context_get(struct cxl *adapter); |
1119 | |
1120 | /* Decrements the number of attached contexts on an adapter */ |
1121 | void cxl_adapter_context_put(struct cxl *adapter); |
1122 | |
1123 | /* If no active contexts then prevents contexts from being attached */ |
1124 | int cxl_adapter_context_lock(struct cxl *adapter); |
1125 | |
1126 | /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */ |
1127 | void cxl_adapter_context_unlock(struct cxl *adapter); |
1128 | |
1129 | /* Increases the reference count to "struct mm_struct" */ |
1130 | void cxl_context_mm_count_get(struct cxl_context *ctx); |
1131 | |
1132 | /* Decrements the reference count to "struct mm_struct" */ |
1133 | void cxl_context_mm_count_put(struct cxl_context *ctx); |
1134 | |
1135 | #endif |
1136 | |