1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2004 Embedded Edge, LLC
4 */
5
6#include <linux/delay.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <linux/interrupt.h>
10#include <linux/mtd/mtd.h>
11#include <linux/mtd/rawnand.h>
12#include <linux/mtd/partitions.h>
13#include <linux/platform_device.h>
14#include <asm/io.h>
15#include <asm/mach-au1x00/au1000.h>
16#include <asm/mach-au1x00/au1550nd.h>
17
18
19struct au1550nd_ctx {
20 struct nand_controller controller;
21 struct nand_chip chip;
22
23 int cs;
24 void __iomem *base;
25};
26
27static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
28{
29 return container_of(this, struct au1550nd_ctx, chip);
30}
31
32/**
33 * au_write_buf - write buffer to chip
34 * @this: NAND chip object
35 * @buf: data buffer
36 * @len: number of bytes to write
37 *
38 * write function for 8bit buswidth
39 */
40static void au_write_buf(struct nand_chip *this, const void *buf,
41 unsigned int len)
42{
43 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
44 const u8 *p = buf;
45 int i;
46
47 for (i = 0; i < len; i++) {
48 writeb(val: p[i], addr: ctx->base + MEM_STNAND_DATA);
49 wmb(); /* drain writebuffer */
50 }
51}
52
53/**
54 * au_read_buf - read chip data into buffer
55 * @this: NAND chip object
56 * @buf: buffer to store date
57 * @len: number of bytes to read
58 *
59 * read function for 8bit buswidth
60 */
61static void au_read_buf(struct nand_chip *this, void *buf,
62 unsigned int len)
63{
64 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
65 u8 *p = buf;
66 int i;
67
68 for (i = 0; i < len; i++) {
69 p[i] = readb(addr: ctx->base + MEM_STNAND_DATA);
70 wmb(); /* drain writebuffer */
71 }
72}
73
74/**
75 * au_write_buf16 - write buffer to chip
76 * @this: NAND chip object
77 * @buf: data buffer
78 * @len: number of bytes to write
79 *
80 * write function for 16bit buswidth
81 */
82static void au_write_buf16(struct nand_chip *this, const void *buf,
83 unsigned int len)
84{
85 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
86 const u16 *p = buf;
87 unsigned int i;
88
89 len >>= 1;
90 for (i = 0; i < len; i++) {
91 writew(val: p[i], addr: ctx->base + MEM_STNAND_DATA);
92 wmb(); /* drain writebuffer */
93 }
94}
95
96/**
97 * au_read_buf16 - read chip data into buffer
98 * @this: NAND chip object
99 * @buf: buffer to store date
100 * @len: number of bytes to read
101 *
102 * read function for 16bit buswidth
103 */
104static void au_read_buf16(struct nand_chip *this, void *buf, unsigned int len)
105{
106 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
107 unsigned int i;
108 u16 *p = buf;
109
110 len >>= 1;
111 for (i = 0; i < len; i++) {
112 p[i] = readw(addr: ctx->base + MEM_STNAND_DATA);
113 wmb(); /* drain writebuffer */
114 }
115}
116
117static int find_nand_cs(unsigned long nand_base)
118{
119 void __iomem *base =
120 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
121 unsigned long addr, staddr, start, mask, end;
122 int i;
123
124 for (i = 0; i < 4; i++) {
125 addr = 0x1000 + (i * 0x10); /* CSx */
126 staddr = __raw_readl(addr: base + addr + 0x08); /* STADDRx */
127 /* figure out the decoded range of this CS */
128 start = (staddr << 4) & 0xfffc0000;
129 mask = (staddr << 18) & 0xfffc0000;
130 end = (start | (start - 1)) & ~(start ^ mask);
131 if ((nand_base >= start) && (nand_base < end))
132 return i;
133 }
134
135 return -ENODEV;
136}
137
138static int au1550nd_waitrdy(struct nand_chip *this, unsigned int timeout_ms)
139{
140 unsigned long timeout_jiffies = jiffies;
141
142 timeout_jiffies += msecs_to_jiffies(m: timeout_ms) + 1;
143 do {
144 if (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1)
145 return 0;
146
147 usleep_range(min: 10, max: 100);
148 } while (time_before(jiffies, timeout_jiffies));
149
150 return -ETIMEDOUT;
151}
152
153static int au1550nd_exec_instr(struct nand_chip *this,
154 const struct nand_op_instr *instr)
155{
156 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
157 unsigned int i;
158 int ret = 0;
159
160 switch (instr->type) {
161 case NAND_OP_CMD_INSTR:
162 writeb(val: instr->ctx.cmd.opcode,
163 addr: ctx->base + MEM_STNAND_CMD);
164 /* Drain the writebuffer */
165 wmb();
166 break;
167
168 case NAND_OP_ADDR_INSTR:
169 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
170 writeb(val: instr->ctx.addr.addrs[i],
171 addr: ctx->base + MEM_STNAND_ADDR);
172 /* Drain the writebuffer */
173 wmb();
174 }
175 break;
176
177 case NAND_OP_DATA_IN_INSTR:
178 if ((this->options & NAND_BUSWIDTH_16) &&
179 !instr->ctx.data.force_8bit)
180 au_read_buf16(this, buf: instr->ctx.data.buf.in,
181 len: instr->ctx.data.len);
182 else
183 au_read_buf(this, buf: instr->ctx.data.buf.in,
184 len: instr->ctx.data.len);
185 break;
186
187 case NAND_OP_DATA_OUT_INSTR:
188 if ((this->options & NAND_BUSWIDTH_16) &&
189 !instr->ctx.data.force_8bit)
190 au_write_buf16(this, buf: instr->ctx.data.buf.out,
191 len: instr->ctx.data.len);
192 else
193 au_write_buf(this, buf: instr->ctx.data.buf.out,
194 len: instr->ctx.data.len);
195 break;
196
197 case NAND_OP_WAITRDY_INSTR:
198 ret = au1550nd_waitrdy(this, timeout_ms: instr->ctx.waitrdy.timeout_ms);
199 break;
200 default:
201 return -EINVAL;
202 }
203
204 if (instr->delay_ns)
205 ndelay(instr->delay_ns);
206
207 return ret;
208}
209
210static int au1550nd_exec_op(struct nand_chip *this,
211 const struct nand_operation *op,
212 bool check_only)
213{
214 struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
215 unsigned int i;
216 int ret;
217
218 if (check_only)
219 return 0;
220
221 /* assert (force assert) chip enable */
222 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
223 /* Drain the writebuffer */
224 wmb();
225
226 for (i = 0; i < op->ninstrs; i++) {
227 ret = au1550nd_exec_instr(this, instr: &op->instrs[i]);
228 if (ret)
229 break;
230 }
231
232 /* deassert chip enable */
233 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
234 /* Drain the writebuffer */
235 wmb();
236
237 return ret;
238}
239
240static int au1550nd_attach_chip(struct nand_chip *chip)
241{
242 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
243 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
244 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
245
246 return 0;
247}
248
249static const struct nand_controller_ops au1550nd_ops = {
250 .exec_op = au1550nd_exec_op,
251 .attach_chip = au1550nd_attach_chip,
252};
253
254static int au1550nd_probe(struct platform_device *pdev)
255{
256 struct au1550nd_platdata *pd;
257 struct au1550nd_ctx *ctx;
258 struct nand_chip *this;
259 struct mtd_info *mtd;
260 struct resource *r;
261 int ret, cs;
262
263 pd = dev_get_platdata(dev: &pdev->dev);
264 if (!pd) {
265 dev_err(&pdev->dev, "missing platform data\n");
266 return -ENODEV;
267 }
268
269 ctx = kzalloc(size: sizeof(*ctx), GFP_KERNEL);
270 if (!ctx)
271 return -ENOMEM;
272
273 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
274 if (!r) {
275 dev_err(&pdev->dev, "no NAND memory resource\n");
276 ret = -ENODEV;
277 goto out1;
278 }
279 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
280 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
281 ret = -ENOMEM;
282 goto out1;
283 }
284
285 ctx->base = ioremap(offset: r->start, size: 0x1000);
286 if (!ctx->base) {
287 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
288 ret = -ENODEV;
289 goto out2;
290 }
291
292 this = &ctx->chip;
293 mtd = nand_to_mtd(chip: this);
294 mtd->dev.parent = &pdev->dev;
295
296 /* figure out which CS# r->start belongs to */
297 cs = find_nand_cs(nand_base: r->start);
298 if (cs < 0) {
299 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
300 ret = -ENODEV;
301 goto out3;
302 }
303 ctx->cs = cs;
304
305 nand_controller_init(nfc: &ctx->controller);
306 ctx->controller.ops = &au1550nd_ops;
307 this->controller = &ctx->controller;
308
309 if (pd->devwidth)
310 this->options |= NAND_BUSWIDTH_16;
311
312 /*
313 * This driver assumes that the default ECC engine should be TYPE_SOFT.
314 * Set ->engine_type before registering the NAND devices in order to
315 * provide a driver specific default value.
316 */
317 this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
318
319 ret = nand_scan(chip: this, max_chips: 1);
320 if (ret) {
321 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
322 goto out3;
323 }
324
325 mtd_device_register(mtd, pd->parts, pd->num_parts);
326
327 platform_set_drvdata(pdev, data: ctx);
328
329 return 0;
330
331out3:
332 iounmap(addr: ctx->base);
333out2:
334 release_mem_region(r->start, resource_size(r));
335out1:
336 kfree(objp: ctx);
337 return ret;
338}
339
340static void au1550nd_remove(struct platform_device *pdev)
341{
342 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
343 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
344 struct nand_chip *chip = &ctx->chip;
345 int ret;
346
347 ret = mtd_device_unregister(master: nand_to_mtd(chip));
348 WARN_ON(ret);
349 nand_cleanup(chip);
350 iounmap(addr: ctx->base);
351 release_mem_region(r->start, 0x1000);
352 kfree(objp: ctx);
353}
354
355static struct platform_driver au1550nd_driver = {
356 .driver = {
357 .name = "au1550-nand",
358 },
359 .probe = au1550nd_probe,
360 .remove_new = au1550nd_remove,
361};
362
363module_platform_driver(au1550nd_driver);
364
365MODULE_LICENSE("GPL");
366MODULE_AUTHOR("Embedded Edge, LLC");
367MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
368

source code of linux/drivers/mtd/nand/raw/au1550nd.c