1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * NAND Flash Controller Device Driver |
4 | * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. |
5 | */ |
6 | |
7 | #ifndef __DENALI_H__ |
8 | #define __DENALI_H__ |
9 | |
10 | #include <linux/bits.h> |
11 | #include <linux/completion.h> |
12 | #include <linux/list.h> |
13 | #include <linux/mtd/rawnand.h> |
14 | #include <linux/spinlock_types.h> |
15 | #include <linux/types.h> |
16 | |
17 | #define DEVICE_RESET 0x0 |
18 | #define DEVICE_RESET__BANK(bank) BIT(bank) |
19 | |
20 | #define TRANSFER_SPARE_REG 0x10 |
21 | #define TRANSFER_SPARE_REG__FLAG BIT(0) |
22 | |
23 | #define LOAD_WAIT_CNT 0x20 |
24 | #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0) |
25 | |
26 | #define PROGRAM_WAIT_CNT 0x30 |
27 | #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0) |
28 | |
29 | #define ERASE_WAIT_CNT 0x40 |
30 | #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0) |
31 | |
32 | #define INT_MON_CYCCNT 0x50 |
33 | #define INT_MON_CYCCNT__VALUE GENMASK(15, 0) |
34 | |
35 | #define RB_PIN_ENABLED 0x60 |
36 | #define RB_PIN_ENABLED__BANK(bank) BIT(bank) |
37 | |
38 | #define MULTIPLANE_OPERATION 0x70 |
39 | #define MULTIPLANE_OPERATION__FLAG BIT(0) |
40 | |
41 | #define MULTIPLANE_READ_ENABLE 0x80 |
42 | #define MULTIPLANE_READ_ENABLE__FLAG BIT(0) |
43 | |
44 | #define COPYBACK_DISABLE 0x90 |
45 | #define COPYBACK_DISABLE__FLAG BIT(0) |
46 | |
47 | #define CACHE_WRITE_ENABLE 0xa0 |
48 | #define CACHE_WRITE_ENABLE__FLAG BIT(0) |
49 | |
50 | #define CACHE_READ_ENABLE 0xb0 |
51 | #define CACHE_READ_ENABLE__FLAG BIT(0) |
52 | |
53 | #define PREFETCH_MODE 0xc0 |
54 | #define PREFETCH_MODE__PREFETCH_EN BIT(0) |
55 | #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4) |
56 | |
57 | #define CHIP_ENABLE_DONT_CARE 0xd0 |
58 | #define CHIP_EN_DONT_CARE__FLAG BIT(0) |
59 | |
60 | #define ECC_ENABLE 0xe0 |
61 | #define ECC_ENABLE__FLAG BIT(0) |
62 | |
63 | #define GLOBAL_INT_ENABLE 0xf0 |
64 | #define GLOBAL_INT_EN_FLAG BIT(0) |
65 | |
66 | #define TWHR2_AND_WE_2_RE 0x100 |
67 | #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0) |
68 | #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8) |
69 | |
70 | #define TCWAW_AND_ADDR_2_DATA 0x110 |
71 | /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */ |
72 | #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0) |
73 | #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8) |
74 | |
75 | #define RE_2_WE 0x120 |
76 | #define RE_2_WE__VALUE GENMASK(5, 0) |
77 | |
78 | #define ACC_CLKS 0x130 |
79 | #define ACC_CLKS__VALUE GENMASK(3, 0) |
80 | |
81 | #define NUMBER_OF_PLANES 0x140 |
82 | #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0) |
83 | |
84 | #define PAGES_PER_BLOCK 0x150 |
85 | #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0) |
86 | |
87 | #define DEVICE_WIDTH 0x160 |
88 | #define DEVICE_WIDTH__VALUE GENMASK(1, 0) |
89 | |
90 | #define DEVICE_MAIN_AREA_SIZE 0x170 |
91 | #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0) |
92 | |
93 | #define DEVICE_SPARE_AREA_SIZE 0x180 |
94 | #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0) |
95 | |
96 | #define TWO_ROW_ADDR_CYCLES 0x190 |
97 | #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0) |
98 | |
99 | #define MULTIPLANE_ADDR_RESTRICT 0x1a0 |
100 | #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0) |
101 | |
102 | #define ECC_CORRECTION 0x1b0 |
103 | #define ECC_CORRECTION__VALUE GENMASK(4, 0) |
104 | #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) |
105 | |
106 | #define READ_MODE 0x1c0 |
107 | #define READ_MODE__VALUE GENMASK(3, 0) |
108 | |
109 | #define WRITE_MODE 0x1d0 |
110 | #define WRITE_MODE__VALUE GENMASK(3, 0) |
111 | |
112 | #define COPYBACK_MODE 0x1e0 |
113 | #define COPYBACK_MODE__VALUE GENMASK(3, 0) |
114 | |
115 | #define RDWR_EN_LO_CNT 0x1f0 |
116 | #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0) |
117 | |
118 | #define RDWR_EN_HI_CNT 0x200 |
119 | #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0) |
120 | |
121 | #define MAX_RD_DELAY 0x210 |
122 | #define MAX_RD_DELAY__VALUE GENMASK(3, 0) |
123 | |
124 | #define CS_SETUP_CNT 0x220 |
125 | #define CS_SETUP_CNT__VALUE GENMASK(4, 0) |
126 | #define CS_SETUP_CNT__TWB GENMASK(17, 12) |
127 | |
128 | #define SPARE_AREA_SKIP_BYTES 0x230 |
129 | #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0) |
130 | |
131 | #define SPARE_AREA_MARKER 0x240 |
132 | #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0) |
133 | |
134 | #define DEVICES_CONNECTED 0x250 |
135 | #define DEVICES_CONNECTED__VALUE GENMASK(2, 0) |
136 | |
137 | #define DIE_MASK 0x260 |
138 | #define DIE_MASK__VALUE GENMASK(7, 0) |
139 | |
140 | #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 |
141 | #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0) |
142 | |
143 | #define WRITE_PROTECT 0x280 |
144 | #define WRITE_PROTECT__FLAG BIT(0) |
145 | |
146 | #define RE_2_RE 0x290 |
147 | #define RE_2_RE__VALUE GENMASK(5, 0) |
148 | |
149 | #define MANUFACTURER_ID 0x300 |
150 | #define MANUFACTURER_ID__VALUE GENMASK(7, 0) |
151 | |
152 | #define DEVICE_ID 0x310 |
153 | #define DEVICE_ID__VALUE GENMASK(7, 0) |
154 | |
155 | #define DEVICE_PARAM_0 0x320 |
156 | #define DEVICE_PARAM_0__VALUE GENMASK(7, 0) |
157 | |
158 | #define DEVICE_PARAM_1 0x330 |
159 | #define DEVICE_PARAM_1__VALUE GENMASK(7, 0) |
160 | |
161 | #define DEVICE_PARAM_2 0x340 |
162 | #define DEVICE_PARAM_2__VALUE GENMASK(7, 0) |
163 | |
164 | #define LOGICAL_PAGE_DATA_SIZE 0x350 |
165 | #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0) |
166 | |
167 | #define LOGICAL_PAGE_SPARE_SIZE 0x360 |
168 | #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0) |
169 | |
170 | #define REVISION 0x370 |
171 | #define REVISION__VALUE GENMASK(15, 0) |
172 | |
173 | #define ONFI_DEVICE_FEATURES 0x380 |
174 | #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0) |
175 | |
176 | #define ONFI_OPTIONAL_COMMANDS 0x390 |
177 | #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0) |
178 | |
179 | #define ONFI_TIMING_MODE 0x3a0 |
180 | #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0) |
181 | |
182 | #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 |
183 | #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0) |
184 | |
185 | #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 |
186 | #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0) |
187 | #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8) |
188 | |
189 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 |
190 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0) |
191 | |
192 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 |
193 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0) |
194 | |
195 | #define FEATURES 0x3f0 |
196 | #define FEATURES__N_BANKS GENMASK(1, 0) |
197 | #define FEATURES__ECC_MAX_ERR GENMASK(5, 2) |
198 | #define FEATURES__DMA BIT(6) |
199 | #define FEATURES__CMD_DMA BIT(7) |
200 | #define FEATURES__PARTITION BIT(8) |
201 | #define FEATURES__XDMA_SIDEBAND BIT(9) |
202 | #define FEATURES__GPREG BIT(10) |
203 | #define FEATURES__INDEX_ADDR BIT(11) |
204 | |
205 | #define TRANSFER_MODE 0x400 |
206 | #define TRANSFER_MODE__VALUE GENMASK(1, 0) |
207 | |
208 | #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) |
209 | #define INTR_EN(bank) (0x420 + (bank) * 0x50) |
210 | /* bit[1:0] is used differently depending on IP version */ |
211 | #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */ |
212 | #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */ |
213 | #define INTR__ECC_ERR BIT(1) /* old IP */ |
214 | #define INTR__DMA_CMD_COMP BIT(2) |
215 | #define INTR__TIME_OUT BIT(3) |
216 | #define INTR__PROGRAM_FAIL BIT(4) |
217 | #define INTR__ERASE_FAIL BIT(5) |
218 | #define INTR__LOAD_COMP BIT(6) |
219 | #define INTR__PROGRAM_COMP BIT(7) |
220 | #define INTR__ERASE_COMP BIT(8) |
221 | #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9) |
222 | #define INTR__LOCKED_BLK BIT(10) |
223 | #define INTR__UNSUP_CMD BIT(11) |
224 | #define INTR__INT_ACT BIT(12) |
225 | #define INTR__RST_COMP BIT(13) |
226 | #define INTR__PIPE_CMD_ERR BIT(14) |
227 | #define INTR__PAGE_XFER_INC BIT(15) |
228 | #define INTR__ERASED_PAGE BIT(16) |
229 | |
230 | #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) |
231 | #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) |
232 | #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) |
233 | |
234 | #define ECC_THRESHOLD 0x600 |
235 | #define ECC_THRESHOLD__VALUE GENMASK(9, 0) |
236 | |
237 | #define ECC_ERROR_BLOCK_ADDRESS 0x610 |
238 | #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0) |
239 | |
240 | #define ECC_ERROR_PAGE_ADDRESS 0x620 |
241 | #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0) |
242 | #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12) |
243 | |
244 | #define ECC_ERROR_ADDRESS 0x630 |
245 | #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0) |
246 | #define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12) |
247 | |
248 | #define ERR_CORRECTION_INFO 0x640 |
249 | #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0) |
250 | #define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8) |
251 | #define ERR_CORRECTION_INFO__UNCOR BIT(14) |
252 | #define ERR_CORRECTION_INFO__LAST_ERR BIT(15) |
253 | |
254 | #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) |
255 | #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) |
256 | #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0) |
257 | #define ECC_COR_INFO__UNCOR_ERR BIT(7) |
258 | |
259 | #define CFG_DATA_BLOCK_SIZE 0x6b0 |
260 | |
261 | #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0 |
262 | |
263 | #define CFG_NUM_DATA_BLOCKS 0x6d0 |
264 | |
265 | #define CFG_META_DATA_SIZE 0x6e0 |
266 | |
267 | #define DMA_ENABLE 0x700 |
268 | #define DMA_ENABLE__FLAG BIT(0) |
269 | |
270 | #define IGNORE_ECC_DONE 0x710 |
271 | #define IGNORE_ECC_DONE__FLAG BIT(0) |
272 | |
273 | #define DMA_INTR 0x720 |
274 | #define DMA_INTR_EN 0x730 |
275 | #define DMA_INTR__TARGET_ERROR BIT(0) |
276 | #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1) |
277 | #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2) |
278 | #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3) |
279 | #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4) |
280 | #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5) |
281 | |
282 | #define TARGET_ERR_ADDR_LO 0x740 |
283 | #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0) |
284 | |
285 | #define TARGET_ERR_ADDR_HI 0x750 |
286 | #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0) |
287 | |
288 | #define CHNL_ACTIVE 0x760 |
289 | #define CHNL_ACTIVE__CHANNEL0 BIT(0) |
290 | #define CHNL_ACTIVE__CHANNEL1 BIT(1) |
291 | #define CHNL_ACTIVE__CHANNEL2 BIT(2) |
292 | #define CHNL_ACTIVE__CHANNEL3 BIT(3) |
293 | |
294 | /** |
295 | * struct denali_chip_sel - per-CS data of Denali NAND |
296 | * |
297 | * @bank: bank id of the controller this CS is connected to |
298 | * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE |
299 | * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA |
300 | * @re_2_we: value of timing register RE_2_WE |
301 | * @acc_clks: value of timing register ACC_CLKS |
302 | * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT |
303 | * @rdwr_en_hi_cnt: value of timing register RDWR_EN_HI_CNT |
304 | * @cs_setup_cnt: value of timing register CS_SETUP_CNT |
305 | * @re_2_re: value of timing register RE_2_RE |
306 | */ |
307 | struct denali_chip_sel { |
308 | int bank; |
309 | u32 hwhr2_and_we_2_re; |
310 | u32 tcwaw_and_addr_2_data; |
311 | u32 re_2_we; |
312 | u32 acc_clks; |
313 | u32 rdwr_en_lo_cnt; |
314 | u32 rdwr_en_hi_cnt; |
315 | u32 cs_setup_cnt; |
316 | u32 re_2_re; |
317 | }; |
318 | |
319 | /** |
320 | * struct denali_chip - per-chip data of Denali NAND |
321 | * |
322 | * @chip: base NAND chip structure |
323 | * @node: node to be used to associate this chip with the controller |
324 | * @nsels: the number of CS lines of this chip |
325 | * @sels: the array of per-cs data |
326 | */ |
327 | struct denali_chip { |
328 | struct nand_chip chip; |
329 | struct list_head node; |
330 | unsigned int nsels; |
331 | struct denali_chip_sel sels[] __counted_by(nsels); |
332 | }; |
333 | |
334 | /** |
335 | * struct denali_controller - Denali NAND controller data |
336 | * |
337 | * @controller: base NAND controller structure |
338 | * @dev: device |
339 | * @chips: the list of chips attached to this controller |
340 | * @clk_rate: frequency of core clock |
341 | * @clk_x_rate: frequency of bus interface clock |
342 | * @reg: base of Register Interface |
343 | * @host: base of Host Data/Command interface |
344 | * @complete: completion used to wait for interrupts |
345 | * @irq: interrupt number |
346 | * @irq_mask: interrupt bits the controller is waiting for |
347 | * @irq_status: interrupt bits of events that have happened |
348 | * @irq_lock: lock to protect @irq_mask and @irq_status |
349 | * @dma_avail: set if DMA engine is available |
350 | * @devs_per_cs: number of devices connected in parallel |
351 | * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine |
352 | * @active_bank: active bank id |
353 | * @nbanks: the number of banks supported by this controller |
354 | * @revision: IP revision |
355 | * @caps: controller capabilities that cannot be detected run-time |
356 | * @ecc_caps: ECC engine capabilities |
357 | * @host_read: callback for read access of Host Data/Command Interface |
358 | * @host_write: callback for write access of Host Data/Command Interface |
359 | * @setup_dma: callback for setup of the Data DMA |
360 | */ |
361 | struct denali_controller { |
362 | struct nand_controller controller; |
363 | struct device *dev; |
364 | struct list_head chips; |
365 | unsigned long clk_rate; |
366 | unsigned long clk_x_rate; |
367 | void __iomem *reg; |
368 | void __iomem *host; |
369 | struct completion complete; |
370 | int irq; |
371 | u32 irq_mask; |
372 | u32 irq_status; |
373 | spinlock_t irq_lock; |
374 | bool dma_avail; |
375 | int devs_per_cs; |
376 | int oob_skip_bytes; |
377 | int active_bank; |
378 | int nbanks; |
379 | unsigned int revision; |
380 | unsigned int caps; |
381 | const struct nand_ecc_caps *ecc_caps; |
382 | u32 (*host_read)(struct denali_controller *denali, u32 addr); |
383 | void (*host_write)(struct denali_controller *denali, u32 addr, |
384 | u32 data); |
385 | void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr, |
386 | int page, bool write); |
387 | }; |
388 | |
389 | #define DENALI_CAP_HW_ECC_FIXUP BIT(0) |
390 | #define DENALI_CAP_DMA_64BIT BIT(1) |
391 | |
392 | int denali_calc_ecc_bytes(int step_size, int strength); |
393 | int denali_chip_init(struct denali_controller *denali, |
394 | struct denali_chip *dchip); |
395 | int denali_init(struct denali_controller *denali); |
396 | void denali_remove(struct denali_controller *denali); |
397 | |
398 | #endif /* __DENALI_H__ */ |
399 | |