1/*
2 * NAND support for Marvell Orion SoC platforms
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/of.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/rawnand.h>
17#include <linux/mtd/partitions.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/sizes.h>
22#include <linux/platform_data/mtd-orion_nand.h>
23
24struct orion_nand_info {
25 struct nand_controller controller;
26 struct nand_chip chip;
27 struct clk *clk;
28};
29
30static void orion_nand_cmd_ctrl(struct nand_chip *nc, int cmd,
31 unsigned int ctrl)
32{
33 struct orion_nand_data *board = nand_get_controller_data(chip: nc);
34 u32 offs;
35
36 if (cmd == NAND_CMD_NONE)
37 return;
38
39 if (ctrl & NAND_CLE)
40 offs = (1 << board->cle);
41 else if (ctrl & NAND_ALE)
42 offs = (1 << board->ale);
43 else
44 return;
45
46 if (nc->options & NAND_BUSWIDTH_16)
47 offs <<= 1;
48
49 writeb(val: cmd, addr: nc->legacy.IO_ADDR_W + offs);
50}
51
52static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
53{
54 void __iomem *io_base = chip->legacy.IO_ADDR_R;
55#if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
56 uint64_t *buf64;
57#endif
58 int i = 0;
59
60 while (len && (unsigned long)buf & 7) {
61 *buf++ = readb(addr: io_base);
62 len--;
63 }
64#if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
65 buf64 = (uint64_t *)buf;
66 while (i < len/8) {
67 /*
68 * Since GCC has no proper constraint (PR 43518)
69 * force x variable to r2/r3 registers as ldrd instruction
70 * requires first register to be even.
71 */
72 register uint64_t x asm ("r2");
73
74 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
75 buf64[i++] = x;
76 }
77 i *= 8;
78#else
79 readsl(addr: io_base, buffer: buf, count: len/4);
80 i = len / 4 * 4;
81#endif
82 while (i < len)
83 buf[i++] = readb(addr: io_base);
84}
85
86static int orion_nand_attach_chip(struct nand_chip *chip)
87{
88 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
89 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
90 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
91
92 return 0;
93}
94
95static const struct nand_controller_ops orion_nand_ops = {
96 .attach_chip = orion_nand_attach_chip,
97};
98
99static int __init orion_nand_probe(struct platform_device *pdev)
100{
101 struct orion_nand_info *info;
102 struct mtd_info *mtd;
103 struct nand_chip *nc;
104 struct orion_nand_data *board;
105 void __iomem *io_base;
106 int ret = 0;
107 u32 val = 0;
108
109 info = devm_kzalloc(dev: &pdev->dev,
110 size: sizeof(struct orion_nand_info),
111 GFP_KERNEL);
112 if (!info)
113 return -ENOMEM;
114 nc = &info->chip;
115 mtd = nand_to_mtd(chip: nc);
116
117 nand_controller_init(nfc: &info->controller);
118 info->controller.ops = &orion_nand_ops;
119 nc->controller = &info->controller;
120
121 io_base = devm_platform_ioremap_resource(pdev, index: 0);
122
123 if (IS_ERR(ptr: io_base))
124 return PTR_ERR(ptr: io_base);
125
126 if (pdev->dev.of_node) {
127 board = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct orion_nand_data),
128 GFP_KERNEL);
129 if (!board)
130 return -ENOMEM;
131 if (!of_property_read_u32(np: pdev->dev.of_node, propname: "cle", out_value: &val))
132 board->cle = (u8)val;
133 else
134 board->cle = 0;
135 if (!of_property_read_u32(np: pdev->dev.of_node, propname: "ale", out_value: &val))
136 board->ale = (u8)val;
137 else
138 board->ale = 1;
139 if (!of_property_read_u32(np: pdev->dev.of_node,
140 propname: "bank-width", out_value: &val))
141 board->width = (u8)val * 8;
142 else
143 board->width = 8;
144 if (!of_property_read_u32(np: pdev->dev.of_node,
145 propname: "chip-delay", out_value: &val))
146 board->chip_delay = (u8)val;
147 } else {
148 board = dev_get_platdata(dev: &pdev->dev);
149 }
150
151 mtd->dev.parent = &pdev->dev;
152
153 nand_set_controller_data(chip: nc, priv: board);
154 nand_set_flash_node(chip: nc, np: pdev->dev.of_node);
155 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
156 nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
157 nc->legacy.read_buf = orion_nand_read_buf;
158
159 if (board->chip_delay)
160 nc->legacy.chip_delay = board->chip_delay;
161
162 WARN(board->width > 16,
163 "%d bit bus width out of range",
164 board->width);
165
166 if (board->width == 16)
167 nc->options |= NAND_BUSWIDTH_16;
168
169 platform_set_drvdata(pdev, data: info);
170
171 /* Not all platforms can gate the clock, so it is optional. */
172 info->clk = devm_clk_get_optional_enabled(dev: &pdev->dev, NULL);
173 if (IS_ERR(ptr: info->clk))
174 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: info->clk),
175 fmt: "failed to get and enable clock!\n");
176
177 /*
178 * This driver assumes that the default ECC engine should be TYPE_SOFT.
179 * Set ->engine_type before registering the NAND devices in order to
180 * provide a driver specific default value.
181 */
182 nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
183
184 ret = nand_scan(chip: nc, max_chips: 1);
185 if (ret)
186 return ret;
187
188 mtd->name = "orion_nand";
189 ret = mtd_device_register(mtd, board->parts, board->nr_parts);
190 if (ret)
191 nand_cleanup(chip: nc);
192
193 return ret;
194}
195
196static void orion_nand_remove(struct platform_device *pdev)
197{
198 struct orion_nand_info *info = platform_get_drvdata(pdev);
199 struct nand_chip *chip = &info->chip;
200 int ret;
201
202 ret = mtd_device_unregister(master: nand_to_mtd(chip));
203 WARN_ON(ret);
204
205 nand_cleanup(chip);
206}
207
208#ifdef CONFIG_OF
209static const struct of_device_id orion_nand_of_match_table[] = {
210 { .compatible = "marvell,orion-nand", },
211 {},
212};
213MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
214#endif
215
216static struct platform_driver orion_nand_driver = {
217 .remove_new = orion_nand_remove,
218 .driver = {
219 .name = "orion_nand",
220 .of_match_table = of_match_ptr(orion_nand_of_match_table),
221 },
222};
223
224module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
225
226MODULE_LICENSE("GPL");
227MODULE_AUTHOR("Tzachi Perelstein");
228MODULE_DESCRIPTION("NAND glue for Orion platforms");
229MODULE_ALIAS("platform:orion_nand");
230

source code of linux/drivers/mtd/nand/raw/orion_nand.c