1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> |
3 | * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> |
4 | * |
5 | * Derived from the PCAN project file driver/src/pcan_pci.c: |
6 | * |
7 | * Copyright (C) 2001-2006 PEAK System-Technik GmbH |
8 | */ |
9 | |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/netdevice.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/pci.h> |
16 | #include <linux/io.h> |
17 | #include <linux/can.h> |
18 | #include <linux/can/dev.h> |
19 | |
20 | #include "peak_canfd_user.h" |
21 | |
22 | MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>" ); |
23 | MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards" ); |
24 | MODULE_LICENSE("GPL v2" ); |
25 | |
26 | #define PCIEFD_DRV_NAME "peak_pciefd" |
27 | |
28 | #define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */ |
29 | #define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */ |
30 | #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */ |
31 | #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */ |
32 | #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */ |
33 | #define PCAN_PCIEFD_OEM_ID 0x0019 /* for PCIe slot OEM cards */ |
34 | #define PCAN_M2_ID 0x001a /* for M2 slot cards */ |
35 | |
36 | /* PEAK PCIe board access description */ |
37 | #define PCIEFD_BAR0_SIZE (64 * 1024) |
38 | #define PCIEFD_RX_DMA_SIZE (4 * 1024) |
39 | #define PCIEFD_TX_DMA_SIZE (4 * 1024) |
40 | |
41 | #define PCIEFD_TX_PAGE_SIZE (2 * 1024) |
42 | |
43 | /* System Control Registers */ |
44 | #define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */ |
45 | #define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */ |
46 | |
47 | /* Version info registers */ |
48 | #define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */ |
49 | #define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */ |
50 | |
51 | #define PCIEFD_FW_VERSION(x, y, z) (((u32)(x) << 24) | \ |
52 | ((u32)(y) << 16) | \ |
53 | ((u32)(z) << 8)) |
54 | |
55 | /* System Control Registers Bits */ |
56 | #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */ |
57 | #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */ |
58 | |
59 | /* CAN-FD channel addresses */ |
60 | #define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000) |
61 | |
62 | #define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF |
63 | |
64 | /* CAN-FD channel registers */ |
65 | #define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */ |
66 | #define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */ |
67 | #define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */ |
68 | #define PCIEFD_REG_CAN_CMD_PORT_H 0x0014 |
69 | #define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */ |
70 | #define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */ |
71 | #define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */ |
72 | #define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */ |
73 | #define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044 |
74 | #define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */ |
75 | #define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */ |
76 | #define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */ |
77 | #define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */ |
78 | #define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */ |
79 | #define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074 |
80 | |
81 | /* CAN-FD channel misc register bits */ |
82 | #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ |
83 | |
84 | /* CAN-FD channel Clock SELector Source & DIVider */ |
85 | #define CANFD_CLK_SEL_DIV_MASK 0x00000007 |
86 | #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ |
87 | #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ |
88 | #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ |
89 | #define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */ |
90 | #define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */ |
91 | |
92 | #define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */ |
93 | #define CANFD_CLK_SEL_SRC_240MHZ 0x00000008 |
94 | #define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \ |
95 | CANFD_CLK_SEL_SRC_MASK) |
96 | |
97 | #define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ |
98 | CANFD_CLK_SEL_DIV_20MHZ) |
99 | #define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ |
100 | CANFD_CLK_SEL_DIV_24MHZ) |
101 | #define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ |
102 | CANFD_CLK_SEL_DIV_30MHZ) |
103 | #define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ |
104 | CANFD_CLK_SEL_DIV_40MHZ) |
105 | #define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ |
106 | CANFD_CLK_SEL_DIV_60MHZ) |
107 | #define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ) |
108 | |
109 | /* CAN-FD channel Rx/Tx control register bits */ |
110 | #define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */ |
111 | #define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */ |
112 | #define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */ |
113 | |
114 | /* Rx IRQ Count and Time Limits */ |
115 | #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ |
116 | #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ |
117 | |
118 | /* Tx anticipation window (link logical address should be aligned on 2K |
119 | * boundary) |
120 | */ |
121 | #define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE) |
122 | |
123 | #define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */ |
124 | |
125 | /* 32-bits IRQ status fields, heading Rx DMA area */ |
126 | static inline int pciefd_irq_tag(u32 irq_status) |
127 | { |
128 | return irq_status & 0x0000000f; |
129 | } |
130 | |
131 | static inline int pciefd_irq_rx_cnt(u32 irq_status) |
132 | { |
133 | return (irq_status & 0x000007f0) >> 4; |
134 | } |
135 | |
136 | static inline int pciefd_irq_is_lnk(u32 irq_status) |
137 | { |
138 | return irq_status & 0x00010000; |
139 | } |
140 | |
141 | /* Rx record */ |
142 | struct pciefd_rx_dma { |
143 | __le32 irq_status; |
144 | __le32 sys_time_low; |
145 | __le32 sys_time_high; |
146 | struct pucan_rx_msg msg[]; |
147 | } __packed __aligned(4); |
148 | |
149 | /* Tx Link record */ |
150 | struct pciefd_tx_link { |
151 | __le16 size; |
152 | __le16 type; |
153 | __le32 laddr_lo; |
154 | __le32 laddr_hi; |
155 | } __packed __aligned(4); |
156 | |
157 | /* Tx page descriptor */ |
158 | struct pciefd_page { |
159 | void *vbase; /* page virtual address */ |
160 | dma_addr_t lbase; /* page logical address */ |
161 | u32 offset; |
162 | u32 size; |
163 | }; |
164 | |
165 | /* CAN-FD channel object */ |
166 | struct pciefd_board; |
167 | struct pciefd_can { |
168 | struct peak_canfd_priv ucan; /* must be the first member */ |
169 | void __iomem *reg_base; /* channel config base addr */ |
170 | struct pciefd_board *board; /* reverse link */ |
171 | |
172 | struct pucan_command pucan_cmd; /* command buffer */ |
173 | |
174 | dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */ |
175 | void *rx_dma_vaddr; /* for Rx and Tx areas */ |
176 | dma_addr_t tx_dma_laddr; |
177 | void *tx_dma_vaddr; |
178 | |
179 | struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT]; |
180 | u16 tx_pages_free; /* free Tx pages counter */ |
181 | u16 tx_page_index; /* current page used for Tx */ |
182 | spinlock_t tx_lock; |
183 | |
184 | u32 irq_status; |
185 | u32 irq_tag; /* next irq tag */ |
186 | }; |
187 | |
188 | /* PEAK-PCIe FD board object */ |
189 | struct pciefd_board { |
190 | void __iomem *reg_base; |
191 | struct pci_dev *pci_dev; |
192 | int can_count; |
193 | spinlock_t cmd_lock; /* 64-bits cmds must be atomic */ |
194 | struct pciefd_can *can[]; /* array of network devices */ |
195 | }; |
196 | |
197 | /* supported device ids. */ |
198 | static const struct pci_device_id peak_pciefd_tbl[] = { |
199 | {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
200 | {PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
201 | {PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
202 | {PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
203 | {PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
204 | {PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,}, |
205 | {0,} |
206 | }; |
207 | |
208 | MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl); |
209 | |
210 | /* read a 32 bits value from a SYS block register */ |
211 | static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) |
212 | { |
213 | return readl(addr: priv->reg_base + reg); |
214 | } |
215 | |
216 | /* write a 32 bits value into a SYS block register */ |
217 | static inline void pciefd_sys_writereg(const struct pciefd_board *priv, |
218 | u32 val, u16 reg) |
219 | { |
220 | writel(val, addr: priv->reg_base + reg); |
221 | } |
222 | |
223 | /* read a 32 bits value from CAN-FD block register */ |
224 | static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) |
225 | { |
226 | return readl(addr: priv->reg_base + reg); |
227 | } |
228 | |
229 | /* write a 32 bits value into a CAN-FD block register */ |
230 | static inline void pciefd_can_writereg(const struct pciefd_can *priv, |
231 | u32 val, u16 reg) |
232 | { |
233 | writel(val, addr: priv->reg_base + reg); |
234 | } |
235 | |
236 | /* give a channel logical Rx DMA address to the board */ |
237 | static void pciefd_can_setup_rx_dma(struct pciefd_can *priv) |
238 | { |
239 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
240 | const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32); |
241 | #else |
242 | const u32 dma_addr_h = 0; |
243 | #endif |
244 | |
245 | /* (DMA must be reset for Rx) */ |
246 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); |
247 | |
248 | /* write the logical address of the Rx DMA area for this channel */ |
249 | pciefd_can_writereg(priv, val: (u32)priv->rx_dma_laddr, |
250 | PCIEFD_REG_CAN_RX_DMA_ADDR_L); |
251 | pciefd_can_writereg(priv, val: dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H); |
252 | |
253 | /* also indicates that Rx DMA is cacheable */ |
254 | pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR); |
255 | } |
256 | |
257 | /* clear channel logical Rx DMA address from the board */ |
258 | static void pciefd_can_clear_rx_dma(struct pciefd_can *priv) |
259 | { |
260 | /* DMA must be reset for Rx */ |
261 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); |
262 | |
263 | /* clear the logical address of the Rx DMA area for this channel */ |
264 | pciefd_can_writereg(priv, val: 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L); |
265 | pciefd_can_writereg(priv, val: 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H); |
266 | } |
267 | |
268 | /* give a channel logical Tx DMA address to the board */ |
269 | static void pciefd_can_setup_tx_dma(struct pciefd_can *priv) |
270 | { |
271 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
272 | const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32); |
273 | #else |
274 | const u32 dma_addr_h = 0; |
275 | #endif |
276 | |
277 | /* (DMA must be reset for Tx) */ |
278 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); |
279 | |
280 | /* write the logical address of the Tx DMA area for this channel */ |
281 | pciefd_can_writereg(priv, val: (u32)priv->tx_dma_laddr, |
282 | PCIEFD_REG_CAN_TX_DMA_ADDR_L); |
283 | pciefd_can_writereg(priv, val: dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H); |
284 | |
285 | /* also indicates that Tx DMA is cacheable */ |
286 | pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); |
287 | } |
288 | |
289 | /* clear channel logical Tx DMA address from the board */ |
290 | static void pciefd_can_clear_tx_dma(struct pciefd_can *priv) |
291 | { |
292 | /* DMA must be reset for Tx */ |
293 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); |
294 | |
295 | /* clear the logical address of the Tx DMA area for this channel */ |
296 | pciefd_can_writereg(priv, val: 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L); |
297 | pciefd_can_writereg(priv, val: 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H); |
298 | } |
299 | |
300 | static void pciefd_can_ack_rx_dma(struct pciefd_can *priv) |
301 | { |
302 | /* read value of current IRQ tag and inc it for next one */ |
303 | priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr); |
304 | priv->irq_tag++; |
305 | priv->irq_tag &= 0xf; |
306 | |
307 | /* write the next IRQ tag for this CAN */ |
308 | pciefd_can_writereg(priv, val: priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK); |
309 | } |
310 | |
311 | /* IRQ handler */ |
312 | static irqreturn_t pciefd_irq_handler(int irq, void *arg) |
313 | { |
314 | struct pciefd_can *priv = arg; |
315 | struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr; |
316 | |
317 | /* INTA mode only to sync with PCIe transaction */ |
318 | if (!pci_dev_msi_enabled(pci_dev: priv->board->pci_dev)) |
319 | (void)pciefd_sys_readreg(priv: priv->board, PCIEFD_REG_SYS_VER1); |
320 | |
321 | /* read IRQ status from the first 32-bits of the Rx DMA area */ |
322 | priv->irq_status = le32_to_cpu(rx_dma->irq_status); |
323 | |
324 | /* check if this (shared) IRQ is for this CAN */ |
325 | if (pciefd_irq_tag(irq_status: priv->irq_status) != priv->irq_tag) |
326 | return IRQ_NONE; |
327 | |
328 | /* handle rx messages (if any) */ |
329 | peak_canfd_handle_msgs_list(priv: &priv->ucan, |
330 | rx_msg: rx_dma->msg, |
331 | rx_count: pciefd_irq_rx_cnt(irq_status: priv->irq_status)); |
332 | |
333 | /* handle tx link interrupt (if any) */ |
334 | if (pciefd_irq_is_lnk(irq_status: priv->irq_status)) { |
335 | unsigned long flags; |
336 | |
337 | spin_lock_irqsave(&priv->tx_lock, flags); |
338 | priv->tx_pages_free++; |
339 | spin_unlock_irqrestore(lock: &priv->tx_lock, flags); |
340 | |
341 | /* wake producer up (only if enough room in echo_skb array) */ |
342 | spin_lock_irqsave(&priv->ucan.echo_lock, flags); |
343 | if (!priv->ucan.can.echo_skb[priv->ucan.echo_idx]) |
344 | netif_wake_queue(dev: priv->ucan.ndev); |
345 | |
346 | spin_unlock_irqrestore(lock: &priv->ucan.echo_lock, flags); |
347 | } |
348 | |
349 | /* re-enable Rx DMA transfer for this CAN */ |
350 | pciefd_can_ack_rx_dma(priv); |
351 | |
352 | return IRQ_HANDLED; |
353 | } |
354 | |
355 | static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan) |
356 | { |
357 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
358 | int i; |
359 | |
360 | /* initialize the Tx pages descriptors */ |
361 | priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1; |
362 | priv->tx_page_index = 0; |
363 | |
364 | priv->tx_pages[0].vbase = priv->tx_dma_vaddr; |
365 | priv->tx_pages[0].lbase = priv->tx_dma_laddr; |
366 | |
367 | for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) { |
368 | priv->tx_pages[i].offset = 0; |
369 | priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE - |
370 | sizeof(struct pciefd_tx_link); |
371 | if (i) { |
372 | priv->tx_pages[i].vbase = |
373 | priv->tx_pages[i - 1].vbase + |
374 | PCIEFD_TX_PAGE_SIZE; |
375 | priv->tx_pages[i].lbase = |
376 | priv->tx_pages[i - 1].lbase + |
377 | PCIEFD_TX_PAGE_SIZE; |
378 | } |
379 | } |
380 | |
381 | /* setup Tx DMA addresses into IP core */ |
382 | pciefd_can_setup_tx_dma(priv); |
383 | |
384 | /* start (TX_RST=0) Tx Path */ |
385 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); |
386 | |
387 | return 0; |
388 | } |
389 | |
390 | /* board specific CANFD command pre-processing */ |
391 | static int pciefd_pre_cmd(struct peak_canfd_priv *ucan) |
392 | { |
393 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
394 | u16 cmd = pucan_cmd_get_opcode(c: &priv->pucan_cmd); |
395 | int err; |
396 | |
397 | /* pre-process command */ |
398 | switch (cmd) { |
399 | case PUCAN_CMD_NORMAL_MODE: |
400 | case PUCAN_CMD_LISTEN_ONLY_MODE: |
401 | |
402 | if (ucan->can.state == CAN_STATE_BUS_OFF) |
403 | break; |
404 | |
405 | /* going into operational mode: setup IRQ handler */ |
406 | err = request_irq(irq: priv->ucan.ndev->irq, |
407 | handler: pciefd_irq_handler, |
408 | IRQF_SHARED, |
409 | PCIEFD_DRV_NAME, |
410 | dev: priv); |
411 | if (err) |
412 | return err; |
413 | |
414 | /* setup Rx DMA address */ |
415 | pciefd_can_setup_rx_dma(priv); |
416 | |
417 | /* setup max count of msgs per IRQ */ |
418 | pciefd_can_writereg(priv, val: (CANFD_CTL_IRQ_TL_DEF) << 8 | |
419 | CANFD_CTL_IRQ_CL_DEF, |
420 | PCIEFD_REG_CAN_RX_CTL_WRT); |
421 | |
422 | /* clear DMA RST for Rx (Rx start) */ |
423 | pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, |
424 | PCIEFD_REG_CAN_RX_CTL_CLR); |
425 | |
426 | /* reset timestamps */ |
427 | pciefd_can_writereg(priv, val: !CANFD_MISC_TS_RST, |
428 | PCIEFD_REG_CAN_MISC); |
429 | |
430 | /* do an initial ACK */ |
431 | pciefd_can_ack_rx_dma(priv); |
432 | |
433 | /* enable IRQ for this CAN after having set next irq_tag */ |
434 | pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, |
435 | PCIEFD_REG_CAN_RX_CTL_SET); |
436 | |
437 | /* Tx path will be setup as soon as RX_BARRIER is received */ |
438 | break; |
439 | default: |
440 | break; |
441 | } |
442 | |
443 | return 0; |
444 | } |
445 | |
446 | /* write a command */ |
447 | static int pciefd_write_cmd(struct peak_canfd_priv *ucan) |
448 | { |
449 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
450 | unsigned long flags; |
451 | |
452 | /* 64-bits command is atomic */ |
453 | spin_lock_irqsave(&priv->board->cmd_lock, flags); |
454 | |
455 | pciefd_can_writereg(priv, val: *(u32 *)ucan->cmd_buffer, |
456 | PCIEFD_REG_CAN_CMD_PORT_L); |
457 | pciefd_can_writereg(priv, val: *(u32 *)(ucan->cmd_buffer + 4), |
458 | PCIEFD_REG_CAN_CMD_PORT_H); |
459 | |
460 | spin_unlock_irqrestore(lock: &priv->board->cmd_lock, flags); |
461 | |
462 | return 0; |
463 | } |
464 | |
465 | /* board specific CANFD command post-processing */ |
466 | static int pciefd_post_cmd(struct peak_canfd_priv *ucan) |
467 | { |
468 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
469 | u16 cmd = pucan_cmd_get_opcode(c: &priv->pucan_cmd); |
470 | |
471 | switch (cmd) { |
472 | case PUCAN_CMD_RESET_MODE: |
473 | |
474 | if (ucan->can.state == CAN_STATE_STOPPED) |
475 | break; |
476 | |
477 | /* controller now in reset mode: */ |
478 | |
479 | /* disable IRQ for this CAN */ |
480 | pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, |
481 | PCIEFD_REG_CAN_RX_CTL_CLR); |
482 | |
483 | /* stop and reset DMA addresses in Tx/Rx engines */ |
484 | pciefd_can_clear_tx_dma(priv); |
485 | pciefd_can_clear_rx_dma(priv); |
486 | |
487 | /* wait for above commands to complete (read cycle) */ |
488 | (void)pciefd_sys_readreg(priv: priv->board, PCIEFD_REG_SYS_VER1); |
489 | |
490 | free_irq(priv->ucan.ndev->irq, priv); |
491 | |
492 | ucan->can.state = CAN_STATE_STOPPED; |
493 | |
494 | break; |
495 | } |
496 | |
497 | return 0; |
498 | } |
499 | |
500 | static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size, |
501 | int *room_left) |
502 | { |
503 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
504 | struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; |
505 | unsigned long flags; |
506 | void *msg; |
507 | |
508 | spin_lock_irqsave(&priv->tx_lock, flags); |
509 | |
510 | if (page->offset + msg_size > page->size) { |
511 | struct pciefd_tx_link *lk; |
512 | |
513 | /* not enough space in this page: try another one */ |
514 | if (!priv->tx_pages_free) { |
515 | spin_unlock_irqrestore(lock: &priv->tx_lock, flags); |
516 | |
517 | /* Tx overflow */ |
518 | return NULL; |
519 | } |
520 | |
521 | priv->tx_pages_free--; |
522 | |
523 | /* keep address of the very last free slot of current page */ |
524 | lk = page->vbase + page->offset; |
525 | |
526 | /* next, move on a new free page */ |
527 | priv->tx_page_index = (priv->tx_page_index + 1) % |
528 | PCIEFD_TX_PAGE_COUNT; |
529 | page = priv->tx_pages + priv->tx_page_index; |
530 | |
531 | /* put link record to this new page at the end of prev one */ |
532 | lk->size = cpu_to_le16(sizeof(*lk)); |
533 | lk->type = cpu_to_le16(CANFD_MSG_LNK_TX); |
534 | lk->laddr_lo = cpu_to_le32(page->lbase); |
535 | |
536 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
537 | lk->laddr_hi = cpu_to_le32(page->lbase >> 32); |
538 | #else |
539 | lk->laddr_hi = 0; |
540 | #endif |
541 | /* next msgs will be put from the begininng of this new page */ |
542 | page->offset = 0; |
543 | } |
544 | |
545 | *room_left = priv->tx_pages_free * page->size; |
546 | |
547 | spin_unlock_irqrestore(lock: &priv->tx_lock, flags); |
548 | |
549 | msg = page->vbase + page->offset; |
550 | |
551 | /* give back room left in the tx ring */ |
552 | *room_left += page->size - (page->offset + msg_size); |
553 | |
554 | return msg; |
555 | } |
556 | |
557 | static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan, |
558 | struct pucan_tx_msg *msg) |
559 | { |
560 | struct pciefd_can *priv = (struct pciefd_can *)ucan; |
561 | struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; |
562 | |
563 | /* this slot is now reserved for writing the frame */ |
564 | page->offset += le16_to_cpu(msg->size); |
565 | |
566 | /* tell the board a frame has been written in Tx DMA area */ |
567 | pciefd_can_writereg(priv, val: 1, PCIEFD_REG_CAN_TX_REQ_ACC); |
568 | |
569 | return 0; |
570 | } |
571 | |
572 | /* probe for CAN-FD channel #pciefd_board->can_count */ |
573 | static int pciefd_can_probe(struct pciefd_board *pciefd) |
574 | { |
575 | struct net_device *ndev; |
576 | struct pciefd_can *priv; |
577 | u32 clk; |
578 | int err; |
579 | |
580 | /* allocate the candev object with default isize of echo skbs ring */ |
581 | ndev = alloc_peak_canfd_dev(sizeof_priv: sizeof(*priv), index: pciefd->can_count, |
582 | PCIEFD_ECHO_SKB_MAX); |
583 | if (!ndev) { |
584 | dev_err(&pciefd->pci_dev->dev, |
585 | "failed to alloc candev object\n" ); |
586 | goto failure; |
587 | } |
588 | |
589 | priv = netdev_priv(dev: ndev); |
590 | |
591 | /* fill-in candev private object: */ |
592 | |
593 | /* setup PCIe-FD own callbacks */ |
594 | priv->ucan.pre_cmd = pciefd_pre_cmd; |
595 | priv->ucan.write_cmd = pciefd_write_cmd; |
596 | priv->ucan.post_cmd = pciefd_post_cmd; |
597 | priv->ucan.enable_tx_path = pciefd_enable_tx_path; |
598 | priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg; |
599 | priv->ucan.write_tx_msg = pciefd_write_tx_msg; |
600 | |
601 | /* setup PCIe-FD own command buffer */ |
602 | priv->ucan.cmd_buffer = &priv->pucan_cmd; |
603 | priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd); |
604 | |
605 | priv->board = pciefd; |
606 | |
607 | /* CAN config regs block address */ |
608 | priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index); |
609 | |
610 | /* allocate non-cacheable DMA'able 4KB memory area for Rx */ |
611 | priv->rx_dma_vaddr = dmam_alloc_coherent(dev: &pciefd->pci_dev->dev, |
612 | PCIEFD_RX_DMA_SIZE, |
613 | dma_handle: &priv->rx_dma_laddr, |
614 | GFP_KERNEL); |
615 | if (!priv->rx_dma_vaddr) { |
616 | dev_err(&pciefd->pci_dev->dev, |
617 | "Rx dmam_alloc_coherent(%u) failure\n" , |
618 | PCIEFD_RX_DMA_SIZE); |
619 | goto err_free_candev; |
620 | } |
621 | |
622 | /* allocate non-cacheable DMA'able 4KB memory area for Tx */ |
623 | priv->tx_dma_vaddr = dmam_alloc_coherent(dev: &pciefd->pci_dev->dev, |
624 | PCIEFD_TX_DMA_SIZE, |
625 | dma_handle: &priv->tx_dma_laddr, |
626 | GFP_KERNEL); |
627 | if (!priv->tx_dma_vaddr) { |
628 | dev_err(&pciefd->pci_dev->dev, |
629 | "Tx dmam_alloc_coherent(%u) failure\n" , |
630 | PCIEFD_TX_DMA_SIZE); |
631 | goto err_free_candev; |
632 | } |
633 | |
634 | /* CAN clock in RST mode */ |
635 | pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC); |
636 | |
637 | /* read current clock value */ |
638 | clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL); |
639 | switch (clk) { |
640 | case CANFD_CLK_SEL_20MHZ: |
641 | priv->ucan.can.clock.freq = 20 * 1000 * 1000; |
642 | break; |
643 | case CANFD_CLK_SEL_24MHZ: |
644 | priv->ucan.can.clock.freq = 24 * 1000 * 1000; |
645 | break; |
646 | case CANFD_CLK_SEL_30MHZ: |
647 | priv->ucan.can.clock.freq = 30 * 1000 * 1000; |
648 | break; |
649 | case CANFD_CLK_SEL_40MHZ: |
650 | priv->ucan.can.clock.freq = 40 * 1000 * 1000; |
651 | break; |
652 | case CANFD_CLK_SEL_60MHZ: |
653 | priv->ucan.can.clock.freq = 60 * 1000 * 1000; |
654 | break; |
655 | default: |
656 | pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ, |
657 | PCIEFD_REG_CAN_CLK_SEL); |
658 | |
659 | fallthrough; |
660 | case CANFD_CLK_SEL_80MHZ: |
661 | priv->ucan.can.clock.freq = 80 * 1000 * 1000; |
662 | break; |
663 | } |
664 | |
665 | ndev->irq = pciefd->pci_dev->irq; |
666 | |
667 | SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev); |
668 | |
669 | err = register_candev(dev: ndev); |
670 | if (err) { |
671 | dev_err(&pciefd->pci_dev->dev, |
672 | "couldn't register CAN device: %d\n" , err); |
673 | goto err_free_candev; |
674 | } |
675 | |
676 | spin_lock_init(&priv->tx_lock); |
677 | |
678 | /* save the object address in the board structure */ |
679 | pciefd->can[pciefd->can_count] = priv; |
680 | |
681 | dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n" , |
682 | ndev->name, priv->reg_base, ndev->irq); |
683 | |
684 | return 0; |
685 | |
686 | err_free_candev: |
687 | free_candev(dev: ndev); |
688 | |
689 | failure: |
690 | return -ENOMEM; |
691 | } |
692 | |
693 | /* remove a CAN-FD channel by releasing all of its resources */ |
694 | static void pciefd_can_remove(struct pciefd_can *priv) |
695 | { |
696 | /* unregister (close) the can device to go back to RST mode first */ |
697 | unregister_candev(dev: priv->ucan.ndev); |
698 | |
699 | /* finally, free the candev object */ |
700 | free_candev(dev: priv->ucan.ndev); |
701 | } |
702 | |
703 | /* remove all CAN-FD channels by releasing their own resources */ |
704 | static void pciefd_can_remove_all(struct pciefd_board *pciefd) |
705 | { |
706 | while (pciefd->can_count > 0) |
707 | pciefd_can_remove(priv: pciefd->can[--pciefd->can_count]); |
708 | } |
709 | |
710 | /* probe for the entire device */ |
711 | static int peak_pciefd_probe(struct pci_dev *pdev, |
712 | const struct pci_device_id *ent) |
713 | { |
714 | struct pciefd_board *pciefd; |
715 | int err, can_count; |
716 | u16 sub_sys_id; |
717 | u8 hw_ver_major; |
718 | u8 hw_ver_minor; |
719 | u8 hw_ver_sub; |
720 | u32 v2; |
721 | |
722 | err = pci_enable_device(dev: pdev); |
723 | if (err) |
724 | return err; |
725 | err = pci_request_regions(pdev, PCIEFD_DRV_NAME); |
726 | if (err) |
727 | goto err_disable_pci; |
728 | |
729 | /* the number of channels depends on sub-system id */ |
730 | err = pci_read_config_word(dev: pdev, PCI_SUBSYSTEM_ID, val: &sub_sys_id); |
731 | if (err) |
732 | goto err_release_regions; |
733 | |
734 | dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n" , |
735 | pdev->vendor, pdev->device, sub_sys_id); |
736 | |
737 | if (sub_sys_id >= 0x0012) |
738 | can_count = 4; |
739 | else if (sub_sys_id >= 0x0010) |
740 | can_count = 3; |
741 | else if (sub_sys_id >= 0x0004) |
742 | can_count = 2; |
743 | else |
744 | can_count = 1; |
745 | |
746 | /* allocate board structure object */ |
747 | pciefd = devm_kzalloc(dev: &pdev->dev, struct_size(pciefd, can, can_count), |
748 | GFP_KERNEL); |
749 | if (!pciefd) { |
750 | err = -ENOMEM; |
751 | goto err_release_regions; |
752 | } |
753 | |
754 | /* initialize the board structure */ |
755 | pciefd->pci_dev = pdev; |
756 | spin_lock_init(&pciefd->cmd_lock); |
757 | |
758 | /* save the PCI BAR0 virtual address for further system regs access */ |
759 | pciefd->reg_base = pci_iomap(dev: pdev, bar: 0, PCIEFD_BAR0_SIZE); |
760 | if (!pciefd->reg_base) { |
761 | dev_err(&pdev->dev, "failed to map PCI resource #0\n" ); |
762 | err = -ENOMEM; |
763 | goto err_release_regions; |
764 | } |
765 | |
766 | /* read the firmware version number */ |
767 | v2 = pciefd_sys_readreg(priv: pciefd, PCIEFD_REG_SYS_VER2); |
768 | |
769 | hw_ver_major = (v2 & 0x0000f000) >> 12; |
770 | hw_ver_minor = (v2 & 0x00000f00) >> 8; |
771 | hw_ver_sub = (v2 & 0x000000f0) >> 4; |
772 | |
773 | dev_info(&pdev->dev, |
774 | "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n" , can_count, |
775 | hw_ver_major, hw_ver_minor, hw_ver_sub); |
776 | |
777 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
778 | /* FW < v3.3.0 DMA logic doesn't handle correctly the mix of 32-bit and |
779 | * 64-bit logical addresses: this workaround forces usage of 32-bit |
780 | * DMA addresses only when such a fw is detected. |
781 | */ |
782 | if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) < |
783 | PCIEFD_FW_VERSION(3, 3, 0)) { |
784 | err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(32)); |
785 | if (err) |
786 | dev_warn(&pdev->dev, |
787 | "warning: can't set DMA mask %llxh (err %d)\n" , |
788 | DMA_BIT_MASK(32), err); |
789 | } |
790 | #endif |
791 | |
792 | /* stop system clock */ |
793 | pciefd_sys_writereg(priv: pciefd, PCIEFD_SYS_CTL_CLK_EN, |
794 | PCIEFD_REG_SYS_CTL_CLR); |
795 | |
796 | pci_set_master(dev: pdev); |
797 | |
798 | /* create now the corresponding channels objects */ |
799 | while (pciefd->can_count < can_count) { |
800 | err = pciefd_can_probe(pciefd); |
801 | if (err) |
802 | goto err_free_canfd; |
803 | |
804 | pciefd->can_count++; |
805 | } |
806 | |
807 | /* set system timestamps counter in RST mode */ |
808 | pciefd_sys_writereg(priv: pciefd, PCIEFD_SYS_CTL_TS_RST, |
809 | PCIEFD_REG_SYS_CTL_SET); |
810 | |
811 | /* wait a bit (read cycle) */ |
812 | (void)pciefd_sys_readreg(priv: pciefd, PCIEFD_REG_SYS_VER1); |
813 | |
814 | /* free all clocks */ |
815 | pciefd_sys_writereg(priv: pciefd, PCIEFD_SYS_CTL_TS_RST, |
816 | PCIEFD_REG_SYS_CTL_CLR); |
817 | |
818 | /* start system clock */ |
819 | pciefd_sys_writereg(priv: pciefd, PCIEFD_SYS_CTL_CLK_EN, |
820 | PCIEFD_REG_SYS_CTL_SET); |
821 | |
822 | /* remember the board structure address in the device user data */ |
823 | pci_set_drvdata(pdev, data: pciefd); |
824 | |
825 | return 0; |
826 | |
827 | err_free_canfd: |
828 | pciefd_can_remove_all(pciefd); |
829 | |
830 | pci_iounmap(dev: pdev, pciefd->reg_base); |
831 | |
832 | err_release_regions: |
833 | pci_release_regions(pdev); |
834 | |
835 | err_disable_pci: |
836 | pci_disable_device(dev: pdev); |
837 | |
838 | /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while |
839 | * the probe() function must return a negative errno in case of failure |
840 | * (err is unchanged if negative) |
841 | */ |
842 | return pcibios_err_to_errno(err); |
843 | } |
844 | |
845 | /* free the board structure object, as well as its resources: */ |
846 | static void peak_pciefd_remove(struct pci_dev *pdev) |
847 | { |
848 | struct pciefd_board *pciefd = pci_get_drvdata(pdev); |
849 | |
850 | /* release CAN-FD channels resources */ |
851 | pciefd_can_remove_all(pciefd); |
852 | |
853 | pci_iounmap(dev: pdev, pciefd->reg_base); |
854 | |
855 | pci_release_regions(pdev); |
856 | pci_disable_device(dev: pdev); |
857 | } |
858 | |
859 | static struct pci_driver peak_pciefd_driver = { |
860 | .name = PCIEFD_DRV_NAME, |
861 | .id_table = peak_pciefd_tbl, |
862 | .probe = peak_pciefd_probe, |
863 | .remove = peak_pciefd_remove, |
864 | }; |
865 | |
866 | module_pci_driver(peak_pciefd_driver); |
867 | |