1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> |
4 | * |
5 | * Derived from the ems_pci.c driver: |
6 | * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> |
7 | * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> |
8 | * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> |
9 | */ |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/netdevice.h> |
15 | #include <linux/delay.h> |
16 | #include <linux/slab.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/can/dev.h> |
19 | #include <linux/io.h> |
20 | |
21 | #include "sja1000.h" |
22 | |
23 | #define DRV_NAME "sja1000_plx_pci" |
24 | |
25 | MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>" ); |
26 | MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " |
27 | "the SJA1000 chips" ); |
28 | MODULE_LICENSE("GPL v2" ); |
29 | |
30 | #define PLX_PCI_MAX_CHAN 2 |
31 | |
32 | struct plx_pci_card { |
33 | int channels; /* detected channels count */ |
34 | struct net_device *net_dev[PLX_PCI_MAX_CHAN]; |
35 | void __iomem *conf_addr; |
36 | |
37 | /* Pointer to device-dependent reset function */ |
38 | void (*reset_func)(struct pci_dev *pdev); |
39 | }; |
40 | |
41 | #define PLX_PCI_CAN_CLOCK (16000000 / 2) |
42 | |
43 | /* PLX9030/9050/9052 registers */ |
44 | #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ |
45 | #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, |
46 | * Serial EEPROM, and Initialization |
47 | * Control register |
48 | */ |
49 | |
50 | #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ |
51 | #define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */ |
52 | #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ |
53 | #define PLX_LINT2_POL (1 << 4) /* Local interrupt 2 polarity */ |
54 | #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ |
55 | #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ |
56 | |
57 | /* PLX9056 registers */ |
58 | #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ |
59 | #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ |
60 | |
61 | #define PLX9056_LINTI (1 << 11) |
62 | #define PLX9056_PCI_INT_EN (1 << 8) |
63 | #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ |
64 | |
65 | /* |
66 | * The board configuration is probably following: |
67 | * RX1 is connected to ground. |
68 | * TX1 is not connected. |
69 | * CLKO is not connected. |
70 | * Setting the OCR register to 0xDA is a good idea. |
71 | * This means normal output mode, push-pull and the correct polarity. |
72 | */ |
73 | #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) |
74 | |
75 | /* OCR setting for ASEM Dual CAN raw */ |
76 | #define ASEM_PCI_OCR 0xfe |
77 | |
78 | /* |
79 | * In the CDR register, you should set CBP to 1. |
80 | * You will probably also want to set the clock divider value to 7 |
81 | * (meaning direct oscillator output) because the second SJA1000 chip |
82 | * is driven by the first one CLKOUT output. |
83 | */ |
84 | #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) |
85 | |
86 | /* SJA1000 Control Register in the BasicCAN Mode */ |
87 | #define REG_CR 0x00 |
88 | |
89 | /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ |
90 | #define REG_CR_BASICCAN_INITIAL 0x21 |
91 | #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 |
92 | #define REG_SR_BASICCAN_INITIAL 0x0c |
93 | #define REG_IR_BASICCAN_INITIAL 0xe0 |
94 | |
95 | /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ |
96 | #define REG_MOD_PELICAN_INITIAL 0x01 |
97 | #define REG_SR_PELICAN_INITIAL 0x3c |
98 | #define REG_IR_PELICAN_INITIAL 0x00 |
99 | |
100 | #define ADLINK_PCI_VENDOR_ID 0x144A |
101 | #define ADLINK_PCI_DEVICE_ID 0x7841 |
102 | |
103 | #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 |
104 | #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 |
105 | #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e |
106 | #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b |
107 | #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 |
108 | #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 |
109 | |
110 | #define CAN200PCI_DEVICE_ID 0x9030 |
111 | #define CAN200PCI_VENDOR_ID 0x10b5 |
112 | #define CAN200PCI_SUB_DEVICE_ID 0x0301 |
113 | #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 |
114 | |
115 | #define IXXAT_PCI_VENDOR_ID 0x10b5 |
116 | #define IXXAT_PCI_DEVICE_ID 0x9050 |
117 | #define IXXAT_PCI_SUB_SYS_ID 0x2540 |
118 | |
119 | #define MARATHON_PCI_DEVICE_ID 0x2715 |
120 | #define MARATHON_PCIE_DEVICE_ID 0x3432 |
121 | |
122 | #define TEWS_PCI_VENDOR_ID 0x1498 |
123 | #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A |
124 | |
125 | #define CTI_PCI_VENDOR_ID 0x12c4 |
126 | #define CTI_PCI_DEVICE_ID_CRG001 0x0900 |
127 | |
128 | #define MOXA_PCI_VENDOR_ID 0x1393 |
129 | #define MOXA_PCI_DEVICE_ID 0x0100 |
130 | |
131 | #define ASEM_RAW_CAN_VENDOR_ID 0x10b5 |
132 | #define ASEM_RAW_CAN_DEVICE_ID 0x9030 |
133 | #define ASEM_RAW_CAN_SUB_VENDOR_ID 0x3000 |
134 | #define ASEM_RAW_CAN_SUB_DEVICE_ID 0x1001 |
135 | #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS 0x1002 |
136 | #define ASEM_RAW_CAN_RST_REGISTER 0x54 |
137 | #define ASEM_RAW_CAN_RST_MASK_CAN1 0x20 |
138 | #define ASEM_RAW_CAN_RST_MASK_CAN2 0x04 |
139 | |
140 | static void plx_pci_reset_common(struct pci_dev *pdev); |
141 | static void plx9056_pci_reset_common(struct pci_dev *pdev); |
142 | static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); |
143 | static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); |
144 | static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev); |
145 | |
146 | struct plx_pci_channel_map { |
147 | u32 bar; |
148 | u32 offset; |
149 | u32 size; /* 0x00 - auto, e.g. length of entire bar */ |
150 | }; |
151 | |
152 | struct plx_pci_card_info { |
153 | const char *name; |
154 | int channel_count; |
155 | u32 can_clock; |
156 | u8 ocr; /* output control register */ |
157 | u8 cdr; /* clock divider register */ |
158 | |
159 | /* Parameters for mapping local configuration space */ |
160 | struct plx_pci_channel_map conf_map; |
161 | |
162 | /* Parameters for mapping the SJA1000 chips */ |
163 | struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; |
164 | |
165 | /* Pointer to device-dependent reset function */ |
166 | void (*reset_func)(struct pci_dev *pdev); |
167 | }; |
168 | |
169 | static struct plx_pci_card_info plx_pci_card_info_adlink = { |
170 | "Adlink PCI-7841/cPCI-7841" , 2, |
171 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
172 | {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, |
173 | &plx_pci_reset_common |
174 | /* based on PLX9052 */ |
175 | }; |
176 | |
177 | static struct plx_pci_card_info plx_pci_card_info_adlink_se = { |
178 | "Adlink PCI-7841/cPCI-7841 SE" , 2, |
179 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
180 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, |
181 | &plx_pci_reset_common |
182 | /* based on PLX9052 */ |
183 | }; |
184 | |
185 | static struct plx_pci_card_info plx_pci_card_info_esd200 = { |
186 | "esd CAN-PCI/CPCI/PCI104/200" , 2, |
187 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
188 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, |
189 | &plx_pci_reset_common |
190 | /* based on PLX9030/9050 */ |
191 | }; |
192 | |
193 | static struct plx_pci_card_info plx_pci_card_info_esd266 = { |
194 | "esd CAN-PCI/PMC/266" , 2, |
195 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
196 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, |
197 | &plx9056_pci_reset_common |
198 | /* based on PLX9056 */ |
199 | }; |
200 | |
201 | static struct plx_pci_card_info plx_pci_card_info_esd2000 = { |
202 | "esd CAN-PCIe/2000" , 2, |
203 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
204 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, |
205 | &plx9056_pci_reset_common |
206 | /* based on PEX8311 */ |
207 | }; |
208 | |
209 | static struct plx_pci_card_info plx_pci_card_info_ixxat = { |
210 | "IXXAT PC-I 04/PCI" , 2, |
211 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
212 | {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, |
213 | &plx_pci_reset_common |
214 | /* based on PLX9050 */ |
215 | }; |
216 | |
217 | static struct plx_pci_card_info plx_pci_card_info_marathon_pci = { |
218 | "Marathon CAN-bus-PCI" , 2, |
219 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
220 | {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, |
221 | &plx_pci_reset_marathon_pci |
222 | /* based on PLX9052 */ |
223 | }; |
224 | |
225 | static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = { |
226 | "Marathon CAN-bus-PCIe" , 2, |
227 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
228 | {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} }, |
229 | &plx_pci_reset_marathon_pcie |
230 | /* based on PEX8311 */ |
231 | }; |
232 | |
233 | static struct plx_pci_card_info plx_pci_card_info_tews = { |
234 | "TEWS TECHNOLOGIES TPMC810" , 2, |
235 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
236 | {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, |
237 | &plx_pci_reset_common |
238 | /* based on PLX9030 */ |
239 | }; |
240 | |
241 | static struct plx_pci_card_info plx_pci_card_info_cti = { |
242 | "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)" , 2, |
243 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
244 | {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, |
245 | &plx_pci_reset_common |
246 | /* based on PLX9030 */ |
247 | }; |
248 | |
249 | static struct plx_pci_card_info plx_pci_card_info_elcus = { |
250 | "Eclus CAN-200-PCI" , 2, |
251 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
252 | {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, |
253 | &plx_pci_reset_common |
254 | /* based on PLX9030 */ |
255 | }; |
256 | |
257 | static struct plx_pci_card_info plx_pci_card_info_moxa = { |
258 | "MOXA" , 2, |
259 | PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, |
260 | {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} }, |
261 | &plx_pci_reset_common |
262 | /* based on PLX9052 */ |
263 | }; |
264 | |
265 | static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = { |
266 | "ASEM Dual CAN raw PCI" , 2, |
267 | PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR, |
268 | {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, |
269 | &plx_pci_reset_asem_dual_can_raw |
270 | /* based on PLX9030 */ |
271 | }; |
272 | |
273 | static const struct pci_device_id plx_pci_tbl[] = { |
274 | { |
275 | /* Adlink PCI-7841/cPCI-7841 */ |
276 | ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, |
277 | PCI_ANY_ID, PCI_ANY_ID, |
278 | PCI_CLASS_NETWORK_OTHER << 8, ~0, |
279 | (kernel_ulong_t)&plx_pci_card_info_adlink |
280 | }, |
281 | { |
282 | /* Adlink PCI-7841/cPCI-7841 SE */ |
283 | ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, |
284 | PCI_ANY_ID, PCI_ANY_ID, |
285 | PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, |
286 | (kernel_ulong_t)&plx_pci_card_info_adlink_se |
287 | }, |
288 | { |
289 | /* esd CAN-PCI/200 */ |
290 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
291 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, |
292 | 0, 0, |
293 | (kernel_ulong_t)&plx_pci_card_info_esd200 |
294 | }, |
295 | { |
296 | /* esd CAN-CPCI/200 */ |
297 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
298 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, |
299 | 0, 0, |
300 | (kernel_ulong_t)&plx_pci_card_info_esd200 |
301 | }, |
302 | { |
303 | /* esd CAN-PCI104/200 */ |
304 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
305 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, |
306 | 0, 0, |
307 | (kernel_ulong_t)&plx_pci_card_info_esd200 |
308 | }, |
309 | { |
310 | /* esd CAN-PCI/266 */ |
311 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, |
312 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, |
313 | 0, 0, |
314 | (kernel_ulong_t)&plx_pci_card_info_esd266 |
315 | }, |
316 | { |
317 | /* esd CAN-PMC/266 */ |
318 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, |
319 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, |
320 | 0, 0, |
321 | (kernel_ulong_t)&plx_pci_card_info_esd266 |
322 | }, |
323 | { |
324 | /* esd CAN-PCIE/2000 */ |
325 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, |
326 | PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, |
327 | 0, 0, |
328 | (kernel_ulong_t)&plx_pci_card_info_esd2000 |
329 | }, |
330 | { |
331 | /* IXXAT PC-I 04/PCI card */ |
332 | IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, |
333 | PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, |
334 | 0, 0, |
335 | (kernel_ulong_t)&plx_pci_card_info_ixxat |
336 | }, |
337 | { |
338 | /* Marathon CAN-bus-PCI card */ |
339 | PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, |
340 | PCI_ANY_ID, PCI_ANY_ID, |
341 | 0, 0, |
342 | (kernel_ulong_t)&plx_pci_card_info_marathon_pci |
343 | }, |
344 | { |
345 | /* Marathon CAN-bus-PCIe card */ |
346 | PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID, |
347 | PCI_ANY_ID, PCI_ANY_ID, |
348 | 0, 0, |
349 | (kernel_ulong_t)&plx_pci_card_info_marathon_pcie |
350 | }, |
351 | { |
352 | /* TEWS TECHNOLOGIES TPMC810 card */ |
353 | TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, |
354 | PCI_ANY_ID, PCI_ANY_ID, |
355 | 0, 0, |
356 | (kernel_ulong_t)&plx_pci_card_info_tews |
357 | }, |
358 | { |
359 | /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ |
360 | PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
361 | CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, |
362 | 0, 0, |
363 | (kernel_ulong_t)&plx_pci_card_info_cti |
364 | }, |
365 | { |
366 | /* Elcus CAN-200-PCI */ |
367 | CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, |
368 | CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, |
369 | 0, 0, |
370 | (kernel_ulong_t)&plx_pci_card_info_elcus |
371 | }, |
372 | { |
373 | /* moxa */ |
374 | MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID, |
375 | PCI_ANY_ID, PCI_ANY_ID, |
376 | 0, 0, |
377 | (kernel_ulong_t)&plx_pci_card_info_moxa |
378 | }, |
379 | { |
380 | /* ASEM Dual CAN raw */ |
381 | ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, |
382 | ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID, |
383 | 0, 0, |
384 | (kernel_ulong_t)&plx_pci_card_info_asem_dual_can |
385 | }, |
386 | { |
387 | /* ASEM Dual CAN raw -new model */ |
388 | ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, |
389 | ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS, |
390 | 0, 0, |
391 | (kernel_ulong_t)&plx_pci_card_info_asem_dual_can |
392 | }, |
393 | { 0,} |
394 | }; |
395 | MODULE_DEVICE_TABLE(pci, plx_pci_tbl); |
396 | |
397 | static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) |
398 | { |
399 | return ioread8(priv->reg_base + port); |
400 | } |
401 | |
402 | static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) |
403 | { |
404 | iowrite8(val, priv->reg_base + port); |
405 | } |
406 | |
407 | /* |
408 | * Check if a CAN controller is present at the specified location |
409 | * by trying to switch 'em from the Basic mode into the PeliCAN mode. |
410 | * Also check states of some registers in reset mode. |
411 | */ |
412 | static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) |
413 | { |
414 | int flag = 0; |
415 | |
416 | /* |
417 | * Check registers after hardware reset (the Basic mode) |
418 | * See states on p. 10 of the Datasheet. |
419 | */ |
420 | if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == |
421 | REG_CR_BASICCAN_INITIAL && |
422 | (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && |
423 | (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) |
424 | flag = 1; |
425 | |
426 | /* Bring the SJA1000 into the PeliCAN mode*/ |
427 | priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); |
428 | |
429 | /* |
430 | * Check registers after reset in the PeliCAN mode. |
431 | * See states on p. 23 of the Datasheet. |
432 | */ |
433 | if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && |
434 | priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && |
435 | priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) |
436 | return flag; |
437 | |
438 | return 0; |
439 | } |
440 | |
441 | /* |
442 | * PLX9030/50/52 software reset |
443 | * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). |
444 | * For most cards it's enough for reset the SJA1000 chips. |
445 | */ |
446 | static void plx_pci_reset_common(struct pci_dev *pdev) |
447 | { |
448 | struct plx_pci_card *card = pci_get_drvdata(pdev); |
449 | u32 cntrl; |
450 | |
451 | cntrl = ioread32(card->conf_addr + PLX_CNTRL); |
452 | cntrl |= PLX_PCI_RESET; |
453 | iowrite32(cntrl, card->conf_addr + PLX_CNTRL); |
454 | udelay(100); |
455 | cntrl ^= PLX_PCI_RESET; |
456 | iowrite32(cntrl, card->conf_addr + PLX_CNTRL); |
457 | }; |
458 | |
459 | /* |
460 | * PLX9056 software reset |
461 | * Assert LRESET# and reset device(s) on the Local Bus (if wired). |
462 | */ |
463 | static void plx9056_pci_reset_common(struct pci_dev *pdev) |
464 | { |
465 | struct plx_pci_card *card = pci_get_drvdata(pdev); |
466 | u32 cntrl; |
467 | |
468 | /* issue a local bus reset */ |
469 | cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); |
470 | cntrl |= PLX_PCI_RESET; |
471 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); |
472 | udelay(100); |
473 | cntrl ^= PLX_PCI_RESET; |
474 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); |
475 | |
476 | /* reload local configuration from EEPROM */ |
477 | cntrl |= PLX9056_PCI_RCR; |
478 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); |
479 | |
480 | /* |
481 | * There is no safe way to poll for the end |
482 | * of reconfiguration process. Waiting for 10ms |
483 | * is safe. |
484 | */ |
485 | mdelay(10); |
486 | |
487 | cntrl ^= PLX9056_PCI_RCR; |
488 | iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); |
489 | }; |
490 | |
491 | /* Special reset function for Marathon CAN-bus-PCI card */ |
492 | static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) |
493 | { |
494 | void __iomem *reset_addr; |
495 | int i; |
496 | static const int reset_bar[2] = {3, 5}; |
497 | |
498 | plx_pci_reset_common(pdev); |
499 | |
500 | for (i = 0; i < 2; i++) { |
501 | reset_addr = pci_iomap(dev: pdev, bar: reset_bar[i], max: 0); |
502 | if (!reset_addr) { |
503 | dev_err(&pdev->dev, "Failed to remap reset " |
504 | "space %d (BAR%d)\n" , i, reset_bar[i]); |
505 | } else { |
506 | /* reset the SJA1000 chip */ |
507 | iowrite8(0x1, reset_addr); |
508 | udelay(100); |
509 | pci_iounmap(dev: pdev, reset_addr); |
510 | } |
511 | } |
512 | } |
513 | |
514 | /* Special reset function for Marathon CAN-bus-PCIe card */ |
515 | static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) |
516 | { |
517 | void __iomem *addr; |
518 | void __iomem *reset_addr; |
519 | int i; |
520 | |
521 | plx9056_pci_reset_common(pdev); |
522 | |
523 | for (i = 0; i < 2; i++) { |
524 | struct plx_pci_channel_map *chan_map = |
525 | &plx_pci_card_info_marathon_pcie.chan_map_tbl[i]; |
526 | addr = pci_iomap(dev: pdev, bar: chan_map->bar, max: chan_map->size); |
527 | if (!addr) { |
528 | dev_err(&pdev->dev, "Failed to remap reset " |
529 | "space %d (BAR%d)\n" , i, chan_map->bar); |
530 | } else { |
531 | /* reset the SJA1000 chip */ |
532 | #define MARATHON_PCIE_RESET_OFFSET 32 |
533 | reset_addr = addr + chan_map->offset + |
534 | MARATHON_PCIE_RESET_OFFSET; |
535 | iowrite8(0x1, reset_addr); |
536 | udelay(100); |
537 | pci_iounmap(dev: pdev, addr); |
538 | } |
539 | } |
540 | } |
541 | |
542 | /* Special reset function for ASEM Dual CAN raw card */ |
543 | static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev) |
544 | { |
545 | void __iomem *bar0_addr; |
546 | u8 tmpval; |
547 | |
548 | plx_pci_reset_common(pdev); |
549 | |
550 | bar0_addr = pci_iomap(dev: pdev, bar: 0, max: 0); |
551 | if (!bar0_addr) { |
552 | dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n" ); |
553 | return; |
554 | } |
555 | |
556 | /* reset the two SJA1000 chips */ |
557 | tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER); |
558 | tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2); |
559 | iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); |
560 | usleep_range(min: 300, max: 400); |
561 | tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2; |
562 | iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); |
563 | usleep_range(min: 300, max: 400); |
564 | pci_iounmap(dev: pdev, bar0_addr); |
565 | } |
566 | |
567 | static void plx_pci_del_card(struct pci_dev *pdev) |
568 | { |
569 | struct plx_pci_card *card = pci_get_drvdata(pdev); |
570 | struct net_device *dev; |
571 | struct sja1000_priv *priv; |
572 | int i = 0; |
573 | |
574 | for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { |
575 | dev = card->net_dev[i]; |
576 | if (!dev) |
577 | continue; |
578 | |
579 | dev_info(&pdev->dev, "Removing %s\n" , dev->name); |
580 | unregister_sja1000dev(dev); |
581 | priv = netdev_priv(dev); |
582 | if (priv->reg_base) |
583 | pci_iounmap(dev: pdev, priv->reg_base); |
584 | free_sja1000dev(dev); |
585 | } |
586 | |
587 | card->reset_func(pdev); |
588 | |
589 | /* |
590 | * Disable interrupts from PCI-card and disable local |
591 | * interrupts |
592 | */ |
593 | if (pdev->device != PCI_DEVICE_ID_PLX_9056 && |
594 | pdev->device != MARATHON_PCIE_DEVICE_ID) |
595 | iowrite32(0x0, card->conf_addr + PLX_INTCSR); |
596 | else |
597 | iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); |
598 | |
599 | if (card->conf_addr) |
600 | pci_iounmap(dev: pdev, card->conf_addr); |
601 | |
602 | kfree(objp: card); |
603 | |
604 | pci_disable_device(dev: pdev); |
605 | } |
606 | |
607 | /* |
608 | * Probe PLX90xx based device for the SJA1000 chips and register each |
609 | * available CAN channel to SJA1000 Socket-CAN subsystem. |
610 | */ |
611 | static int plx_pci_add_card(struct pci_dev *pdev, |
612 | const struct pci_device_id *ent) |
613 | { |
614 | struct sja1000_priv *priv; |
615 | struct net_device *dev; |
616 | struct plx_pci_card *card; |
617 | struct plx_pci_card_info *ci; |
618 | int err, i; |
619 | u32 val; |
620 | void __iomem *addr; |
621 | |
622 | ci = (struct plx_pci_card_info *)ent->driver_data; |
623 | |
624 | if (pci_enable_device(dev: pdev) < 0) { |
625 | dev_err(&pdev->dev, "Failed to enable PCI device\n" ); |
626 | return -ENODEV; |
627 | } |
628 | |
629 | dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n" , |
630 | ci->name, PCI_SLOT(pdev->devfn)); |
631 | |
632 | /* Allocate card structures to hold addresses, ... */ |
633 | card = kzalloc(size: sizeof(*card), GFP_KERNEL); |
634 | if (!card) { |
635 | pci_disable_device(dev: pdev); |
636 | return -ENOMEM; |
637 | } |
638 | |
639 | pci_set_drvdata(pdev, data: card); |
640 | |
641 | card->channels = 0; |
642 | |
643 | /* Remap PLX90xx configuration space */ |
644 | addr = pci_iomap(dev: pdev, bar: ci->conf_map.bar, max: ci->conf_map.size); |
645 | if (!addr) { |
646 | err = -ENOMEM; |
647 | dev_err(&pdev->dev, "Failed to remap configuration space " |
648 | "(BAR%d)\n" , ci->conf_map.bar); |
649 | goto failure_cleanup; |
650 | } |
651 | card->conf_addr = addr + ci->conf_map.offset; |
652 | |
653 | ci->reset_func(pdev); |
654 | card->reset_func = ci->reset_func; |
655 | |
656 | /* Detect available channels */ |
657 | for (i = 0; i < ci->channel_count; i++) { |
658 | struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; |
659 | |
660 | dev = alloc_sja1000dev(sizeof_priv: 0); |
661 | if (!dev) { |
662 | err = -ENOMEM; |
663 | goto failure_cleanup; |
664 | } |
665 | |
666 | card->net_dev[i] = dev; |
667 | priv = netdev_priv(dev); |
668 | priv->priv = card; |
669 | priv->irq_flags = IRQF_SHARED; |
670 | |
671 | dev->irq = pdev->irq; |
672 | |
673 | /* |
674 | * Remap IO space of the SJA1000 chips |
675 | * This is device-dependent mapping |
676 | */ |
677 | addr = pci_iomap(dev: pdev, bar: cm->bar, max: cm->size); |
678 | if (!addr) { |
679 | err = -ENOMEM; |
680 | dev_err(&pdev->dev, "Failed to remap BAR%d\n" , cm->bar); |
681 | goto failure_cleanup; |
682 | } |
683 | |
684 | priv->reg_base = addr + cm->offset; |
685 | priv->read_reg = plx_pci_read_reg; |
686 | priv->write_reg = plx_pci_write_reg; |
687 | |
688 | /* Check if channel is present */ |
689 | if (plx_pci_check_sja1000(priv)) { |
690 | priv->can.clock.freq = ci->can_clock; |
691 | priv->ocr = ci->ocr; |
692 | priv->cdr = ci->cdr; |
693 | |
694 | SET_NETDEV_DEV(dev, &pdev->dev); |
695 | dev->dev_id = i; |
696 | |
697 | /* Register SJA1000 device */ |
698 | err = register_sja1000dev(dev); |
699 | if (err) { |
700 | dev_err(&pdev->dev, "Registering device failed " |
701 | "(err=%d)\n" , err); |
702 | goto failure_cleanup; |
703 | } |
704 | |
705 | card->channels++; |
706 | |
707 | dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " |
708 | "registered as %s\n" , i + 1, priv->reg_base, |
709 | dev->irq, dev->name); |
710 | } else { |
711 | dev_err(&pdev->dev, "Channel #%d not detected\n" , |
712 | i + 1); |
713 | free_sja1000dev(dev); |
714 | card->net_dev[i] = NULL; |
715 | } |
716 | } |
717 | |
718 | if (!card->channels) { |
719 | err = -ENODEV; |
720 | goto failure_cleanup; |
721 | } |
722 | |
723 | /* |
724 | * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, |
725 | * Local_2 interrupts from the SJA1000 chips |
726 | */ |
727 | if (pdev->device != PCI_DEVICE_ID_PLX_9056 && |
728 | pdev->device != MARATHON_PCIE_DEVICE_ID) { |
729 | val = ioread32(card->conf_addr + PLX_INTCSR); |
730 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) |
731 | val |= PLX_LINT1_EN | PLX_PCI_INT_EN; |
732 | else |
733 | val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; |
734 | iowrite32(val, card->conf_addr + PLX_INTCSR); |
735 | } else { |
736 | iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, |
737 | card->conf_addr + PLX9056_INTCSR); |
738 | } |
739 | return 0; |
740 | |
741 | failure_cleanup: |
742 | dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n" , err); |
743 | |
744 | plx_pci_del_card(pdev); |
745 | |
746 | return err; |
747 | } |
748 | |
749 | static struct pci_driver plx_pci_driver = { |
750 | .name = DRV_NAME, |
751 | .id_table = plx_pci_tbl, |
752 | .probe = plx_pci_add_card, |
753 | .remove = plx_pci_del_card, |
754 | }; |
755 | |
756 | module_pci_driver(plx_pci_driver); |
757 | |