| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Broadcom Starfighter 2 switch register defines |
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| 4 | * |
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| 5 | * Copyright (C) 2014, Broadcom Corporation |
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| 6 | */ |
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| 7 | #ifndef __BCM_SF2_REGS_H |
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| 8 | #define __BCM_SF2_REGS_H |
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| 9 | |
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| 10 | /* Register set relative to 'REG' */ |
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| 11 | |
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| 12 | enum bcm_sf2_reg_offs { |
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| 13 | REG_SWITCH_CNTRL = 0, |
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| 14 | REG_SWITCH_STATUS, |
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| 15 | REG_DIR_DATA_WRITE, |
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| 16 | REG_DIR_DATA_READ, |
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| 17 | REG_SWITCH_REVISION, |
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| 18 | REG_PHY_REVISION, |
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| 19 | REG_SPHY_CNTRL, |
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| 20 | REG_CROSSBAR, |
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| 21 | REG_RGMII_0_CNTRL, |
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| 22 | REG_RGMII_1_CNTRL, |
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| 23 | REG_RGMII_2_CNTRL, |
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| 24 | REG_RGMII_11_CNTRL, |
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| 25 | REG_LED_0_CNTRL, |
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| 26 | REG_LED_1_CNTRL, |
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| 27 | REG_LED_2_CNTRL, |
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| 28 | REG_LED_3_CNTRL, |
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| 29 | REG_LED_4_CNTRL, |
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| 30 | REG_LED_5_CNTRL, |
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| 31 | REG_LED_AGGREGATE_CTRL, |
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| 32 | REG_SWITCH_REG_MAX, |
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| 33 | }; |
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| 34 | |
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| 35 | /* Relative to REG_SWITCH_CNTRL */ |
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| 36 | #define MDIO_MASTER_SEL (1 << 0) |
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| 37 | |
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| 38 | /* Relative to REG_SWITCH_REVISION */ |
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| 39 | #define SF2_REV_MASK 0xffff |
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| 40 | #define SWITCH_TOP_REV_SHIFT 16 |
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| 41 | #define SWITCH_TOP_REV_MASK 0xffff |
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| 42 | |
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| 43 | /* Relative to REG_PHY_REVISION */ |
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| 44 | #define PHY_REVISION_MASK 0xffff |
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| 45 | |
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| 46 | /* Relative to REG_SPHY_CNTRL */ |
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| 47 | #define IDDQ_BIAS (1 << 0) |
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| 48 | #define EXT_PWR_DOWN (1 << 1) |
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| 49 | #define FORCE_DLL_EN (1 << 2) |
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| 50 | #define IDDQ_GLOBAL_PWR (1 << 3) |
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| 51 | #define CK25_DIS (1 << 4) |
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| 52 | #define PHY_RESET (1 << 5) |
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| 53 | #define PHY_PHYAD_SHIFT 8 |
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| 54 | #define PHY_PHYAD_MASK 0x1F |
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| 55 | |
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| 56 | /* Relative to REG_CROSSBAR */ |
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| 57 | #define CROSSBAR_BCM4908_INT_P7 0 |
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| 58 | #define CROSSBAR_BCM4908_INT_RUNNER 1 |
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| 59 | #define CROSSBAR_BCM4908_EXT_SERDES 0 |
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| 60 | #define CROSSBAR_BCM4908_EXT_GPHY4 1 |
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| 61 | #define CROSSBAR_BCM4908_EXT_RGMII 2 |
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| 62 | |
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| 63 | /* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */ |
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| 64 | #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0 |
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| 65 | #define LED_CNTRL_M10_ENCODE_SHIFT 2 |
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| 66 | #define LED_CNTRL_M100_ENCODE_SHIFT 4 |
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| 67 | #define LED_CNTRL_M1000_ENCODE_SHIFT 6 |
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| 68 | #define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8 |
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| 69 | #define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10 |
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| 70 | #define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12 |
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| 71 | #define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14 |
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| 72 | #define LED_CNTRL_RX_DV_EN (1 << 16) |
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| 73 | #define LED_CNTRL_TX_EN_EN (1 << 17) |
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| 74 | #define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18 |
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| 75 | #define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20 |
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| 76 | #define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22 |
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| 77 | #define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24) |
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| 78 | #define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25) |
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| 79 | #define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26) |
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| 80 | #define LED_CNTRL_ACT_LED_POL_SEL (1 << 27) |
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| 81 | #define LED_CNTRL_MASK 0x3 |
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| 82 | |
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| 83 | /* Register relative to REG_LED_*_CNTRL (BCM4908) */ |
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| 84 | #define REG_LED_CTRL 0x0 |
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| 85 | #define LED_CTRL_RX_ACT_EN 0x00000001 |
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| 86 | #define LED_CTRL_TX_ACT_EN 0x00000002 |
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| 87 | #define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004 |
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| 88 | #define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008 |
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| 89 | #define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010 |
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| 90 | #define LED_CTRL_ACT_LED_ACT_SEL 0x00000020 |
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| 91 | #define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040 |
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| 92 | #define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080 |
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| 93 | #define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100 |
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| 94 | #define LED_CTRL_ACT_LED_POL_SEL 0x00000200 |
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| 95 | #define LED_CTRL_LED_SPD_OVRD 0x00001c00 |
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| 96 | #define LED_CTRL_LNK_STATUS_OVRD 0x00002000 |
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| 97 | #define LED_CTRL_SPD_OVRD_EN 0x00004000 |
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| 98 | #define LED_CTRL_LNK_OVRD_EN 0x00008000 |
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| 99 | |
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| 100 | /* Register relative to REG_LED_*_CNTRL (BCM4908) */ |
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| 101 | #define REG_LED_LINK_SPEED_ENC_SEL 0x4 |
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| 102 | #define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0 |
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| 103 | #define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3 |
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| 104 | #define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6 |
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| 105 | #define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9 |
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| 106 | #define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12 |
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| 107 | #define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15 |
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| 108 | #define LED_LINK_SPEED_ENC_SEL_MASK 0x7 |
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| 109 | |
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| 110 | /* Register relative to REG_LED_*_CNTRL (BCM4908) */ |
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| 111 | #define REG_LED_LINK_SPEED_ENC 0x8 |
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| 112 | #define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0 |
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| 113 | #define LED_LINK_SPEED_ENC_M10_SHIFT 3 |
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| 114 | #define LED_LINK_SPEED_ENC_M100_SHIFT 6 |
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| 115 | #define LED_LINK_SPEED_ENC_M1000_SHIFT 9 |
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| 116 | #define LED_LINK_SPEED_ENC_M2500_SHIFT 12 |
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| 117 | #define LED_LINK_SPEED_ENC_M10G_SHIFT 15 |
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| 118 | #define LED_LINK_SPEED_ENC_MASK 0x7 |
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| 119 | |
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| 120 | /* Relative to REG_RGMII_CNTRL */ |
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| 121 | #define RGMII_MODE_EN (1 << 0) |
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| 122 | #define ID_MODE_DIS (1 << 1) |
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| 123 | #define PORT_MODE_SHIFT 2 |
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| 124 | #define INT_EPHY (0 << PORT_MODE_SHIFT) |
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| 125 | #define INT_GPHY (1 << PORT_MODE_SHIFT) |
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| 126 | #define EXT_EPHY (2 << PORT_MODE_SHIFT) |
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| 127 | #define EXT_GPHY (3 << PORT_MODE_SHIFT) |
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| 128 | #define EXT_REVMII (4 << PORT_MODE_SHIFT) |
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| 129 | #define PORT_MODE_MASK 0x7 |
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| 130 | #define RVMII_REF_SEL (1 << 5) |
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| 131 | #define RX_PAUSE_EN (1 << 6) |
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| 132 | #define TX_PAUSE_EN (1 << 7) |
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| 133 | #define TX_CLK_STOP_EN (1 << 8) |
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| 134 | #define LPI_COUNT_SHIFT 9 |
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| 135 | #define LPI_COUNT_MASK 0x3F |
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| 136 | |
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| 137 | /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ |
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| 138 | #define INTRL2_CPU_STATUS 0x00 |
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| 139 | #define INTRL2_CPU_SET 0x04 |
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| 140 | #define INTRL2_CPU_CLEAR 0x08 |
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| 141 | #define INTRL2_CPU_MASK_STATUS 0x0c |
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| 142 | #define INTRL2_CPU_MASK_SET 0x10 |
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| 143 | #define INTRL2_CPU_MASK_CLEAR 0x14 |
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| 144 | |
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| 145 | /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */ |
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| 146 | #define P_LINK_UP_IRQ(x) (1 << (0 + (x))) |
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| 147 | #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) |
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| 148 | #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) |
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| 149 | #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) |
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| 150 | #define P_GPHY_IRQ(x) (1 << (4 + (x))) |
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| 151 | #define P_NUM_IRQ 5 |
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| 152 | #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ |
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| 153 | P_LINK_DOWN_IRQ((x)) | \ |
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| 154 | P_ENERGY_ON_IRQ((x)) | \ |
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| 155 | P_ENERGY_OFF_IRQ((x)) | \ |
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| 156 | P_GPHY_IRQ((x))) |
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| 157 | |
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| 158 | /* INTRL2_0 interrupt sources */ |
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| 159 | #define P0_IRQ_OFF 0 |
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| 160 | #define MEM_DOUBLE_IRQ (1 << 5) |
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| 161 | #define EEE_LPI_IRQ (1 << 6) |
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| 162 | #define P5_CPU_WAKE_IRQ (1 << 7) |
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| 163 | #define P8_CPU_WAKE_IRQ (1 << 8) |
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| 164 | #define P7_CPU_WAKE_IRQ (1 << 9) |
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| 165 | #define IEEE1588_IRQ (1 << 10) |
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| 166 | #define MDIO_ERR_IRQ (1 << 11) |
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| 167 | #define MDIO_DONE_IRQ (1 << 12) |
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| 168 | #define GISB_ERR_IRQ (1 << 13) |
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| 169 | #define UBUS_ERR_IRQ (1 << 14) |
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| 170 | #define FAILOVER_ON_IRQ (1 << 15) |
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| 171 | #define FAILOVER_OFF_IRQ (1 << 16) |
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| 172 | #define TCAM_SOFT_ERR_IRQ (1 << 17) |
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| 173 | |
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| 174 | /* INTRL2_1 interrupt sources */ |
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| 175 | #define P7_IRQ_OFF 0 |
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| 176 | #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) |
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| 177 | |
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| 178 | /* Register set relative to 'ACB' */ |
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| 179 | #define ACB_CONTROL 0x00 |
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| 180 | #define ACB_EN (1 << 0) |
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| 181 | #define ACB_ALGORITHM (1 << 1) |
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| 182 | #define ACB_FLUSH_SHIFT 2 |
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| 183 | #define ACB_FLUSH_MASK 0x3 |
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| 184 | |
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| 185 | #define ACB_QUEUE_0_CFG 0x08 |
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| 186 | #define XOFF_THRESHOLD_MASK 0x7ff |
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| 187 | #define XON_EN (1 << 11) |
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| 188 | #define TOTAL_XOFF_THRESHOLD_SHIFT 12 |
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| 189 | #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff |
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| 190 | #define TOTAL_XOFF_EN (1 << 23) |
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| 191 | #define TOTAL_XON_EN (1 << 24) |
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| 192 | #define PKTLEN_SHIFT 25 |
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| 193 | #define PKTLEN_MASK 0x3f |
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| 194 | #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4)) |
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| 195 | |
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| 196 | /* Register set relative to 'CORE' */ |
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| 197 | #define CORE_G_PCTL_PORT0 0x00000 |
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| 198 | #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) |
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| 199 | #define CORE_IMP_CTL 0x00020 |
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| 200 | #define RX_DIS (1 << 0) |
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| 201 | #define TX_DIS (1 << 1) |
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| 202 | #define RX_BCST_EN (1 << 2) |
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| 203 | #define RX_MCST_EN (1 << 3) |
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| 204 | #define RX_UCST_EN (1 << 4) |
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| 205 | |
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| 206 | #define CORE_SWMODE 0x0002c |
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| 207 | #define SW_FWDG_MODE (1 << 0) |
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| 208 | #define SW_FWDG_EN (1 << 1) |
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| 209 | #define RTRY_LMT_DIS (1 << 2) |
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| 210 | |
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| 211 | #define CORE_STS_OVERRIDE_IMP 0x00038 |
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| 212 | #define GMII_SPEED_UP_2G (1 << 6) |
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| 213 | #define MII_SW_OR (1 << 7) |
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| 214 | |
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| 215 | /* Alternate layout for e.g: 7278 */ |
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| 216 | #define CORE_STS_OVERRIDE_IMP2 0x39040 |
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| 217 | |
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| 218 | #define CORE_NEW_CTRL 0x00084 |
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| 219 | #define IP_MC (1 << 0) |
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| 220 | #define OUTRANGEERR_DISCARD (1 << 1) |
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| 221 | #define INRANGEERR_DISCARD (1 << 2) |
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| 222 | #define CABLE_DIAG_LEN (1 << 3) |
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| 223 | #define OVERRIDE_AUTO_PD_WAR (1 << 4) |
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| 224 | #define EN_AUTO_PD_WAR (1 << 5) |
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| 225 | #define UC_FWD_EN (1 << 6) |
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| 226 | #define MC_FWD_EN (1 << 7) |
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| 227 | |
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| 228 | #define CORE_SWITCH_CTRL 0x00088 |
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| 229 | #define MII_DUMB_FWDG_EN (1 << 6) |
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| 230 | |
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| 231 | #define CORE_DIS_LEARN 0x000f0 |
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| 232 | |
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| 233 | #define CORE_SFT_LRN_CTRL 0x000f8 |
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| 234 | #define SW_LEARN_CNTL(x) (1 << (x)) |
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| 235 | |
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| 236 | #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) |
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| 237 | #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8) |
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| 238 | #define LINK_STS (1 << 0) |
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| 239 | #define DUPLX_MODE (1 << 1) |
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| 240 | #define SPEED_SHIFT 2 |
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| 241 | #define SPEED_MASK 0x3 |
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| 242 | #define RXFLOW_CNTL (1 << 4) |
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| 243 | #define TXFLOW_CNTL (1 << 5) |
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| 244 | #define SW_OVERRIDE (1 << 6) |
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| 245 | |
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| 246 | #define CORE_WATCHDOG_CTRL 0x001e4 |
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| 247 | #define SOFTWARE_RESET (1 << 7) |
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| 248 | #define EN_CHIP_RST (1 << 6) |
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| 249 | #define EN_SW_RESET (1 << 4) |
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| 250 | |
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| 251 | #define CORE_FAST_AGE_CTRL 0x00220 |
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| 252 | #define EN_FAST_AGE_STATIC (1 << 0) |
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| 253 | #define EN_AGE_DYNAMIC (1 << 1) |
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| 254 | #define EN_AGE_PORT (1 << 2) |
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| 255 | #define EN_AGE_VLAN (1 << 3) |
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| 256 | #define EN_AGE_SPT (1 << 4) |
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| 257 | #define EN_AGE_MCAST (1 << 5) |
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| 258 | #define FAST_AGE_STR_DONE (1 << 7) |
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| 259 | |
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| 260 | #define CORE_FAST_AGE_PORT 0x00224 |
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| 261 | #define AGE_PORT_MASK 0xf |
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| 262 | |
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| 263 | #define CORE_FAST_AGE_VID 0x00228 |
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| 264 | #define AGE_VID_MASK 0x3fff |
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| 265 | |
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| 266 | #define CORE_LNKSTS 0x00400 |
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| 267 | #define LNK_STS_MASK 0x1ff |
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| 268 | |
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| 269 | #define CORE_SPDSTS 0x00410 |
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| 270 | #define SPDSTS_10 0 |
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| 271 | #define SPDSTS_100 1 |
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| 272 | #define SPDSTS_1000 2 |
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| 273 | #define SPDSTS_SHIFT 2 |
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| 274 | #define SPDSTS_MASK 0x3 |
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| 275 | |
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| 276 | #define CORE_DUPSTS 0x00420 |
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| 277 | #define CORE_DUPSTS_MASK 0x1ff |
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| 278 | |
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| 279 | #define CORE_PAUSESTS 0x00428 |
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| 280 | #define PAUSESTS_TX_PAUSE_SHIFT 9 |
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| 281 | |
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| 282 | #define CORE_GMNCFGCFG 0x0800 |
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| 283 | #define RST_MIB_CNT (1 << 0) |
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| 284 | #define RXBPDU_EN (1 << 1) |
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| 285 | |
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| 286 | #define CORE_IMP0_PRT_ID 0x0804 |
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| 287 | |
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| 288 | #define CORE_RST_MIB_CNT_EN 0x0950 |
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| 289 | |
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| 290 | #define CORE_ARLA_VTBL_RWCTRL 0x1600 |
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| 291 | #define ARLA_VTBL_CMD_WRITE 0 |
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| 292 | #define ARLA_VTBL_CMD_READ 1 |
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| 293 | #define ARLA_VTBL_CMD_CLEAR 2 |
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| 294 | #define ARLA_VTBL_STDN (1 << 7) |
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| 295 | |
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| 296 | #define CORE_ARLA_VTBL_ADDR 0x1604 |
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| 297 | #define VTBL_ADDR_INDEX_MASK 0xfff |
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| 298 | |
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| 299 | #define CORE_ARLA_VTBL_ENTRY 0x160c |
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| 300 | #define FWD_MAP_MASK 0x1ff |
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| 301 | #define UNTAG_MAP_MASK 0x1ff |
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| 302 | #define UNTAG_MAP_SHIFT 9 |
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| 303 | #define MSTP_INDEX_MASK 0x7 |
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| 304 | #define MSTP_INDEX_SHIFT 18 |
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| 305 | #define FWD_MODE (1 << 21) |
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| 306 | |
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| 307 | #define CORE_MEM_PSM_VDD_CTRL 0x2380 |
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| 308 | #define P_TXQ_PSM_VDD_SHIFT 2 |
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| 309 | #define P_TXQ_PSM_VDD_MASK 0x3 |
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| 310 | #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ |
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| 311 | ((x) * P_TXQ_PSM_VDD_SHIFT)) |
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| 312 | |
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| 313 | #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10)) |
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| 314 | #define PRT_TO_QID_MASK 0x3 |
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| 315 | #define PRT_TO_QID_SHIFT 3 |
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| 316 | |
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| 317 | #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) |
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| 318 | #define PORT_VLAN_CTRL_MASK 0x1ff |
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| 319 | |
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| 320 | #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80 |
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| 321 | #define TXQ_PAUSE_THD_MASK 0x7ff |
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| 322 | #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \ |
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| 323 | (x) * 0x8) |
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| 324 | |
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| 325 | #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) |
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| 326 | #define CFI_SHIFT 12 |
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| 327 | #define PRI_SHIFT 13 |
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| 328 | #define PRI_MASK 0x7 |
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| 329 | |
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| 330 | #define CORE_JOIN_ALL_VLAN_EN 0xd140 |
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| 331 | |
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| 332 | #define CORE_CFP_ACC 0x28000 |
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| 333 | #define OP_STR_DONE (1 << 0) |
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| 334 | #define OP_SEL_SHIFT 1 |
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| 335 | #define OP_SEL_READ (1 << OP_SEL_SHIFT) |
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| 336 | #define OP_SEL_WRITE (2 << OP_SEL_SHIFT) |
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| 337 | #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT) |
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| 338 | #define OP_SEL_MASK (7 << OP_SEL_SHIFT) |
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| 339 | #define CFP_RAM_CLEAR (1 << 4) |
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| 340 | #define RAM_SEL_SHIFT 10 |
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| 341 | #define TCAM_SEL (1 << RAM_SEL_SHIFT) |
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| 342 | #define ACT_POL_RAM (2 << RAM_SEL_SHIFT) |
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| 343 | #define RATE_METER_RAM (4 << RAM_SEL_SHIFT) |
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| 344 | #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT) |
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| 345 | #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT) |
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| 346 | #define RED_STAT_RAM (24 << RAM_SEL_SHIFT) |
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| 347 | #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT) |
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| 348 | #define TCAM_RESET (1 << 15) |
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| 349 | #define XCESS_ADDR_SHIFT 16 |
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| 350 | #define XCESS_ADDR_MASK 0xff |
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| 351 | #define SEARCH_STS (1 << 27) |
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| 352 | #define RD_STS_SHIFT 28 |
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| 353 | #define RD_STS_TCAM (1 << RD_STS_SHIFT) |
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| 354 | #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT) |
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| 355 | #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT) |
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| 356 | #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT) |
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| 357 | |
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| 358 | #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010 |
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| 359 | |
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| 360 | #define CORE_CFP_DATA_PORT_0 0x28040 |
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| 361 | #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \ |
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| 362 | (x) * 0x10) |
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| 363 | |
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| 364 | /* UDF_DATA7 */ |
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| 365 | #define L3_FRAMING_SHIFT 24 |
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| 366 | #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT) |
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| 367 | #define IPTOS_SHIFT 16 |
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| 368 | #define IPTOS_MASK 0xff |
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| 369 | #define IPPROTO_SHIFT 8 |
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| 370 | #define IPPROTO_MASK (0xff << IPPROTO_SHIFT) |
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| 371 | #define IP_FRAG_SHIFT 7 |
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| 372 | #define IP_FRAG (1 << IP_FRAG_SHIFT) |
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| 373 | |
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| 374 | /* UDF_DATA0 */ |
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| 375 | #define SLICE_VALID 3 |
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| 376 | #define SLICE_NUM_SHIFT 2 |
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| 377 | #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT) |
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| 378 | #define SLICE_NUM_MASK 0x3 |
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| 379 | |
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| 380 | #define CORE_CFP_MASK_PORT_0 0x280c0 |
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| 381 | |
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| 382 | #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \ |
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| 383 | (x) * 0x10) |
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| 384 | |
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| 385 | #define CORE_ACT_POL_DATA0 0x28140 |
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| 386 | #define VLAN_BYP (1 << 0) |
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| 387 | #define EAP_BYP (1 << 1) |
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| 388 | #define STP_BYP (1 << 2) |
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| 389 | #define REASON_CODE_SHIFT 3 |
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| 390 | #define REASON_CODE_MASK 0x3f |
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| 391 | #define LOOP_BK_EN (1 << 9) |
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| 392 | #define NEW_TC_SHIFT 10 |
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| 393 | #define NEW_TC_MASK 0x7 |
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| 394 | #define CHANGE_TC (1 << 13) |
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| 395 | #define DST_MAP_IB_SHIFT 14 |
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| 396 | #define DST_MAP_IB_MASK 0x1ff |
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| 397 | #define CHANGE_FWRD_MAP_IB_SHIFT 24 |
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| 398 | #define CHANGE_FWRD_MAP_IB_MASK 0x3 |
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| 399 | #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT) |
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| 400 | #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT) |
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| 401 | #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT) |
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| 402 | #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT) |
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| 403 | #define NEW_DSCP_IB_SHIFT 26 |
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| 404 | #define NEW_DSCP_IB_MASK 0x3f |
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| 405 | |
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| 406 | #define CORE_ACT_POL_DATA1 0x28150 |
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| 407 | #define CHANGE_DSCP_IB (1 << 0) |
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| 408 | #define DST_MAP_OB_SHIFT 1 |
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| 409 | #define DST_MAP_OB_MASK 0x3ff |
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| 410 | #define CHANGE_FWRD_MAP_OB_SHIT 11 |
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| 411 | #define CHANGE_FWRD_MAP_OB_MASK 0x3 |
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| 412 | #define NEW_DSCP_OB_SHIFT 13 |
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| 413 | #define NEW_DSCP_OB_MASK 0x3f |
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| 414 | #define CHANGE_DSCP_OB (1 << 19) |
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| 415 | #define CHAIN_ID_SHIFT 20 |
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| 416 | #define CHAIN_ID_MASK 0xff |
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| 417 | #define CHANGE_COLOR (1 << 28) |
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| 418 | #define NEW_COLOR_SHIFT 29 |
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| 419 | #define NEW_COLOR_MASK 0x3 |
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| 420 | #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT) |
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| 421 | #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT) |
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| 422 | #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT) |
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| 423 | #define RED_DEFAULT (1 << 31) |
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| 424 | |
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| 425 | #define CORE_ACT_POL_DATA2 0x28160 |
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| 426 | #define MAC_LIMIT_BYPASS (1 << 0) |
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| 427 | #define CHANGE_TC_O (1 << 1) |
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| 428 | #define NEW_TC_O_SHIFT 2 |
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| 429 | #define NEW_TC_O_MASK 0x7 |
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| 430 | #define SPCP_RMK_DISABLE (1 << 5) |
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| 431 | #define CPCP_RMK_DISABLE (1 << 6) |
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| 432 | #define DEI_RMK_DISABLE (1 << 7) |
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| 433 | |
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| 434 | #define CORE_RATE_METER0 0x28180 |
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| 435 | #define COLOR_MODE (1 << 0) |
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| 436 | #define POLICER_ACTION (1 << 1) |
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| 437 | #define COUPLING_FLAG (1 << 2) |
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| 438 | #define POLICER_MODE_SHIFT 3 |
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| 439 | #define POLICER_MODE_MASK 0x3 |
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| 440 | #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT) |
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| 441 | #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT) |
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| 442 | #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT) |
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| 443 | #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT) |
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| 444 | |
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| 445 | #define CORE_RATE_METER1 0x28190 |
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| 446 | #define EIR_TK_BKT_MASK 0x7fffff |
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| 447 | |
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| 448 | #define CORE_RATE_METER2 0x281a0 |
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| 449 | #define EIR_BKT_SIZE_MASK 0xfffff |
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| 450 | |
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| 451 | #define CORE_RATE_METER3 0x281b0 |
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| 452 | #define EIR_REF_CNT_MASK 0x7ffff |
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| 453 | |
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| 454 | #define CORE_RATE_METER4 0x281c0 |
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| 455 | #define CIR_TK_BKT_MASK 0x7fffff |
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| 456 | |
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| 457 | #define CORE_RATE_METER5 0x281d0 |
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| 458 | #define CIR_BKT_SIZE_MASK 0xfffff |
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| 459 | |
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| 460 | #define CORE_RATE_METER6 0x281e0 |
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| 461 | #define CIR_REF_CNT_MASK 0x7ffff |
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| 462 | |
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| 463 | #define CORE_STAT_GREEN_CNTR 0x28200 |
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| 464 | #define CORE_STAT_YELLOW_CNTR 0x28210 |
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| 465 | #define CORE_STAT_RED_CNTR 0x28220 |
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| 466 | |
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| 467 | #define CORE_CFP_CTL_REG 0x28400 |
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| 468 | #define CFP_EN_MAP_MASK 0x1ff |
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| 469 | |
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| 470 | /* IPv4 slices, 3 of them */ |
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| 471 | #define CORE_UDF_0_A_0_8_PORT_0 0x28440 |
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| 472 | #define CFG_UDF_OFFSET_MASK 0x1f |
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| 473 | #define CFG_UDF_OFFSET_BASE_SHIFT 5 |
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| 474 | #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT) |
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| 475 | #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT) |
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| 476 | #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT) |
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| 477 | |
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| 478 | /* IPv6 slices */ |
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| 479 | #define CORE_UDF_0_B_0_8_PORT_0 0x28500 |
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| 480 | |
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| 481 | /* IPv6 chained slices */ |
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| 482 | #define CORE_UDF_0_D_0_11_PORT_0 0x28680 |
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| 483 | |
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| 484 | /* Number of slices for IPv4, IPv6 and non-IP */ |
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| 485 | #define UDF_NUM_SLICES 4 |
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| 486 | #define UDFS_PER_SLICE 9 |
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| 487 | |
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| 488 | /* Spacing between different slices */ |
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| 489 | #define UDF_SLICE_OFFSET 0x40 |
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| 490 | |
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| 491 | #define CFP_NUM_RULES 256 |
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| 492 | |
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| 493 | /* Number of egress queues per port */ |
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| 494 | #define SF2_NUM_EGRESS_QUEUES 8 |
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| 495 | |
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| 496 | #endif /* __BCM_SF2_REGS_H */ |
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| 497 | |
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