1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* Applied Micro X-Gene SoC Ethernet Driver |
3 | * |
4 | * Copyright (c) 2014, Applied Micro Circuits Corporation |
5 | * Authors: Iyappan Subramanian <isubramanian@apm.com> |
6 | * Ravi Patel <rapatel@apm.com> |
7 | * Keyur Chudgar <kchudgar@apm.com> |
8 | */ |
9 | |
10 | #ifndef __XGENE_ENET_MAIN_H__ |
11 | #define __XGENE_ENET_MAIN_H__ |
12 | |
13 | #include <linux/acpi.h> |
14 | #include <linux/clk.h> |
15 | #include <linux/efi.h> |
16 | #include <linux/irq.h> |
17 | #include <linux/io.h> |
18 | #include <linux/of.h> |
19 | #include <linux/of_net.h> |
20 | #include <linux/of_mdio.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/mdio/mdio-xgene.h> |
23 | #include <linux/module.h> |
24 | #include <net/ip.h> |
25 | #include <linux/prefetch.h> |
26 | #include <linux/if_vlan.h> |
27 | #include <linux/phy.h> |
28 | #include "xgene_enet_hw.h" |
29 | #include "xgene_enet_cle.h" |
30 | #include "xgene_enet_ring2.h" |
31 | |
32 | #define ETHER_MIN_PACKET 64 |
33 | #define ETHER_STD_PACKET 1518 |
34 | #define XGENE_ENET_STD_MTU 1536 |
35 | #define XGENE_ENET_MAX_MTU 9600 |
36 | #define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN) |
37 | |
38 | #define BUFLEN_16K (16 * 1024) |
39 | #define NUM_PKT_BUF 1024 |
40 | #define NUM_BUFPOOL 32 |
41 | #define NUM_NXTBUFPOOL 8 |
42 | #define MAX_EXP_BUFFS 256 |
43 | #define NUM_MSS_REG 4 |
44 | #define XGENE_MIN_ENET_FRAME_SIZE 60 |
45 | |
46 | #define XGENE_MAX_ENET_IRQ 16 |
47 | #define XGENE_NUM_RX_RING 8 |
48 | #define XGENE_NUM_TX_RING 8 |
49 | #define XGENE_NUM_TXC_RING 8 |
50 | |
51 | #define START_CPU_BUFNUM_0 0 |
52 | #define START_ETH_BUFNUM_0 2 |
53 | #define START_BP_BUFNUM_0 0x22 |
54 | #define START_RING_NUM_0 8 |
55 | #define START_CPU_BUFNUM_1 12 |
56 | #define START_ETH_BUFNUM_1 10 |
57 | #define START_BP_BUFNUM_1 0x2A |
58 | #define START_RING_NUM_1 264 |
59 | |
60 | #define XG_START_CPU_BUFNUM_1 12 |
61 | #define XG_START_ETH_BUFNUM_1 2 |
62 | #define XG_START_BP_BUFNUM_1 0x22 |
63 | #define XG_START_RING_NUM_1 264 |
64 | |
65 | #define X2_START_CPU_BUFNUM_0 0 |
66 | #define X2_START_ETH_BUFNUM_0 0 |
67 | #define X2_START_BP_BUFNUM_0 0x20 |
68 | #define X2_START_RING_NUM_0 0 |
69 | #define X2_START_CPU_BUFNUM_1 0xc |
70 | #define X2_START_ETH_BUFNUM_1 0 |
71 | #define X2_START_BP_BUFNUM_1 0x20 |
72 | #define X2_START_RING_NUM_1 256 |
73 | |
74 | #define IRQ_ID_SIZE 16 |
75 | |
76 | #define PHY_POLL_LINK_ON (10 * HZ) |
77 | #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5) |
78 | |
79 | enum xgene_enet_id { |
80 | XGENE_ENET1 = 1, |
81 | XGENE_ENET2 |
82 | }; |
83 | |
84 | enum xgene_enet_buf_len { |
85 | SIZE_2K = 2048, |
86 | SIZE_4K = 4096, |
87 | SIZE_16K = 16384 |
88 | }; |
89 | |
90 | /* software context of a descriptor ring */ |
91 | struct xgene_enet_desc_ring { |
92 | struct net_device *ndev; |
93 | u16 id; |
94 | u16 num; |
95 | u16 head; |
96 | u16 tail; |
97 | u16 exp_buf_tail; |
98 | u16 slots; |
99 | u16 irq; |
100 | char irq_name[IRQ_ID_SIZE]; |
101 | u32 size; |
102 | u32 state[X2_NUM_RING_CONFIG]; |
103 | void __iomem *cmd_base; |
104 | void __iomem *cmd; |
105 | dma_addr_t dma; |
106 | dma_addr_t irq_mbox_dma; |
107 | void *irq_mbox_addr; |
108 | u16 dst_ring_num; |
109 | u16 nbufpool; |
110 | int npagepool; |
111 | u8 index; |
112 | u32 flags; |
113 | struct sk_buff *(*rx_skb); |
114 | struct sk_buff *(*cp_skb); |
115 | dma_addr_t *frag_dma_addr; |
116 | struct page *(*frag_page); |
117 | enum xgene_enet_ring_cfgsize cfgsize; |
118 | struct xgene_enet_desc_ring *cp_ring; |
119 | struct xgene_enet_desc_ring *buf_pool; |
120 | struct xgene_enet_desc_ring *page_pool; |
121 | struct napi_struct napi; |
122 | union { |
123 | void *desc_addr; |
124 | struct xgene_enet_raw_desc *raw_desc; |
125 | struct xgene_enet_raw_desc16 *raw_desc16; |
126 | }; |
127 | __le64 *exp_bufs; |
128 | u64 tx_packets; |
129 | u64 tx_bytes; |
130 | u64 tx_dropped; |
131 | u64 tx_errors; |
132 | u64 rx_packets; |
133 | u64 rx_bytes; |
134 | u64 rx_dropped; |
135 | u64 rx_errors; |
136 | u64 rx_length_errors; |
137 | u64 rx_crc_errors; |
138 | u64 rx_frame_errors; |
139 | u64 rx_fifo_errors; |
140 | }; |
141 | |
142 | struct xgene_mac_ops { |
143 | void (*init)(struct xgene_enet_pdata *pdata); |
144 | void (*reset)(struct xgene_enet_pdata *pdata); |
145 | void (*tx_enable)(struct xgene_enet_pdata *pdata); |
146 | void (*rx_enable)(struct xgene_enet_pdata *pdata); |
147 | void (*tx_disable)(struct xgene_enet_pdata *pdata); |
148 | void (*rx_disable)(struct xgene_enet_pdata *pdata); |
149 | void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx); |
150 | void (*set_speed)(struct xgene_enet_pdata *pdata); |
151 | void (*set_mac_addr)(struct xgene_enet_pdata *pdata); |
152 | void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize); |
153 | void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index); |
154 | void (*link_state)(struct work_struct *work); |
155 | void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable); |
156 | void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable); |
157 | void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable); |
158 | }; |
159 | |
160 | struct xgene_port_ops { |
161 | int (*reset)(struct xgene_enet_pdata *pdata); |
162 | void (*clear)(struct xgene_enet_pdata *pdata, |
163 | struct xgene_enet_desc_ring *ring); |
164 | void (*cle_bypass)(struct xgene_enet_pdata *pdata, |
165 | u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id); |
166 | void (*shutdown)(struct xgene_enet_pdata *pdata); |
167 | }; |
168 | |
169 | struct xgene_ring_ops { |
170 | u8 num_ring_config; |
171 | u8 num_ring_id_shift; |
172 | struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *); |
173 | void (*clear)(struct xgene_enet_desc_ring *); |
174 | void (*wr_cmd)(struct xgene_enet_desc_ring *, int); |
175 | u32 (*len)(struct xgene_enet_desc_ring *); |
176 | void (*coalesce)(struct xgene_enet_desc_ring *); |
177 | }; |
178 | |
179 | struct xgene_cle_ops { |
180 | int (*cle_init)(struct xgene_enet_pdata *pdata); |
181 | }; |
182 | |
183 | /* ethernet private data */ |
184 | struct xgene_enet_pdata { |
185 | struct net_device *ndev; |
186 | struct mii_bus *mdio_bus; |
187 | int phy_speed; |
188 | struct clk *clk; |
189 | struct platform_device *pdev; |
190 | enum xgene_enet_id enet_id; |
191 | struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING]; |
192 | struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING]; |
193 | u16 tx_level[XGENE_NUM_TX_RING]; |
194 | u16 txc_level[XGENE_NUM_TX_RING]; |
195 | char *dev_name; |
196 | u32 rx_buff_cnt; |
197 | u32 tx_qcnt_hi; |
198 | u32 irqs[XGENE_MAX_ENET_IRQ]; |
199 | u8 rxq_cnt; |
200 | u8 txq_cnt; |
201 | u8 cq_cnt; |
202 | void __iomem *eth_csr_addr; |
203 | void __iomem *eth_ring_if_addr; |
204 | void __iomem *eth_diag_csr_addr; |
205 | void __iomem *mcx_mac_addr; |
206 | void __iomem *mcx_mac_csr_addr; |
207 | void __iomem *mcx_stats_addr; |
208 | void __iomem *base_addr; |
209 | void __iomem *pcs_addr; |
210 | void __iomem *ring_csr_addr; |
211 | void __iomem *ring_cmd_addr; |
212 | int phy_mode; |
213 | enum xgene_enet_rm rm; |
214 | struct xgene_enet_cle cle; |
215 | u64 *extd_stats; |
216 | u64 false_rflr; |
217 | u64 vlan_rjbr; |
218 | spinlock_t stats_lock; /* statistics lock */ |
219 | const struct xgene_mac_ops *mac_ops; |
220 | spinlock_t mac_lock; /* mac lock */ |
221 | const struct xgene_port_ops *port_ops; |
222 | struct xgene_ring_ops *ring_ops; |
223 | const struct xgene_cle_ops *cle_ops; |
224 | struct delayed_work link_work; |
225 | u32 port_id; |
226 | u8 cpu_bufnum; |
227 | u8 eth_bufnum; |
228 | u8 bp_bufnum; |
229 | u16 ring_num; |
230 | u32 mss[NUM_MSS_REG]; |
231 | u32 mss_refcnt[NUM_MSS_REG]; |
232 | spinlock_t mss_lock; /* mss lock */ |
233 | u8 tx_delay; |
234 | u8 rx_delay; |
235 | bool mdio_driver; |
236 | struct gpio_desc *sfp_rdy; |
237 | bool sfp_gpio_en; |
238 | u32 pause_autoneg; |
239 | bool tx_pause; |
240 | bool rx_pause; |
241 | }; |
242 | |
243 | struct xgene_indirect_ctl { |
244 | void __iomem *addr; |
245 | void __iomem *ctl; |
246 | void __iomem *cmd; |
247 | void __iomem *cmd_done; |
248 | }; |
249 | |
250 | static inline struct device *ndev_to_dev(struct net_device *ndev) |
251 | { |
252 | return ndev->dev.parent; |
253 | } |
254 | |
255 | static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) |
256 | { |
257 | struct xgene_enet_pdata *pdata = netdev_priv(dev: ring->ndev); |
258 | |
259 | return ((u16)pdata->rm << 10) | ring->num; |
260 | } |
261 | |
262 | void xgene_enet_set_ethtool_ops(struct net_device *netdev); |
263 | int xgene_extd_stats_init(struct xgene_enet_pdata *pdata); |
264 | |
265 | #endif /* __XGENE_ENET_MAIN_H__ */ |
266 | |