1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Atlantic Network Driver
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6#ifndef HW_ATL2_INTERNAL_H
7#define HW_ATL2_INTERNAL_H
8
9#include "hw_atl2_utils.h"
10
11#define HW_ATL2_MTU_JUMBO 16352U
12#define HW_ATL2_MTU 1514U
13
14#define HW_ATL2_TX_RINGS 4U
15#define HW_ATL2_RX_RINGS 4U
16
17#define HW_ATL2_RINGS_MAX 32U
18#define HW_ATL2_TXD_SIZE (16U)
19#define HW_ATL2_RXD_SIZE (16U)
20
21#define HW_ATL2_MAC_UC 0U
22#define HW_ATL2_MAC_MIN 1U
23#define HW_ATL2_MAC_MAX 38U
24
25/* interrupts */
26#define HW_ATL2_ERR_INT 8U
27#define HW_ATL2_INT_MASK (0xFFFFFFFFU)
28
29#define HW_ATL2_TXBUF_MAX 128U
30#define HW_ATL2_RXBUF_MAX 192U
31
32#define HW_ATL2_RSS_REDIRECTION_MAX 64U
33
34#define HW_ATL2_TC_MAX 8U
35#define HW_ATL2_RSS_MAX 8U
36
37#define HW_ATL2_INTR_MODER_MAX 0x1FF
38#define HW_ATL2_INTR_MODER_MIN 0xFF
39
40#define HW_ATL2_MIN_RXD \
41 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
42#define HW_ATL2_MIN_TXD \
43 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
44
45#define HW_ATL2_MAX_RXD 8184U
46#define HW_ATL2_MAX_TXD 8184U
47
48#define HW_ATL2_FW_SM_ACT_RSLVR 0x3U
49
50#define HW_ATL2_RPF_TAG_UC_OFFSET 0x0
51#define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6
52#define HW_ATL2_RPF_TAG_ET_OFFSET 0x7
53#define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA
54#define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE
55#define HW_ATL2_RPF_TAG_L3_V4_OFFSET 0xF
56#define HW_ATL2_RPF_TAG_L3_V6_OFFSET 0x12
57#define HW_ATL2_RPF_TAG_L4_OFFSET 0x15
58#define HW_ATL2_RPF_TAG_L4_FLEX_OFFSET 0x18
59#define HW_ATL2_RPF_TAG_FLEX_OFFSET 0x1B
60#define HW_ATL2_RPF_TAG_PCP_OFFSET 0x1D
61
62#define HW_ATL2_RPF_TAG_UC_MASK (0x0000003F << HW_ATL2_RPF_TAG_UC_OFFSET)
63#define HW_ATL2_RPF_TAG_ALLMC_MASK (0x00000001 << HW_ATL2_RPF_TAG_ALLMC_OFFSET)
64#define HW_ATL2_RPF_TAG_UNTAG_MASK (0x00000001 << HW_ATL2_RPF_TAG_UNTAG_OFFSET)
65#define HW_ATL2_RPF_TAG_VLAN_MASK (0x0000000F << HW_ATL2_RPF_TAG_VLAN_OFFSET)
66#define HW_ATL2_RPF_TAG_ET_MASK (0x00000007 << HW_ATL2_RPF_TAG_ET_OFFSET)
67#define HW_ATL2_RPF_TAG_L3_V4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V4_OFFSET)
68#define HW_ATL2_RPF_TAG_L3_V6_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V6_OFFSET)
69#define HW_ATL2_RPF_TAG_L4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L4_OFFSET)
70#define HW_ATL2_RPF_TAG_PCP_MASK (0x00000007 << HW_ATL2_RPF_TAG_PCP_OFFSET)
71
72#define HW_ATL2_RPF_TAG_BASE_UC BIT(HW_ATL2_RPF_TAG_UC_OFFSET)
73#define HW_ATL2_RPF_TAG_BASE_ALLMC BIT(HW_ATL2_RPF_TAG_ALLMC_OFFSET)
74#define HW_ATL2_RPF_TAG_BASE_UNTAG BIT(HW_ATL2_RPF_TAG_UNTAG_OFFSET)
75#define HW_ATL2_RPF_TAG_BASE_VLAN BIT(HW_ATL2_RPF_TAG_VLAN_OFFSET)
76
77enum HW_ATL2_RPF_ART_INDEX {
78 HW_ATL2_RPF_L2_PROMISC_OFF_INDEX,
79 HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX,
80 HW_ATL2_RPF_L3L4_USER_INDEX = 8,
81 HW_ATL2_RPF_ET_PCP_USER_INDEX = HW_ATL2_RPF_L3L4_USER_INDEX + 16,
82 HW_ATL2_RPF_VLAN_USER_INDEX = HW_ATL2_RPF_ET_PCP_USER_INDEX + 16,
83 HW_ATL2_RPF_PCP_TO_TC_INDEX = HW_ATL2_RPF_VLAN_USER_INDEX +
84 HW_ATL_VLAN_MAX_FILTERS,
85};
86
87#define HW_ATL2_ACTION(ACTION, RSS, INDEX, VALID) \
88 ((((ACTION) & 0x3U) << 8) | \
89 (((RSS) & 0x1U) << 7) | \
90 (((INDEX) & 0x3FU) << 2) | \
91 (((VALID) & 0x1U) << 0))
92
93#define HW_ATL2_ACTION_DROP HW_ATL2_ACTION(0, 0, 0, 1)
94#define HW_ATL2_ACTION_DISABLE HW_ATL2_ACTION(0, 0, 0, 0)
95#define HW_ATL2_ACTION_ASSIGN_QUEUE(QUEUE) HW_ATL2_ACTION(1, 0, (QUEUE), 1)
96#define HW_ATL2_ACTION_ASSIGN_TC(TC) HW_ATL2_ACTION(1, 1, (TC), 1)
97
98enum HW_ATL2_RPF_RSS_HASH_TYPE {
99 HW_ATL2_RPF_RSS_HASH_TYPE_NONE = 0,
100 HW_ATL2_RPF_RSS_HASH_TYPE_IPV4 = BIT(0),
101 HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_TCP = BIT(1),
102 HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_UDP = BIT(2),
103 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6 = BIT(3),
104 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_TCP = BIT(4),
105 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_UDP = BIT(5),
106 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX = BIT(6),
107 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_TCP = BIT(7),
108 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_UDP = BIT(8),
109 HW_ATL2_RPF_RSS_HASH_TYPE_ALL = HW_ATL2_RPF_RSS_HASH_TYPE_IPV4 |
110 HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_TCP |
111 HW_ATL2_RPF_RSS_HASH_TYPE_IPV4_UDP |
112 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6 |
113 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_TCP |
114 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_UDP |
115 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX |
116 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_TCP |
117 HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_UDP,
118};
119
120#define HW_ATL_MCAST_FLT_ANY_TO_HOST 0x00010FFFU
121
122struct hw_atl2_priv {
123 struct statistics_s last_stats;
124 unsigned int art_base_index;
125};
126
127#endif /* HW_ATL2_INTERNAL_H */
128

source code of linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h