1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Atlantic Network Driver |
3 | * Copyright (C) 2020 Marvell International Ltd. |
4 | */ |
5 | |
6 | #include "aq_hw.h" |
7 | #include "aq_hw_utils.h" |
8 | #include "aq_ring.h" |
9 | #include "aq_nic.h" |
10 | #include "hw_atl/hw_atl_b0.h" |
11 | #include "hw_atl/hw_atl_utils.h" |
12 | #include "hw_atl/hw_atl_llh.h" |
13 | #include "hw_atl/hw_atl_llh_internal.h" |
14 | #include "hw_atl2_utils.h" |
15 | #include "hw_atl2_llh.h" |
16 | #include "hw_atl2_internal.h" |
17 | #include "hw_atl2_llh_internal.h" |
18 | |
19 | static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, |
20 | u32 tag, u32 mask, u32 action); |
21 | |
22 | #define DEFAULT_BOARD_BASIC_CAPABILITIES \ |
23 | .is_64_dma = true, \ |
24 | .op64bit = true, \ |
25 | .msix_irqs = 8U, \ |
26 | .irq_mask = ~0U, \ |
27 | .vecs = HW_ATL2_RSS_MAX, \ |
28 | .tcs_max = HW_ATL2_TC_MAX, \ |
29 | .rxd_alignment = 1U, \ |
30 | .rxd_size = HW_ATL2_RXD_SIZE, \ |
31 | .rxds_max = HW_ATL2_MAX_RXD, \ |
32 | .rxds_min = HW_ATL2_MIN_RXD, \ |
33 | .txd_alignment = 1U, \ |
34 | .txd_size = HW_ATL2_TXD_SIZE, \ |
35 | .txds_max = HW_ATL2_MAX_TXD, \ |
36 | .txds_min = HW_ATL2_MIN_TXD, \ |
37 | .txhwb_alignment = 4096U, \ |
38 | .tx_rings = HW_ATL2_TX_RINGS, \ |
39 | .rx_rings = HW_ATL2_RX_RINGS, \ |
40 | .hw_features = NETIF_F_HW_CSUM | \ |
41 | NETIF_F_RXCSUM | \ |
42 | NETIF_F_RXHASH | \ |
43 | NETIF_F_SG | \ |
44 | NETIF_F_TSO | \ |
45 | NETIF_F_TSO6 | \ |
46 | NETIF_F_LRO | \ |
47 | NETIF_F_NTUPLE | \ |
48 | NETIF_F_HW_VLAN_CTAG_FILTER | \ |
49 | NETIF_F_HW_VLAN_CTAG_RX | \ |
50 | NETIF_F_HW_VLAN_CTAG_TX | \ |
51 | NETIF_F_GSO_UDP_L4 | \ |
52 | NETIF_F_GSO_PARTIAL | \ |
53 | NETIF_F_HW_TC, \ |
54 | .hw_priv_flags = IFF_UNICAST_FLT, \ |
55 | .flow_control = true, \ |
56 | .mtu = HW_ATL2_MTU_JUMBO, \ |
57 | .mac_regs_count = 72, \ |
58 | .hw_alive_check_addr = 0x10U, \ |
59 | .priv_data_len = sizeof(struct hw_atl2_priv) |
60 | |
61 | const struct aq_hw_caps_s hw_atl2_caps_aqc113 = { |
62 | DEFAULT_BOARD_BASIC_CAPABILITIES, |
63 | .media_type = AQ_HW_MEDIA_TYPE_TP, |
64 | .link_speed_msk = AQ_NIC_RATE_10G | |
65 | AQ_NIC_RATE_5G | |
66 | AQ_NIC_RATE_2G5 | |
67 | AQ_NIC_RATE_1G | |
68 | AQ_NIC_RATE_100M | |
69 | AQ_NIC_RATE_10M, |
70 | }; |
71 | |
72 | const struct aq_hw_caps_s hw_atl2_caps_aqc115c = { |
73 | DEFAULT_BOARD_BASIC_CAPABILITIES, |
74 | .media_type = AQ_HW_MEDIA_TYPE_TP, |
75 | .link_speed_msk = AQ_NIC_RATE_2G5 | |
76 | AQ_NIC_RATE_1G | |
77 | AQ_NIC_RATE_100M | |
78 | AQ_NIC_RATE_10M, |
79 | }; |
80 | |
81 | const struct aq_hw_caps_s hw_atl2_caps_aqc116c = { |
82 | DEFAULT_BOARD_BASIC_CAPABILITIES, |
83 | .media_type = AQ_HW_MEDIA_TYPE_TP, |
84 | .link_speed_msk = AQ_NIC_RATE_1G | |
85 | AQ_NIC_RATE_100M | |
86 | AQ_NIC_RATE_10M, |
87 | }; |
88 | |
89 | static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self) |
90 | { |
91 | return hw_atl_reg_glb_cpu_sem_get(aq_hw: self, HW_ATL2_FW_SM_ACT_RSLVR); |
92 | } |
93 | |
94 | static int hw_atl2_hw_reset(struct aq_hw_s *self) |
95 | { |
96 | struct hw_atl2_priv *priv = self->priv; |
97 | int err; |
98 | |
99 | err = hw_atl2_utils_soft_reset(self); |
100 | if (err) |
101 | return err; |
102 | |
103 | memset(priv, 0, sizeof(*priv)); |
104 | |
105 | self->aq_fw_ops->set_state(self, MPI_RESET); |
106 | |
107 | err = aq_hw_err_from_flags(hw: self); |
108 | |
109 | return err; |
110 | } |
111 | |
112 | static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self) |
113 | { |
114 | struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; |
115 | unsigned int tcs, q_per_tc; |
116 | unsigned int tc, q; |
117 | u32 rx_map = 0; |
118 | u32 tx_map = 0; |
119 | |
120 | hw_atl2_tpb_tx_tc_q_rand_map_en_set(aq_hw: self, tc_q_rand_map_en: 1U); |
121 | |
122 | switch (cfg->tc_mode) { |
123 | case AQ_TC_MODE_8TCS: |
124 | tcs = 8; |
125 | q_per_tc = 4; |
126 | break; |
127 | case AQ_TC_MODE_4TCS: |
128 | tcs = 4; |
129 | q_per_tc = 8; |
130 | break; |
131 | default: |
132 | return -EINVAL; |
133 | } |
134 | |
135 | for (tc = 0; tc != tcs; tc++) { |
136 | unsigned int tc_q_offset = tc * q_per_tc; |
137 | |
138 | for (q = tc_q_offset; q != tc_q_offset + q_per_tc; q++) { |
139 | rx_map |= tc << HW_ATL2_RX_Q_TC_MAP_SHIFT(q); |
140 | if (HW_ATL2_RX_Q_TC_MAP_ADR(q) != |
141 | HW_ATL2_RX_Q_TC_MAP_ADR(q + 1)) { |
142 | aq_hw_write_reg(hw: self, |
143 | HW_ATL2_RX_Q_TC_MAP_ADR(q), |
144 | value: rx_map); |
145 | rx_map = 0; |
146 | } |
147 | |
148 | tx_map |= tc << HW_ATL2_TX_Q_TC_MAP_SHIFT(q); |
149 | if (HW_ATL2_TX_Q_TC_MAP_ADR(q) != |
150 | HW_ATL2_TX_Q_TC_MAP_ADR(q + 1)) { |
151 | aq_hw_write_reg(hw: self, |
152 | HW_ATL2_TX_Q_TC_MAP_ADR(q), |
153 | value: tx_map); |
154 | tx_map = 0; |
155 | } |
156 | } |
157 | } |
158 | |
159 | return aq_hw_err_from_flags(hw: self); |
160 | } |
161 | |
162 | static int hw_atl2_hw_qos_set(struct aq_hw_s *self) |
163 | { |
164 | struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; |
165 | u32 tx_buff_size = HW_ATL2_TXBUF_MAX; |
166 | u32 rx_buff_size = HW_ATL2_RXBUF_MAX; |
167 | unsigned int prio = 0U; |
168 | u32 tc = 0U; |
169 | |
170 | /* TPS Descriptor rate init */ |
171 | hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(aq_hw: self, curr_time_res: 0x0U); |
172 | hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(aq_hw: self, tx_pkt_shed_desc_rate_lim: 0xA); |
173 | |
174 | /* TPS VM init */ |
175 | hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(aq_hw: self, arb_mode: 0U); |
176 | |
177 | tx_buff_size /= cfg->tcs; |
178 | rx_buff_size /= cfg->tcs; |
179 | for (tc = 0; tc < cfg->tcs; tc++) { |
180 | u32 threshold = 0U; |
181 | |
182 | /* Tx buf size TC0 */ |
183 | hw_atl_tpb_tx_pkt_buff_size_per_tc_set(aq_hw: self, tx_pkt_buff_size_per_tc: tx_buff_size, buffer: tc); |
184 | |
185 | threshold = (tx_buff_size * (1024 / 32U) * 66U) / 100U; |
186 | hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(aq_hw: self, tx_buff_hi_threshold_per_tc: threshold, buffer: tc); |
187 | |
188 | threshold = (tx_buff_size * (1024 / 32U) * 50U) / 100U; |
189 | hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(aq_hw: self, tx_buff_lo_threshold_per_tc: threshold, buffer: tc); |
190 | |
191 | /* QoS Rx buf size per TC */ |
192 | hw_atl_rpb_rx_pkt_buff_size_per_tc_set(aq_hw: self, rx_pkt_buff_size_per_tc: rx_buff_size, buffer: tc); |
193 | |
194 | threshold = (rx_buff_size * (1024U / 32U) * 66U) / 100U; |
195 | hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(aq_hw: self, rx_buff_hi_threshold_per_tc: threshold, buffer: tc); |
196 | |
197 | threshold = (rx_buff_size * (1024U / 32U) * 50U) / 100U; |
198 | hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(aq_hw: self, rx_buff_lo_threshold_per_tc: threshold, buffer: tc); |
199 | |
200 | hw_atl_b0_set_fc(self, fc: self->aq_nic_cfg->fc.req, tc); |
201 | } |
202 | |
203 | /* QoS 802.1p priority -> TC mapping */ |
204 | for (prio = 0; prio < 8; ++prio) |
205 | hw_atl_rpf_rpb_user_priority_tc_map_set(aq_hw: self, user_priority_tc_map: prio, |
206 | tc: cfg->prio_tc_map[prio]); |
207 | |
208 | /* ATL2 Apply ring to TC mapping */ |
209 | hw_atl2_hw_queue_to_tc_map_set(self); |
210 | |
211 | return aq_hw_err_from_flags(hw: self); |
212 | } |
213 | |
214 | static int (struct aq_hw_s *self, |
215 | struct aq_rss_parameters *) |
216 | { |
217 | u8 *indirection_table = rss_params->indirection_table; |
218 | const u32 num_tcs = aq_hw_num_tcs(hw: self); |
219 | u32 rpf_redir2_enable; |
220 | int tc; |
221 | int i; |
222 | |
223 | rpf_redir2_enable = num_tcs > 4 ? 1 : 0; |
224 | |
225 | hw_atl2_rpf_redirection_table2_select_set(aq_hw: self, select: rpf_redir2_enable); |
226 | |
227 | for (i = HW_ATL2_RSS_REDIRECTION_MAX; i--;) { |
228 | for (tc = 0; tc != num_tcs; tc++) { |
229 | hw_atl2_new_rpf_rss_redir_set(aq_hw: self, tc, index: i, |
230 | queue: tc * |
231 | aq_hw_q_per_tc(hw: self) + |
232 | indirection_table[i]); |
233 | } |
234 | } |
235 | |
236 | return aq_hw_err_from_flags(hw: self); |
237 | } |
238 | |
239 | static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self) |
240 | { |
241 | static const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1; |
242 | /* Scale factor is based on the number of bits in fractional portion */ |
243 | static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH); |
244 | static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >> |
245 | HW_ATL_TPS_DESC_RATE_Y_SHIFT; |
246 | const u32 link_speed = self->aq_link_status.mbps; |
247 | struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; |
248 | unsigned long num_min_rated_tcs = 0; |
249 | u32 tc_weight[AQ_CFG_TCS_MAX]; |
250 | u32 fixed_max_credit_4b; |
251 | u32 fixed_max_credit; |
252 | u8 min_rate_msk = 0; |
253 | u32 sum_weight = 0; |
254 | int tc; |
255 | |
256 | /* By default max_credit is based upon MTU (in unit of 64b) */ |
257 | fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64; |
258 | /* in unit of 4b */ |
259 | fixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4; |
260 | |
261 | if (link_speed) { |
262 | min_rate_msk = nic_cfg->tc_min_rate_msk & |
263 | (BIT(nic_cfg->tcs) - 1); |
264 | num_min_rated_tcs = hweight8(min_rate_msk); |
265 | } |
266 | |
267 | /* First, calculate weights where min_rate is specified */ |
268 | if (num_min_rated_tcs) { |
269 | for (tc = 0; tc != nic_cfg->tcs; tc++) { |
270 | if (!nic_cfg->tc_min_rate[tc]) { |
271 | tc_weight[tc] = 0; |
272 | continue; |
273 | } |
274 | |
275 | tc_weight[tc] = (-1L + link_speed + |
276 | nic_cfg->tc_min_rate[tc] * |
277 | max_weight) / |
278 | link_speed; |
279 | tc_weight[tc] = min(tc_weight[tc], max_weight); |
280 | sum_weight += tc_weight[tc]; |
281 | } |
282 | } |
283 | |
284 | /* WSP, if min_rate is set for at least one TC. |
285 | * RR otherwise. |
286 | */ |
287 | hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(aq_hw: self, data_arb_mode: min_rate_msk ? 1U : 0U); |
288 | /* Data TC Arbiter takes precedence over Descriptor TC Arbiter, |
289 | * leave Descriptor TC Arbiter as RR. |
290 | */ |
291 | hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(aq_hw: self, arb_mode: 0U); |
292 | |
293 | hw_atl_tps_tx_desc_rate_mode_set(aq_hw: self, rate_mode: nic_cfg->is_qos ? 1U : 0U); |
294 | |
295 | for (tc = 0; tc != nic_cfg->tcs; tc++) { |
296 | const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; |
297 | const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); |
298 | u32 weight, max_credit; |
299 | |
300 | hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(aq_hw: self, tc, |
301 | max_credit: fixed_max_credit); |
302 | hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(aq_hw: self, tc, weight: 0x1E); |
303 | |
304 | if (num_min_rated_tcs) { |
305 | weight = tc_weight[tc]; |
306 | |
307 | if (!weight && sum_weight < max_weight) |
308 | weight = (max_weight - sum_weight) / |
309 | (nic_cfg->tcs - num_min_rated_tcs); |
310 | else if (!weight) |
311 | weight = 0x640; |
312 | |
313 | max_credit = max(2 * weight, fixed_max_credit_4b); |
314 | } else { |
315 | weight = 0x640; |
316 | max_credit = 0xFFF0; |
317 | } |
318 | |
319 | hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(aq_hw: self, tc, weight); |
320 | hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(aq_hw: self, tc, |
321 | max_credit); |
322 | |
323 | hw_atl_tps_tx_desc_rate_en_set(aq_hw: self, desc, enable: en); |
324 | |
325 | if (en) { |
326 | /* Nominal rate is always 10G */ |
327 | const u32 rate = 10000U * scale / |
328 | nic_cfg->tc_max_rate[tc]; |
329 | const u32 rate_int = rate >> |
330 | HW_ATL_TPS_DESC_RATE_Y_WIDTH; |
331 | const u32 rate_frac = rate & frac_msk; |
332 | |
333 | hw_atl_tps_tx_desc_rate_x_set(aq_hw: self, desc, rate_int); |
334 | hw_atl_tps_tx_desc_rate_y_set(aq_hw: self, desc, rate_frac); |
335 | } else { |
336 | /* A value of 1 indicates the queue is not |
337 | * rate controlled. |
338 | */ |
339 | hw_atl_tps_tx_desc_rate_x_set(aq_hw: self, desc, rate_int: 1U); |
340 | hw_atl_tps_tx_desc_rate_y_set(aq_hw: self, desc, rate_frac: 0U); |
341 | } |
342 | } |
343 | for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { |
344 | const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0); |
345 | |
346 | hw_atl_tps_tx_desc_rate_en_set(aq_hw: self, desc, enable: 0U); |
347 | hw_atl_tps_tx_desc_rate_x_set(aq_hw: self, desc, rate_int: 1U); |
348 | hw_atl_tps_tx_desc_rate_y_set(aq_hw: self, desc, rate_frac: 0U); |
349 | } |
350 | |
351 | return aq_hw_err_from_flags(hw: self); |
352 | } |
353 | |
354 | static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self) |
355 | { |
356 | struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg; |
357 | |
358 | /* Tx TC/RSS number config */ |
359 | hw_atl_tpb_tps_tx_tc_mode_set(aq_hw: self, tx_traf_class_mode: nic_cfg->tc_mode); |
360 | |
361 | hw_atl_thm_lso_tcp_flag_of_first_pkt_set(aq_hw: self, lso_tcp_flag_of_first_pkt: 0x0FF6U); |
362 | hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(aq_hw: self, lso_tcp_flag_of_middle_pkt: 0x0FF6U); |
363 | hw_atl_thm_lso_tcp_flag_of_last_pkt_set(aq_hw: self, lso_tcp_flag_of_last_pkt: 0x0F7FU); |
364 | |
365 | /* Tx interrupts */ |
366 | hw_atl_tdm_tx_desc_wr_wb_irq_en_set(aq_hw: self, tx_desc_wr_wb_irq_en: 1U); |
367 | |
368 | /* misc */ |
369 | hw_atl_tdm_tx_dca_en_set(aq_hw: self, tx_dca_en: 0U); |
370 | hw_atl_tdm_tx_dca_mode_set(aq_hw: self, tx_dca_mode: 0U); |
371 | |
372 | hw_atl_tpb_tx_path_scp_ins_en_set(aq_hw: self, tx_path_scp_ins_en: 1U); |
373 | |
374 | hw_atl2_tpb_tx_buf_clk_gate_en_set(aq_hw: self, clk_gate_en: 0U); |
375 | |
376 | return aq_hw_err_from_flags(hw: self); |
377 | } |
378 | |
379 | static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) |
380 | { |
381 | u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map; |
382 | struct hw_atl2_priv *priv = self->priv; |
383 | u16 action; |
384 | u8 index; |
385 | int i; |
386 | |
387 | /* Action Resolver Table (ART) is used by RPF to decide which action |
388 | * to take with a packet based upon input tag and tag mask, where: |
389 | * - input tag is a combination of 3-bit VLan Prio (PTP) and |
390 | * 29-bit concatenation of all tags from filter block; |
391 | * - tag mask is a mask used for matching against input tag. |
392 | * The input_tag is compared with the all the Requested_tags in the |
393 | * Record table to find a match. Action field of the selected matched |
394 | * REC entry is used for further processing. If multiple entries match, |
395 | * the lowest REC entry, Action field will be selected. |
396 | */ |
397 | hw_atl2_rpf_act_rslvr_section_en_set(aq_hw: self, sections: 0xFFFF); |
398 | hw_atl2_rpfl2_uc_flr_tag_set(aq_hw: self, HW_ATL2_RPF_TAG_BASE_UC, |
399 | HW_ATL2_MAC_UC); |
400 | hw_atl2_rpfl2_bc_flr_tag_set(aq_hw: self, HW_ATL2_RPF_TAG_BASE_UC); |
401 | |
402 | /* FW reserves the beginning of ART, thus all driver entries must |
403 | * start from the offset specified in FW caps. |
404 | */ |
405 | index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; |
406 | hw_atl2_act_rslvr_table_set(self, location: index, tag: 0, |
407 | HW_ATL2_RPF_TAG_UC_MASK | |
408 | HW_ATL2_RPF_TAG_ALLMC_MASK, |
409 | HW_ATL2_ACTION_DROP); |
410 | |
411 | index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; |
412 | hw_atl2_act_rslvr_table_set(self, location: index, tag: 0, |
413 | HW_ATL2_RPF_TAG_VLAN_MASK | |
414 | HW_ATL2_RPF_TAG_UNTAG_MASK, |
415 | HW_ATL2_ACTION_DROP); |
416 | |
417 | /* Configure ART to map given VLan Prio (PCP) to the TC index for |
418 | * RSS redirection table. |
419 | */ |
420 | for (i = 0; i < 8; i++) { |
421 | action = HW_ATL2_ACTION_ASSIGN_TC(prio_tc_map[i]); |
422 | |
423 | index = priv->art_base_index + HW_ATL2_RPF_PCP_TO_TC_INDEX + i; |
424 | hw_atl2_act_rslvr_table_set(self, location: index, |
425 | tag: i << HW_ATL2_RPF_TAG_PCP_OFFSET, |
426 | HW_ATL2_RPF_TAG_PCP_MASK, action); |
427 | } |
428 | } |
429 | |
430 | static void hw_atl2_hw_new_rx_filter_vlan_promisc(struct aq_hw_s *self, |
431 | bool promisc) |
432 | { |
433 | u16 off_action = (!promisc && |
434 | !hw_atl_rpfl2promiscuous_mode_en_get(aq_hw: self)) ? |
435 | HW_ATL2_ACTION_DROP : HW_ATL2_ACTION_DISABLE; |
436 | struct hw_atl2_priv *priv = self->priv; |
437 | u8 index; |
438 | |
439 | index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; |
440 | hw_atl2_act_rslvr_table_set(self, location: index, tag: 0, |
441 | HW_ATL2_RPF_TAG_VLAN_MASK | |
442 | HW_ATL2_RPF_TAG_UNTAG_MASK, action: off_action); |
443 | } |
444 | |
445 | static void hw_atl2_hw_new_rx_filter_promisc(struct aq_hw_s *self, bool promisc) |
446 | { |
447 | u16 off_action = promisc ? HW_ATL2_ACTION_DISABLE : HW_ATL2_ACTION_DROP; |
448 | struct hw_atl2_priv *priv = self->priv; |
449 | bool vlan_promisc_enable; |
450 | u8 index; |
451 | |
452 | index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; |
453 | hw_atl2_act_rslvr_table_set(self, location: index, tag: 0, |
454 | HW_ATL2_RPF_TAG_UC_MASK | |
455 | HW_ATL2_RPF_TAG_ALLMC_MASK, |
456 | action: off_action); |
457 | |
458 | /* turn VLAN promisc mode too */ |
459 | vlan_promisc_enable = hw_atl_rpf_vlan_prom_mode_en_get(aq_hw: self); |
460 | hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc: promisc | |
461 | vlan_promisc_enable); |
462 | } |
463 | |
464 | static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, |
465 | u32 tag, u32 mask, u32 action) |
466 | { |
467 | u32 val; |
468 | int err; |
469 | |
470 | err = readx_poll_timeout_atomic(hw_atl2_sem_act_rslvr_get, |
471 | self, val, val == 1, |
472 | 1, 10000U); |
473 | if (err) |
474 | return err; |
475 | |
476 | hw_atl2_rpf_act_rslvr_record_set(aq_hw: self, location, tag, mask, |
477 | action); |
478 | |
479 | hw_atl_reg_glb_cpu_sem_set(aq_hw: self, glb_cpu_sem: 1, HW_ATL2_FW_SM_ACT_RSLVR); |
480 | |
481 | return err; |
482 | } |
483 | |
484 | static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) |
485 | { |
486 | struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; |
487 | int i; |
488 | |
489 | /* Rx TC/RSS number config */ |
490 | hw_atl_rpb_rpf_rx_traf_class_mode_set(aq_hw: self, rx_traf_class_mode: cfg->tc_mode); |
491 | |
492 | /* Rx flow control */ |
493 | hw_atl_rpb_rx_flow_ctl_mode_set(aq_hw: self, rx_flow_ctl_mode: 1U); |
494 | |
495 | hw_atl2_rpf_rss_hash_type_set(aq_hw: self, rss_hash_type: HW_ATL2_RPF_RSS_HASH_TYPE_ALL); |
496 | |
497 | /* RSS Ring selection */ |
498 | hw_atl_b0_hw_init_rx_rss_ctrl1(self); |
499 | |
500 | /* Multicast filters */ |
501 | for (i = HW_ATL2_MAC_MAX; i--;) { |
502 | hw_atl_rpfl2_uc_flr_en_set(aq_hw: self, l2unicast_flr_en: (i == 0U) ? 1U : 0U, filter: i); |
503 | hw_atl_rpfl2unicast_flr_act_set(aq_hw: self, l2unicast_flr_act: 1U, filter: i); |
504 | } |
505 | |
506 | hw_atl_reg_rx_flr_mcst_flr_msk_set(aq_hw: self, rx_flr_mcst_flr_msk: 0x00000000U); |
507 | hw_atl_reg_rx_flr_mcst_flr_set(aq_hw: self, HW_ATL_MCAST_FLT_ANY_TO_HOST, filter: 0U); |
508 | |
509 | /* Vlan filters */ |
510 | hw_atl_rpf_vlan_outer_etht_set(aq_hw: self, ETH_P_8021AD); |
511 | hw_atl_rpf_vlan_inner_etht_set(aq_hw: self, ETH_P_8021Q); |
512 | |
513 | hw_atl_rpf_vlan_prom_mode_en_set(aq_hw: self, vlan_prom_mode_en: 1); |
514 | |
515 | /* Always accept untagged packets */ |
516 | hw_atl_rpf_vlan_accept_untagged_packets_set(aq_hw: self, vlan_acc_untagged_packets: 1U); |
517 | hw_atl_rpf_vlan_untagged_act_set(aq_hw: self, vlan_untagged_act: 1U); |
518 | |
519 | hw_atl2_hw_init_new_rx_filters(self); |
520 | |
521 | /* Rx Interrupts */ |
522 | hw_atl_rdm_rx_desc_wr_wb_irq_en_set(aq_hw: self, rx_desc_wr_wb_irq_en: 1U); |
523 | |
524 | hw_atl_rpfl2broadcast_flr_act_set(aq_hw: self, l2broadcast_flr_act: 1U); |
525 | hw_atl_rpfl2broadcast_count_threshold_set(aq_hw: self, l2broadcast_count_threshold: 0xFFFFU & (~0U / 256U)); |
526 | |
527 | hw_atl_rdm_rx_dca_en_set(aq_hw: self, rx_dca_en: 0U); |
528 | hw_atl_rdm_rx_dca_mode_set(aq_hw: self, rx_dca_mode: 0U); |
529 | |
530 | return aq_hw_err_from_flags(hw: self); |
531 | } |
532 | |
533 | static int hw_atl2_hw_init(struct aq_hw_s *self, const u8 *mac_addr) |
534 | { |
535 | static u32 aq_hw_atl2_igcr_table_[4][2] = { |
536 | [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U }, |
537 | [AQ_HW_IRQ_LEGACY] = { 0x20000080U, 0x20000080U }, |
538 | [AQ_HW_IRQ_MSI] = { 0x20000021U, 0x20000025U }, |
539 | [AQ_HW_IRQ_MSIX] = { 0x20000022U, 0x20000026U }, |
540 | }; |
541 | |
542 | struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg; |
543 | struct hw_atl2_priv *priv = self->priv; |
544 | u8 base_index, count; |
545 | int err; |
546 | |
547 | err = hw_atl2_utils_get_action_resolve_table_caps(self, base_index: &base_index, |
548 | count: &count); |
549 | if (err) |
550 | return err; |
551 | |
552 | priv->art_base_index = 8 * base_index; |
553 | |
554 | hw_atl2_init_launchtime(aq_hw: self); |
555 | |
556 | hw_atl2_hw_init_tx_path(self); |
557 | hw_atl2_hw_init_rx_path(self); |
558 | |
559 | hw_atl_b0_hw_mac_addr_set(self, mac_addr); |
560 | |
561 | self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); |
562 | self->aq_fw_ops->set_state(self, MPI_INIT); |
563 | |
564 | hw_atl2_hw_qos_set(self); |
565 | hw_atl2_hw_rss_set(self, rss_params: &aq_nic_cfg->aq_rss); |
566 | hw_atl_b0_hw_rss_hash_set(self, rss_params: &aq_nic_cfg->aq_rss); |
567 | |
568 | hw_atl2_rpf_new_enable_set(aq_hw: self, enable: 1); |
569 | |
570 | /* Reset link status and read out initial hardware counters */ |
571 | self->aq_link_status.mbps = 0; |
572 | self->aq_fw_ops->update_stats(self); |
573 | |
574 | err = aq_hw_err_from_flags(hw: self); |
575 | if (err < 0) |
576 | goto err_exit; |
577 | |
578 | /* Interrupts */ |
579 | hw_atl_reg_irq_glb_ctl_set(aq_hw: self, |
580 | intr_glb_ctl: aq_hw_atl2_igcr_table_[aq_nic_cfg->irq_type] |
581 | [(aq_nic_cfg->vecs > 1U) ? |
582 | 1 : 0]); |
583 | |
584 | hw_atl_itr_irq_auto_masklsw_set(aq_hw: self, irq_auto_masklsw: aq_nic_cfg->aq_hw_caps->irq_mask); |
585 | |
586 | /* Interrupts */ |
587 | hw_atl_reg_gen_irq_map_set(aq_hw: self, |
588 | gen_intr_map: ((HW_ATL2_ERR_INT << 0x18) | |
589 | (1U << 0x1F)) | |
590 | ((HW_ATL2_ERR_INT << 0x10) | |
591 | (1U << 0x17)), regidx: 0U); |
592 | |
593 | hw_atl_b0_hw_offload_set(self, aq_nic_cfg); |
594 | |
595 | err_exit: |
596 | return err; |
597 | } |
598 | |
599 | static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self, |
600 | struct aq_ring_s *aq_ring, |
601 | struct aq_ring_param_s *aq_ring_param) |
602 | { |
603 | return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); |
604 | } |
605 | |
606 | static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self, |
607 | struct aq_ring_s *aq_ring, |
608 | struct aq_ring_param_s *aq_ring_param) |
609 | { |
610 | return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); |
611 | } |
612 | |
613 | #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) |
614 | |
615 | static int hw_atl2_hw_packet_filter_set(struct aq_hw_s *self, |
616 | unsigned int packet_filter) |
617 | { |
618 | hw_atl2_hw_new_rx_filter_promisc(self, IS_FILTER_ENABLED(IFF_PROMISC)); |
619 | |
620 | return hw_atl_b0_hw_packet_filter_set(self, packet_filter); |
621 | } |
622 | |
623 | #undef IS_FILTER_ENABLED |
624 | |
625 | static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self, |
626 | u8 ar_mac |
627 | [AQ_HW_MULTICAST_ADDRESS_MAX] |
628 | [ETH_ALEN], |
629 | u32 count) |
630 | { |
631 | struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; |
632 | int err = 0; |
633 | |
634 | if (count > (HW_ATL2_MAC_MAX - HW_ATL2_MAC_MIN)) { |
635 | err = -EBADRQC; |
636 | goto err_exit; |
637 | } |
638 | for (cfg->mc_list_count = 0U; |
639 | cfg->mc_list_count < count; |
640 | ++cfg->mc_list_count) { |
641 | u32 i = cfg->mc_list_count; |
642 | u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); |
643 | u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | |
644 | (ar_mac[i][4] << 8) | ar_mac[i][5]; |
645 | |
646 | hw_atl_rpfl2_uc_flr_en_set(aq_hw: self, l2unicast_flr_en: 0U, HW_ATL2_MAC_MIN + i); |
647 | |
648 | hw_atl_rpfl2unicast_dest_addresslsw_set(aq_hw: self, l2unicast_dest_addresslsw: l, |
649 | HW_ATL2_MAC_MIN + i); |
650 | |
651 | hw_atl_rpfl2unicast_dest_addressmsw_set(aq_hw: self, l2unicast_dest_addressmsw: h, |
652 | HW_ATL2_MAC_MIN + i); |
653 | |
654 | hw_atl2_rpfl2_uc_flr_tag_set(aq_hw: self, tag: 1, HW_ATL2_MAC_MIN + i); |
655 | |
656 | hw_atl_rpfl2_uc_flr_en_set(aq_hw: self, l2unicast_flr_en: (cfg->is_mc_list_enabled), |
657 | HW_ATL2_MAC_MIN + i); |
658 | } |
659 | |
660 | err = aq_hw_err_from_flags(hw: self); |
661 | |
662 | err_exit: |
663 | return err; |
664 | } |
665 | |
666 | static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self) |
667 | { |
668 | unsigned int i = 0U; |
669 | u32 itr_tx = 2U; |
670 | u32 itr_rx = 2U; |
671 | |
672 | switch (self->aq_nic_cfg->itr) { |
673 | case AQ_CFG_INTERRUPT_MODERATION_ON: |
674 | case AQ_CFG_INTERRUPT_MODERATION_AUTO: |
675 | hw_atl_tdm_tx_desc_wr_wb_irq_en_set(aq_hw: self, tx_desc_wr_wb_irq_en: 0U); |
676 | hw_atl_tdm_tdm_intr_moder_en_set(aq_hw: self, tdm_irq_moderation_en: 1U); |
677 | hw_atl_rdm_rx_desc_wr_wb_irq_en_set(aq_hw: self, rx_desc_wr_wb_irq_en: 0U); |
678 | hw_atl_rdm_rdm_intr_moder_en_set(aq_hw: self, rdm_intr_moder_en: 1U); |
679 | |
680 | if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { |
681 | /* HW timers are in 2us units */ |
682 | int tx_max_timer = self->aq_nic_cfg->tx_itr / 2; |
683 | int tx_min_timer = tx_max_timer / 2; |
684 | |
685 | int rx_max_timer = self->aq_nic_cfg->rx_itr / 2; |
686 | int rx_min_timer = rx_max_timer / 2; |
687 | |
688 | tx_max_timer = min(HW_ATL2_INTR_MODER_MAX, |
689 | tx_max_timer); |
690 | tx_min_timer = min(HW_ATL2_INTR_MODER_MIN, |
691 | tx_min_timer); |
692 | rx_max_timer = min(HW_ATL2_INTR_MODER_MAX, |
693 | rx_max_timer); |
694 | rx_min_timer = min(HW_ATL2_INTR_MODER_MIN, |
695 | rx_min_timer); |
696 | |
697 | itr_tx |= tx_min_timer << 0x8U; |
698 | itr_tx |= tx_max_timer << 0x10U; |
699 | itr_rx |= rx_min_timer << 0x8U; |
700 | itr_rx |= rx_max_timer << 0x10U; |
701 | } else { |
702 | static unsigned int hw_atl2_timers_table_tx_[][2] = { |
703 | {0xfU, 0xffU}, /* 10Gbit */ |
704 | {0xfU, 0x1ffU}, /* 5Gbit */ |
705 | {0xfU, 0x1ffU}, /* 5Gbit 5GS */ |
706 | {0xfU, 0x1ffU}, /* 2.5Gbit */ |
707 | {0xfU, 0x1ffU}, /* 1Gbit */ |
708 | {0xfU, 0x1ffU}, /* 100Mbit */ |
709 | }; |
710 | static unsigned int hw_atl2_timers_table_rx_[][2] = { |
711 | {0x6U, 0x38U},/* 10Gbit */ |
712 | {0xCU, 0x70U},/* 5Gbit */ |
713 | {0xCU, 0x70U},/* 5Gbit 5GS */ |
714 | {0x18U, 0xE0U},/* 2.5Gbit */ |
715 | {0x30U, 0x80U},/* 1Gbit */ |
716 | {0x4U, 0x50U},/* 100Mbit */ |
717 | }; |
718 | unsigned int mbps = self->aq_link_status.mbps; |
719 | unsigned int speed_index; |
720 | |
721 | speed_index = hw_atl_utils_mbps_2_speed_index(mbps); |
722 | |
723 | /* Update user visible ITR settings */ |
724 | self->aq_nic_cfg->tx_itr = hw_atl2_timers_table_tx_ |
725 | [speed_index][1] * 2; |
726 | self->aq_nic_cfg->rx_itr = hw_atl2_timers_table_rx_ |
727 | [speed_index][1] * 2; |
728 | |
729 | itr_tx |= hw_atl2_timers_table_tx_ |
730 | [speed_index][0] << 0x8U; |
731 | itr_tx |= hw_atl2_timers_table_tx_ |
732 | [speed_index][1] << 0x10U; |
733 | |
734 | itr_rx |= hw_atl2_timers_table_rx_ |
735 | [speed_index][0] << 0x8U; |
736 | itr_rx |= hw_atl2_timers_table_rx_ |
737 | [speed_index][1] << 0x10U; |
738 | } |
739 | break; |
740 | case AQ_CFG_INTERRUPT_MODERATION_OFF: |
741 | hw_atl_tdm_tx_desc_wr_wb_irq_en_set(aq_hw: self, tx_desc_wr_wb_irq_en: 1U); |
742 | hw_atl_tdm_tdm_intr_moder_en_set(aq_hw: self, tdm_irq_moderation_en: 0U); |
743 | hw_atl_rdm_rx_desc_wr_wb_irq_en_set(aq_hw: self, rx_desc_wr_wb_irq_en: 1U); |
744 | hw_atl_rdm_rdm_intr_moder_en_set(aq_hw: self, rdm_intr_moder_en: 0U); |
745 | itr_tx = 0U; |
746 | itr_rx = 0U; |
747 | break; |
748 | } |
749 | |
750 | for (i = HW_ATL2_RINGS_MAX; i--;) { |
751 | hw_atl2_reg_tx_intr_moder_ctrl_set(aq_hw: self, tx_intr_moderation_ctl: itr_tx, queue: i); |
752 | hw_atl_reg_rx_intr_moder_ctrl_set(aq_hw: self, rx_intr_moderation_ctl: itr_rx, queue: i); |
753 | } |
754 | |
755 | return aq_hw_err_from_flags(hw: self); |
756 | } |
757 | |
758 | static int hw_atl2_hw_stop(struct aq_hw_s *self) |
759 | { |
760 | hw_atl_b0_hw_irq_disable(self, HW_ATL2_INT_MASK); |
761 | |
762 | return 0; |
763 | } |
764 | |
765 | static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self) |
766 | { |
767 | return &self->curr_stats; |
768 | } |
769 | |
770 | static int hw_atl2_hw_vlan_set(struct aq_hw_s *self, |
771 | struct aq_rx_filter_vlan *aq_vlans) |
772 | { |
773 | struct hw_atl2_priv *priv = self->priv; |
774 | u32 queue; |
775 | u8 index; |
776 | int i; |
777 | |
778 | hw_atl_rpf_vlan_prom_mode_en_set(aq_hw: self, vlan_prom_mode_en: 1U); |
779 | |
780 | for (i = 0; i < HW_ATL_VLAN_MAX_FILTERS; i++) { |
781 | queue = HW_ATL2_ACTION_ASSIGN_QUEUE(aq_vlans[i].queue); |
782 | |
783 | hw_atl_rpf_vlan_flr_en_set(aq_hw: self, vlan_flr_en: 0U, filter: i); |
784 | hw_atl_rpf_vlan_rxq_en_flr_set(aq_hw: self, vlan_rxq_en: 0U, filter: i); |
785 | index = priv->art_base_index + HW_ATL2_RPF_VLAN_USER_INDEX + i; |
786 | hw_atl2_act_rslvr_table_set(self, location: index, tag: 0, mask: 0, |
787 | HW_ATL2_ACTION_DISABLE); |
788 | if (aq_vlans[i].enable) { |
789 | hw_atl_rpf_vlan_id_flr_set(aq_hw: self, |
790 | vlan_id_flr: aq_vlans[i].vlan_id, filter: i); |
791 | hw_atl_rpf_vlan_flr_act_set(aq_hw: self, vlan_filter_act: 1U, filter: i); |
792 | hw_atl_rpf_vlan_flr_en_set(aq_hw: self, vlan_flr_en: 1U, filter: i); |
793 | |
794 | if (aq_vlans[i].queue != 0xFF) { |
795 | hw_atl_rpf_vlan_rxq_flr_set(aq_hw: self, |
796 | vlan_rxq: aq_vlans[i].queue, |
797 | filter: i); |
798 | hw_atl_rpf_vlan_rxq_en_flr_set(aq_hw: self, vlan_rxq_en: 1U, filter: i); |
799 | |
800 | hw_atl2_rpf_vlan_flr_tag_set(aq_hw: self, tag: i + 2, filter: i); |
801 | |
802 | index = priv->art_base_index + |
803 | HW_ATL2_RPF_VLAN_USER_INDEX + i; |
804 | hw_atl2_act_rslvr_table_set(self, location: index, |
805 | tag: (i + 2) << HW_ATL2_RPF_TAG_VLAN_OFFSET, |
806 | HW_ATL2_RPF_TAG_VLAN_MASK, action: queue); |
807 | } else { |
808 | hw_atl2_rpf_vlan_flr_tag_set(aq_hw: self, tag: 1, filter: i); |
809 | } |
810 | } |
811 | } |
812 | |
813 | return aq_hw_err_from_flags(hw: self); |
814 | } |
815 | |
816 | static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) |
817 | { |
818 | /* set promisc in case of disabing the vlan filter */ |
819 | hw_atl_rpf_vlan_prom_mode_en_set(aq_hw: self, vlan_prom_mode_en: !enable); |
820 | hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc: !enable); |
821 | |
822 | return aq_hw_err_from_flags(hw: self); |
823 | } |
824 | |
825 | const struct aq_hw_ops hw_atl2_ops = { |
826 | .hw_soft_reset = hw_atl2_utils_soft_reset, |
827 | .hw_prepare = hw_atl2_utils_initfw, |
828 | .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, |
829 | .hw_init = hw_atl2_hw_init, |
830 | .hw_reset = hw_atl2_hw_reset, |
831 | .hw_start = hw_atl_b0_hw_start, |
832 | .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start, |
833 | .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop, |
834 | .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start, |
835 | .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop, |
836 | .hw_stop = hw_atl2_hw_stop, |
837 | |
838 | .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit, |
839 | .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update, |
840 | |
841 | .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive, |
842 | .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill, |
843 | |
844 | .hw_irq_enable = hw_atl_b0_hw_irq_enable, |
845 | .hw_irq_disable = hw_atl_b0_hw_irq_disable, |
846 | .hw_irq_read = hw_atl_b0_hw_irq_read, |
847 | |
848 | .hw_ring_rx_init = hw_atl2_hw_ring_rx_init, |
849 | .hw_ring_tx_init = hw_atl2_hw_ring_tx_init, |
850 | .hw_packet_filter_set = hw_atl2_hw_packet_filter_set, |
851 | .hw_filter_vlan_set = hw_atl2_hw_vlan_set, |
852 | .hw_filter_vlan_ctrl = hw_atl2_hw_vlan_ctrl, |
853 | .hw_multicast_list_set = hw_atl2_hw_multicast_list_set, |
854 | .hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set, |
855 | .hw_rss_set = hw_atl2_hw_rss_set, |
856 | .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, |
857 | .hw_tc_rate_limit_set = hw_atl2_hw_init_tx_tc_rate_limit, |
858 | .hw_get_hw_stats = hw_atl2_utils_get_hw_stats, |
859 | .hw_get_fw_version = hw_atl2_utils_get_fw_version, |
860 | .hw_set_offload = hw_atl_b0_hw_offload_set, |
861 | .hw_set_loopback = hw_atl_b0_set_loopback, |
862 | .hw_set_fc = hw_atl_b0_set_fc, |
863 | }; |
864 | |