1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Linux network driver for QLogic BR-series Converged Network Adapter. |
4 | */ |
5 | /* |
6 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
7 | * Copyright (c) 2014-2015 QLogic Corporation |
8 | * All rights reserved |
9 | * www.qlogic.com |
10 | */ |
11 | |
12 | /* File for interrupt macros and functions */ |
13 | |
14 | #ifndef __BNA_HW_DEFS_H__ |
15 | #define __BNA_HW_DEFS_H__ |
16 | |
17 | #include "bfi_reg.h" |
18 | |
19 | /* SW imposed limits */ |
20 | |
21 | #define BFI_ENET_DEF_TXQ 1 |
22 | #define BFI_ENET_DEF_RXP 1 |
23 | #define BFI_ENET_DEF_UCAM 1 |
24 | #define BFI_ENET_DEF_RITSZ 1 |
25 | |
26 | #define BFI_ENET_MAX_MCAM 256 |
27 | |
28 | #define BFI_INVALID_RID -1 |
29 | |
30 | #define BFI_IBIDX_SIZE 4 |
31 | |
32 | #define BFI_VLAN_WORD_SHIFT 5 /* 32 bits */ |
33 | #define BFI_VLAN_WORD_MASK 0x1F |
34 | #define BFI_VLAN_BLOCK_SHIFT 9 /* 512 bits */ |
35 | #define BFI_VLAN_BMASK_ALL 0xFF |
36 | |
37 | #define BFI_COALESCING_TIMER_UNIT 5 /* 5us */ |
38 | #define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */ |
39 | #define BFI_MAX_INTERPKT_COUNT 0xFF |
40 | #define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */ |
41 | #define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */ |
42 | #define BFI_TX_INTERPKT_COUNT 12 /* Pkt Cnt = 12 */ |
43 | #define BFI_TX_INTERPKT_TIMEO 15 /* 15 * 0.5 = 7.5us */ |
44 | #define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */ |
45 | #define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */ |
46 | #define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */ |
47 | |
48 | #define BFI_TXQ_WI_SIZE 64 /* bytes */ |
49 | #define BFI_RXQ_WI_SIZE 8 /* bytes */ |
50 | #define BFI_CQ_WI_SIZE 16 /* bytes */ |
51 | #define BFI_TX_MAX_WRR_QUOTA 0xFFF |
52 | |
53 | #define BFI_TX_MAX_VECTORS_PER_WI 4 |
54 | #define BFI_TX_MAX_VECTORS_PER_PKT 0xFF |
55 | #define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF |
56 | #define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF |
57 | |
58 | /* Small Q buffer size */ |
59 | #define BFI_SMALL_RXBUF_SIZE 128 |
60 | |
61 | #define BFI_TX_MAX_PRIO 8 |
62 | #define BFI_TX_PRIO_MAP_ALL 0xFF |
63 | |
64 | /* |
65 | * |
66 | * Register definitions and macros |
67 | * |
68 | */ |
69 | |
70 | #define BNA_PCI_REG_CT_ADDRSZ (0x40000) |
71 | |
72 | #define ct_reg_addr_init(_bna, _pcidev) \ |
73 | { \ |
74 | struct bna_reg_offset reg_offset[] = \ |
75 | {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK}, \ |
76 | {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK}, \ |
77 | {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK}, \ |
78 | {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} }; \ |
79 | \ |
80 | (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ |
81 | reg_offset[(_pcidev)->pci_func].fn_int_status;\ |
82 | (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ |
83 | reg_offset[(_pcidev)->pci_func].fn_int_mask;\ |
84 | } |
85 | |
86 | #define ct_bit_defn_init(_bna, _pcidev) \ |
87 | { \ |
88 | (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \ |
89 | __HFN_INT_MBOX_LPU1); \ |
90 | (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \ |
91 | __HFN_INT_MBOX_LPU1); \ |
92 | (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \ |
93 | (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \ |
94 | (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \ |
95 | (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \ |
96 | } |
97 | |
98 | #define ct2_reg_addr_init(_bna, _pcidev) \ |
99 | { \ |
100 | (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ |
101 | CT2_HOSTFN_INT_STATUS; \ |
102 | (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ |
103 | CT2_HOSTFN_INTR_MASK; \ |
104 | } |
105 | |
106 | #define ct2_bit_defn_init(_bna, _pcidev) \ |
107 | { \ |
108 | (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ |
109 | __HFN_INT_MBOX_LPU1_CT2); \ |
110 | (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ |
111 | __HFN_INT_MBOX_LPU1_CT2); \ |
112 | (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \ |
113 | (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \ |
114 | (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2; \ |
115 | (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2; \ |
116 | } |
117 | |
118 | #define bna_reg_addr_init(_bna, _pcidev) \ |
119 | { \ |
120 | switch ((_pcidev)->device_id) { \ |
121 | case PCI_DEVICE_ID_BROCADE_CT: \ |
122 | ct_reg_addr_init((_bna), (_pcidev)); \ |
123 | ct_bit_defn_init((_bna), (_pcidev)); \ |
124 | break; \ |
125 | case BFA_PCI_DEVICE_ID_CT2: \ |
126 | ct2_reg_addr_init((_bna), (_pcidev)); \ |
127 | ct2_bit_defn_init((_bna), (_pcidev)); \ |
128 | break; \ |
129 | } \ |
130 | } |
131 | |
132 | #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id) |
133 | |
134 | /* Interrupt related bits, flags and macros */ |
135 | |
136 | #define IB_STATUS_BITS 0x0000ffff |
137 | |
138 | #define BNA_IS_MBOX_INTR(_bna, _intr_status) \ |
139 | ((_intr_status) & (_bna)->bits.mbox_status_bits) |
140 | |
141 | #define BNA_IS_HALT_INTR(_bna, _intr_status) \ |
142 | ((_intr_status) & (_bna)->bits.halt_status_bits) |
143 | |
144 | #define BNA_IS_ERR_INTR(_bna, _intr_status) \ |
145 | ((_intr_status) & (_bna)->bits.error_status_bits) |
146 | |
147 | #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status) \ |
148 | (BNA_IS_MBOX_INTR(_bna, _intr_status) | \ |
149 | BNA_IS_ERR_INTR(_bna, _intr_status)) |
150 | |
151 | #define BNA_IS_INTX_DATA_INTR(_intr_status) \ |
152 | ((_intr_status) & IB_STATUS_BITS) |
153 | |
154 | #define bna_halt_clear(_bna) \ |
155 | do { \ |
156 | u32 init_halt; \ |
157 | init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ |
158 | init_halt &= ~__FW_INIT_HALT_P; \ |
159 | writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \ |
160 | init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ |
161 | } while (0) |
162 | |
163 | #define bna_intx_disable(_bna, _cur_mask) \ |
164 | { \ |
165 | (_cur_mask) = readl((_bna)->regs.fn_int_mask); \ |
166 | writel(0xffffffff, (_bna)->regs.fn_int_mask); \ |
167 | } |
168 | |
169 | #define bna_intx_enable(bna, new_mask) \ |
170 | writel((new_mask), (bna)->regs.fn_int_mask) |
171 | #define bna_mbox_intr_disable(bna) \ |
172 | do { \ |
173 | u32 mask; \ |
174 | mask = readl((bna)->regs.fn_int_mask); \ |
175 | writel((mask | (bna)->bits.mbox_mask_bits | \ |
176 | (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \ |
177 | mask = readl((bna)->regs.fn_int_mask); \ |
178 | } while (0) |
179 | |
180 | #define bna_mbox_intr_enable(bna) \ |
181 | do { \ |
182 | u32 mask; \ |
183 | mask = readl((bna)->regs.fn_int_mask); \ |
184 | writel((mask & ~((bna)->bits.mbox_mask_bits | \ |
185 | (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\ |
186 | mask = readl((bna)->regs.fn_int_mask); \ |
187 | } while (0) |
188 | |
189 | #define bna_intr_status_get(_bna, _status) \ |
190 | { \ |
191 | (_status) = readl((_bna)->regs.fn_int_status); \ |
192 | if (_status) { \ |
193 | writel(((_status) & ~(_bna)->bits.mbox_status_bits), \ |
194 | (_bna)->regs.fn_int_status); \ |
195 | } \ |
196 | } |
197 | |
198 | /* |
199 | * MAX ACK EVENTS : No. of acks that can be accumulated in driver, |
200 | * before acking to h/w. The no. of bits is 16 in the doorbell register, |
201 | * however we keep this limited to 15 bits. |
202 | * This is because around the edge of 64K boundary (16 bits), one |
203 | * single poll can make the accumulated ACK counter cross the 64K boundary, |
204 | * causing problems, when we try to ack with a value greater than 64K. |
205 | * 15 bits (32K) should be large enough to accumulate, anyways, and the max. |
206 | * acked events to h/w can be (32K + max poll weight) (currently 64). |
207 | */ |
208 | #define BNA_IB_MAX_ACK_EVENTS BIT(15) |
209 | |
210 | /* These macros build the data portion of the TxQ/RxQ doorbell */ |
211 | #define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi)) |
212 | #define BNA_DOORBELL_Q_STOP (0x40000000) |
213 | |
214 | /* These macros build the data portion of the IB doorbell */ |
215 | #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ |
216 | (0x80000000 | ((_timeout) << 16) | (_events)) |
217 | #define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) |
218 | |
219 | /* Set the coalescing timer for the given ib */ |
220 | #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \ |
221 | ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0)) |
222 | |
223 | /* Acks 'events' # of events for a given ib while disabling interrupts */ |
224 | #define bna_ib_ack_disable_irq(_i_dbell, _events) \ |
225 | (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \ |
226 | (_i_dbell)->doorbell_addr)) |
227 | |
228 | /* Acks 'events' # of events for a given ib */ |
229 | #define bna_ib_ack(_i_dbell, _events) \ |
230 | (writel(((_i_dbell)->doorbell_ack | (_events)), \ |
231 | (_i_dbell)->doorbell_addr)) |
232 | |
233 | #define bna_ib_start(_bna, _ib, _is_regular) \ |
234 | { \ |
235 | u32 intx_mask; \ |
236 | struct bna_ib *ib = _ib; \ |
237 | if ((ib->intr_type == BNA_INTR_T_INTX)) { \ |
238 | bna_intx_disable((_bna), intx_mask); \ |
239 | intx_mask &= ~(ib->intr_vector); \ |
240 | bna_intx_enable((_bna), intx_mask); \ |
241 | } \ |
242 | bna_ib_coalescing_timer_set(&ib->door_bell, \ |
243 | ib->coalescing_timeo); \ |
244 | if (_is_regular) \ |
245 | bna_ib_ack(&ib->door_bell, 0); \ |
246 | } |
247 | |
248 | #define bna_ib_stop(_bna, _ib) \ |
249 | { \ |
250 | u32 intx_mask; \ |
251 | struct bna_ib *ib = _ib; \ |
252 | writel(BNA_DOORBELL_IB_INT_DISABLE, \ |
253 | ib->door_bell.doorbell_addr); \ |
254 | if (ib->intr_type == BNA_INTR_T_INTX) { \ |
255 | bna_intx_disable((_bna), intx_mask); \ |
256 | intx_mask |= ib->intr_vector; \ |
257 | bna_intx_enable((_bna), intx_mask); \ |
258 | } \ |
259 | } |
260 | |
261 | #define bna_txq_prod_indx_doorbell(_tcb) \ |
262 | (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \ |
263 | (_tcb)->q_dbell)) |
264 | |
265 | #define bna_rxq_prod_indx_doorbell(_rcb) \ |
266 | (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \ |
267 | (_rcb)->q_dbell)) |
268 | |
269 | /* TxQ, RxQ, CQ related bits, offsets, macros */ |
270 | |
271 | /* TxQ Entry Opcodes */ |
272 | #define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ |
273 | #define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ |
274 | #define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ |
275 | |
276 | /* TxQ Entry Control Flags */ |
277 | #define BNA_TXQ_WI_CF_FCOE_CRC BIT(8) |
278 | #define BNA_TXQ_WI_CF_IPID_MODE BIT(5) |
279 | #define BNA_TXQ_WI_CF_INS_PRIO BIT(4) |
280 | #define BNA_TXQ_WI_CF_INS_VLAN BIT(3) |
281 | #define BNA_TXQ_WI_CF_UDP_CKSUM BIT(2) |
282 | #define BNA_TXQ_WI_CF_TCP_CKSUM BIT(1) |
283 | #define BNA_TXQ_WI_CF_IP_CKSUM BIT(0) |
284 | |
285 | #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ |
286 | (((_hdr_size) << 10) | ((_offset) & 0x3FF)) |
287 | |
288 | /* |
289 | * Completion Q defines |
290 | */ |
291 | /* CQ Entry Flags */ |
292 | #define BNA_CQ_EF_MAC_ERROR BIT(0) |
293 | #define BNA_CQ_EF_FCS_ERROR BIT(1) |
294 | #define BNA_CQ_EF_TOO_LONG BIT(2) |
295 | #define BNA_CQ_EF_FC_CRC_OK BIT(3) |
296 | |
297 | #define BNA_CQ_EF_RSVD1 BIT(4) |
298 | #define BNA_CQ_EF_L4_CKSUM_OK BIT(5) |
299 | #define BNA_CQ_EF_L3_CKSUM_OK BIT(6) |
300 | #define BIT(7) |
301 | |
302 | #define BNA_CQ_EF_UDP BIT(8) |
303 | #define BNA_CQ_EF_TCP BIT(9) |
304 | #define BNA_CQ_EF_IP_OPTIONS BIT(10) |
305 | #define BNA_CQ_EF_IPV6 BIT(11) |
306 | |
307 | #define BNA_CQ_EF_IPV4 BIT(12) |
308 | #define BNA_CQ_EF_VLAN BIT(13) |
309 | #define BIT(14) |
310 | #define BNA_CQ_EF_RSVD2 BIT(15) |
311 | |
312 | #define BNA_CQ_EF_MCAST_MATCH BIT(16) |
313 | #define BNA_CQ_EF_MCAST BIT(17) |
314 | #define BNA_CQ_EF_BCAST BIT(18) |
315 | #define BNA_CQ_EF_REMOTE BIT(19) |
316 | |
317 | #define BNA_CQ_EF_LOCAL BIT(20) |
318 | /* CAT2 ASIC does not use bit 21 as per the SPEC. |
319 | * Bit 31 is set in every end of frame completion |
320 | */ |
321 | #define BNA_CQ_EF_EOP BIT(31) |
322 | |
323 | /* Data structures */ |
324 | |
325 | struct bna_reg_offset { |
326 | u32 fn_int_status; |
327 | u32 fn_int_mask; |
328 | }; |
329 | |
330 | struct bna_bit_defn { |
331 | u32 mbox_status_bits; |
332 | u32 mbox_mask_bits; |
333 | u32 error_status_bits; |
334 | u32 error_mask_bits; |
335 | u32 halt_status_bits; |
336 | u32 halt_mask_bits; |
337 | }; |
338 | |
339 | struct bna_reg { |
340 | void __iomem *fn_int_status; |
341 | void __iomem *fn_int_mask; |
342 | }; |
343 | |
344 | /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ |
345 | struct bna_dma_addr { |
346 | u32 msb; |
347 | u32 lsb; |
348 | }; |
349 | |
350 | struct bna_txq_wi_vector { |
351 | u16 reserved; |
352 | u16 length; /* Only 14 LSB are valid */ |
353 | struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ |
354 | }; |
355 | |
356 | /* TxQ Entry Structure |
357 | * |
358 | * BEWARE: Load values into this structure with correct endianness. |
359 | */ |
360 | struct bna_txq_entry { |
361 | union { |
362 | struct { |
363 | u8 reserved; |
364 | u8 num_vectors; /* number of vectors present */ |
365 | u16 opcode; /* Either */ |
366 | /* BNA_TXQ_WI_SEND or */ |
367 | /* BNA_TXQ_WI_SEND_LSO */ |
368 | u16 flags; /* OR of all the flags */ |
369 | u16 l4_hdr_size_n_offset; |
370 | u16 vlan_tag; |
371 | u16 lso_mss; /* Only 14 LSB are valid */ |
372 | u32 frame_length; /* Only 24 LSB are valid */ |
373 | } wi; |
374 | |
375 | struct { |
376 | u16 reserved; |
377 | u16 opcode; /* Must be */ |
378 | /* BNA_TXQ_WI_EXTENSION */ |
379 | u32 reserved2[3]; /* Place holder for */ |
380 | /* removed vector (12 bytes) */ |
381 | } wi_ext; |
382 | } hdr; |
383 | struct bna_txq_wi_vector vector[4]; |
384 | }; |
385 | |
386 | /* RxQ Entry Structure */ |
387 | struct bna_rxq_entry { /* Rx-Buffer */ |
388 | struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */ |
389 | }; |
390 | |
391 | /* CQ Entry Structure */ |
392 | struct bna_cq_entry { |
393 | u32 flags; |
394 | u16 vlan_tag; |
395 | u16 length; |
396 | u32 ; |
397 | u8 valid; |
398 | u8 reserved1; |
399 | u8 reserved2; |
400 | u8 rxq_id; |
401 | }; |
402 | |
403 | #endif /* __BNA_HW_DEFS_H__ */ |
404 | |