1/* SPDX-License-Identifier: GPL-2.0+ */
2// Copyright (c) 2016-2017 Hisilicon Limited.
3
4#ifndef __HNAE3_H
5#define __HNAE3_H
6
7/* Names used in this framework:
8 * ae handle (handle):
9 * a set of queues provided by AE
10 * ring buffer queue (rbq):
11 * the channel between upper layer and the AE, can do tx and rx
12 * ring:
13 * a tx or rx channel within a rbq
14 * ring description (desc):
15 * an element in the ring with packet information
16 * buffer:
17 * a memory region referred by desc with the full packet payload
18 *
19 * "num" means a static number set as a parameter, "count" mean a dynamic
20 * number set while running
21 * "cb" means control block
22 */
23
24#include <linux/acpi.h>
25#include <linux/dcbnl.h>
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/ethtool.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
31#include <linux/pci.h>
32#include <linux/pkt_sched.h>
33#include <linux/types.h>
34#include <linux/bitmap.h>
35#include <net/pkt_cls.h>
36#include <net/pkt_sched.h>
37
38#define HNAE3_MOD_VERSION "1.0"
39
40#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
41
42/* Device version */
43#define HNAE3_DEVICE_VERSION_V1 0x00020
44#define HNAE3_DEVICE_VERSION_V2 0x00021
45#define HNAE3_DEVICE_VERSION_V3 0x00030
46
47#define HNAE3_PCI_REVISION_BIT_SIZE 8
48
49/* Device IDs */
50#define HNAE3_DEV_ID_GE 0xA220
51#define HNAE3_DEV_ID_25GE 0xA221
52#define HNAE3_DEV_ID_25GE_RDMA 0xA222
53#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
54#define HNAE3_DEV_ID_50GE_RDMA 0xA224
55#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
56#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
57#define HNAE3_DEV_ID_200G_RDMA 0xA228
58#define HNAE3_DEV_ID_VF 0xA22E
59#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F
60
61#define HNAE3_CLASS_NAME_SIZE 16
62
63#define HNAE3_DEV_INITED_B 0x0
64#define HNAE3_DEV_SUPPORT_ROCE_B 0x1
65#define HNAE3_DEV_SUPPORT_DCB_B 0x2
66#define HNAE3_KNIC_CLIENT_INITED_B 0x3
67#define HNAE3_UNIC_CLIENT_INITED_B 0x4
68#define HNAE3_ROCE_CLIENT_INITED_B 0x5
69
70#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
71 BIT(HNAE3_DEV_SUPPORT_ROCE_B))
72
73#define hnae3_dev_roce_supported(hdev) \
74 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
75
76#define hnae3_dev_dcb_supported(hdev) \
77 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
78
79enum HNAE3_DEV_CAP_BITS {
80 HNAE3_DEV_SUPPORT_FD_B,
81 HNAE3_DEV_SUPPORT_GRO_B,
82 HNAE3_DEV_SUPPORT_FEC_B,
83 HNAE3_DEV_SUPPORT_UDP_GSO_B,
84 HNAE3_DEV_SUPPORT_QB_B,
85 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
86 HNAE3_DEV_SUPPORT_PTP_B,
87 HNAE3_DEV_SUPPORT_INT_QL_B,
88 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
89 HNAE3_DEV_SUPPORT_TX_PUSH_B,
90 HNAE3_DEV_SUPPORT_PHY_IMP_B,
91 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
92 HNAE3_DEV_SUPPORT_HW_PAD_B,
93 HNAE3_DEV_SUPPORT_STASH_B,
94 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
95 HNAE3_DEV_SUPPORT_PAUSE_B,
96 HNAE3_DEV_SUPPORT_RAS_IMP_B,
97 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
98 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
99 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
100 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
101 HNAE3_DEV_SUPPORT_CQ_B,
102 HNAE3_DEV_SUPPORT_FEC_STATS_B,
103 HNAE3_DEV_SUPPORT_LANE_NUM_B,
104 HNAE3_DEV_SUPPORT_WOL_B,
105 HNAE3_DEV_SUPPORT_TM_FLUSH_B,
106 HNAE3_DEV_SUPPORT_VF_FAULT_B,
107};
108
109#define hnae3_ae_dev_fd_supported(ae_dev) \
110 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
111
112#define hnae3_ae_dev_gro_supported(ae_dev) \
113 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)
114
115#define hnae3_dev_fec_supported(hdev) \
116 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
117
118#define hnae3_dev_udp_gso_supported(hdev) \
119 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
120
121#define hnae3_dev_qb_supported(hdev) \
122 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
123
124#define hnae3_dev_fd_forward_tc_supported(hdev) \
125 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
126
127#define hnae3_dev_ptp_supported(hdev) \
128 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
129
130#define hnae3_dev_int_ql_supported(hdev) \
131 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
132
133#define hnae3_dev_hw_csum_supported(hdev) \
134 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
135
136#define hnae3_dev_tx_push_supported(hdev) \
137 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
138
139#define hnae3_dev_phy_imp_supported(hdev) \
140 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
141
142#define hnae3_dev_ras_imp_supported(hdev) \
143 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
144
145#define hnae3_dev_tqp_txrx_indep_supported(hdev) \
146 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
147
148#define hnae3_dev_hw_pad_supported(hdev) \
149 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
150
151#define hnae3_dev_stash_supported(hdev) \
152 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
153
154#define hnae3_dev_pause_supported(hdev) \
155 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
156
157#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
158 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
159
160#define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
161 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
162
163#define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
164 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
165
166#define hnae3_ae_dev_cq_supported(ae_dev) \
167 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
168
169#define hnae3_ae_dev_fec_stats_supported(ae_dev) \
170 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
171
172#define hnae3_ae_dev_lane_num_supported(ae_dev) \
173 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
174
175#define hnae3_ae_dev_wol_supported(ae_dev) \
176 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
177
178#define hnae3_ae_dev_tm_flush_supported(hdev) \
179 test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)
180
181#define hnae3_ae_dev_vf_fault_supported(ae_dev) \
182 test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)
183
184enum HNAE3_PF_CAP_BITS {
185 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
186};
187#define ring_ptr_move_fw(ring, p) \
188 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
189#define ring_ptr_move_bw(ring, p) \
190 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
191
192struct hnae3_handle;
193
194struct hnae3_queue {
195 void __iomem *io_base;
196 void __iomem *mem_base;
197 struct hnae3_ae_algo *ae_algo;
198 struct hnae3_handle *handle;
199 int tqp_index; /* index in a handle */
200 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
201 u16 tx_desc_num; /* total number of tx desc */
202 u16 rx_desc_num; /* total number of rx desc */
203};
204
205struct hns3_mac_stats {
206 u64 tx_pause_cnt;
207 u64 rx_pause_cnt;
208};
209
210/* hnae3 loop mode */
211enum hnae3_loop {
212 HNAE3_LOOP_EXTERNAL,
213 HNAE3_LOOP_APP,
214 HNAE3_LOOP_SERIAL_SERDES,
215 HNAE3_LOOP_PARALLEL_SERDES,
216 HNAE3_LOOP_PHY,
217 HNAE3_LOOP_NONE,
218};
219
220enum hnae3_client_type {
221 HNAE3_CLIENT_KNIC,
222 HNAE3_CLIENT_ROCE,
223};
224
225/* mac media type */
226enum hnae3_media_type {
227 HNAE3_MEDIA_TYPE_UNKNOWN,
228 HNAE3_MEDIA_TYPE_FIBER,
229 HNAE3_MEDIA_TYPE_COPPER,
230 HNAE3_MEDIA_TYPE_BACKPLANE,
231 HNAE3_MEDIA_TYPE_NONE,
232};
233
234/* must be consistent with definition in firmware */
235enum hnae3_module_type {
236 HNAE3_MODULE_TYPE_UNKNOWN = 0x00,
237 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,
238 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,
239 HNAE3_MODULE_TYPE_AOC = 0x03,
240 HNAE3_MODULE_TYPE_CR = 0x04,
241 HNAE3_MODULE_TYPE_KR = 0x05,
242 HNAE3_MODULE_TYPE_TP = 0x06,
243};
244
245enum hnae3_fec_mode {
246 HNAE3_FEC_AUTO = 0,
247 HNAE3_FEC_BASER,
248 HNAE3_FEC_RS,
249 HNAE3_FEC_LLRS,
250 HNAE3_FEC_NONE,
251 HNAE3_FEC_USER_DEF,
252};
253
254enum hnae3_reset_notify_type {
255 HNAE3_UP_CLIENT,
256 HNAE3_DOWN_CLIENT,
257 HNAE3_INIT_CLIENT,
258 HNAE3_UNINIT_CLIENT,
259};
260
261enum hnae3_hw_error_type {
262 HNAE3_PPU_POISON_ERROR,
263 HNAE3_CMDQ_ECC_ERROR,
264 HNAE3_IMP_RD_POISON_ERROR,
265 HNAE3_ROCEE_AXI_RESP_ERROR,
266};
267
268enum hnae3_reset_type {
269 HNAE3_VF_RESET,
270 HNAE3_VF_FUNC_RESET,
271 HNAE3_VF_PF_FUNC_RESET,
272 HNAE3_VF_FULL_RESET,
273 HNAE3_FLR_RESET,
274 HNAE3_FUNC_RESET,
275 HNAE3_GLOBAL_RESET,
276 HNAE3_IMP_RESET,
277 HNAE3_NONE_RESET,
278 HNAE3_VF_EXP_RESET,
279 HNAE3_MAX_RESET,
280};
281
282enum hnae3_port_base_vlan_state {
283 HNAE3_PORT_BASE_VLAN_DISABLE,
284 HNAE3_PORT_BASE_VLAN_ENABLE,
285 HNAE3_PORT_BASE_VLAN_MODIFY,
286 HNAE3_PORT_BASE_VLAN_NOCHANGE,
287};
288
289enum hnae3_dbg_cmd {
290 HNAE3_DBG_CMD_TM_NODES,
291 HNAE3_DBG_CMD_TM_PRI,
292 HNAE3_DBG_CMD_TM_QSET,
293 HNAE3_DBG_CMD_TM_MAP,
294 HNAE3_DBG_CMD_TM_PG,
295 HNAE3_DBG_CMD_TM_PORT,
296 HNAE3_DBG_CMD_TC_SCH_INFO,
297 HNAE3_DBG_CMD_QOS_PAUSE_CFG,
298 HNAE3_DBG_CMD_QOS_PRI_MAP,
299 HNAE3_DBG_CMD_QOS_DSCP_MAP,
300 HNAE3_DBG_CMD_QOS_BUF_CFG,
301 HNAE3_DBG_CMD_DEV_INFO,
302 HNAE3_DBG_CMD_TX_BD,
303 HNAE3_DBG_CMD_RX_BD,
304 HNAE3_DBG_CMD_MAC_UC,
305 HNAE3_DBG_CMD_MAC_MC,
306 HNAE3_DBG_CMD_MNG_TBL,
307 HNAE3_DBG_CMD_LOOPBACK,
308 HNAE3_DBG_CMD_PTP_INFO,
309 HNAE3_DBG_CMD_INTERRUPT_INFO,
310 HNAE3_DBG_CMD_RESET_INFO,
311 HNAE3_DBG_CMD_IMP_INFO,
312 HNAE3_DBG_CMD_NCL_CONFIG,
313 HNAE3_DBG_CMD_REG_BIOS_COMMON,
314 HNAE3_DBG_CMD_REG_SSU,
315 HNAE3_DBG_CMD_REG_IGU_EGU,
316 HNAE3_DBG_CMD_REG_RPU,
317 HNAE3_DBG_CMD_REG_NCSI,
318 HNAE3_DBG_CMD_REG_RTC,
319 HNAE3_DBG_CMD_REG_PPP,
320 HNAE3_DBG_CMD_REG_RCB,
321 HNAE3_DBG_CMD_REG_TQP,
322 HNAE3_DBG_CMD_REG_MAC,
323 HNAE3_DBG_CMD_REG_DCB,
324 HNAE3_DBG_CMD_VLAN_CONFIG,
325 HNAE3_DBG_CMD_QUEUE_MAP,
326 HNAE3_DBG_CMD_RX_QUEUE_INFO,
327 HNAE3_DBG_CMD_TX_QUEUE_INFO,
328 HNAE3_DBG_CMD_FD_TCAM,
329 HNAE3_DBG_CMD_FD_COUNTER,
330 HNAE3_DBG_CMD_MAC_TNL_STATUS,
331 HNAE3_DBG_CMD_SERV_INFO,
332 HNAE3_DBG_CMD_UMV_INFO,
333 HNAE3_DBG_CMD_PAGE_POOL_INFO,
334 HNAE3_DBG_CMD_COAL_INFO,
335 HNAE3_DBG_CMD_UNKNOWN,
336};
337
338enum hnae3_tc_map_mode {
339 HNAE3_TC_MAP_MODE_PRIO,
340 HNAE3_TC_MAP_MODE_DSCP,
341};
342
343struct hnae3_vector_info {
344 u8 __iomem *io_addr;
345 int vector;
346};
347
348#define HNAE3_RING_TYPE_B 0
349#define HNAE3_RING_TYPE_TX 0
350#define HNAE3_RING_TYPE_RX 1
351#define HNAE3_RING_GL_IDX_S 0
352#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
353#define HNAE3_RING_GL_RX 0
354#define HNAE3_RING_GL_TX 1
355
356#define HNAE3_FW_VERSION_BYTE3_SHIFT 24
357#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
358#define HNAE3_FW_VERSION_BYTE2_SHIFT 16
359#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
360#define HNAE3_FW_VERSION_BYTE1_SHIFT 8
361#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
362#define HNAE3_FW_VERSION_BYTE0_SHIFT 0
363#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
364
365struct hnae3_ring_chain_node {
366 struct hnae3_ring_chain_node *next;
367 u32 tqp_index;
368 u32 flag;
369 u32 int_gl_idx;
370};
371
372#define HNAE3_IS_TX_RING(node) \
373 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
374
375/* device specification info from firmware */
376struct hnae3_dev_specs {
377 u32 mac_entry_num; /* number of mac-vlan table entry */
378 u32 mng_entry_num; /* number of manager table entry */
379 u32 max_tm_rate;
380 u16 rss_ind_tbl_size;
381 u16 rss_key_size;
382 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
383 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
384 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
385 u16 max_frm_size;
386 u16 max_qset_num;
387 u16 umv_size;
388 u16 mc_mac_size;
389 u32 mac_stats_num;
390 u8 tnl_num;
391 u8 hilink_version;
392};
393
394struct hnae3_client_ops {
395 int (*init_instance)(struct hnae3_handle *handle);
396 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
397 void (*link_status_change)(struct hnae3_handle *handle, bool state);
398 int (*reset_notify)(struct hnae3_handle *handle,
399 enum hnae3_reset_notify_type type);
400 void (*process_hw_error)(struct hnae3_handle *handle,
401 enum hnae3_hw_error_type);
402};
403
404#define HNAE3_CLIENT_NAME_LENGTH 16
405struct hnae3_client {
406 char name[HNAE3_CLIENT_NAME_LENGTH];
407 unsigned long state;
408 enum hnae3_client_type type;
409 const struct hnae3_client_ops *ops;
410 struct list_head node;
411};
412
413#define HNAE3_DEV_CAPS_MAX_NUM 96
414struct hnae3_ae_dev {
415 struct pci_dev *pdev;
416 const struct hnae3_ae_ops *ops;
417 struct list_head node;
418 u32 flag;
419 unsigned long hw_err_reset_req;
420 struct hnae3_dev_specs dev_specs;
421 u32 dev_version;
422 DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);
423 void *priv;
424};
425
426/* This struct defines the operation on the handle.
427 *
428 * init_ae_dev(): (mandatory)
429 * Get PF configure from pci_dev and initialize PF hardware
430 * uninit_ae_dev()
431 * Disable PF device and release PF resource
432 * register_client
433 * Register client to ae_dev
434 * unregister_client()
435 * Unregister client from ae_dev
436 * start()
437 * Enable the hardware
438 * stop()
439 * Disable the hardware
440 * start_client()
441 * Inform the hclge that client has been started
442 * stop_client()
443 * Inform the hclge that client has been stopped
444 * get_status()
445 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for
446 * non-ok
447 * get_ksettings_an_result()
448 * Get negotiation status,speed and duplex
449 * get_media_type()
450 * Get media type of MAC
451 * check_port_speed()
452 * Check target speed whether is supported
453 * adjust_link()
454 * Adjust link status
455 * set_loopback()
456 * Set loopback
457 * set_promisc_mode
458 * Set promisc mode
459 * request_update_promisc_mode
460 * request to hclge(vf) to update promisc mode
461 * set_mtu()
462 * set mtu
463 * get_pauseparam()
464 * get tx and rx of pause frame use
465 * set_pauseparam()
466 * set tx and rx of pause frame use
467 * set_autoneg()
468 * set auto autonegotiation of pause frame use
469 * get_autoneg()
470 * get auto autonegotiation of pause frame use
471 * restart_autoneg()
472 * restart autonegotiation
473 * halt_autoneg()
474 * halt/resume autonegotiation when autonegotiation on
475 * get_coalesce_usecs()
476 * get usecs to delay a TX interrupt after a packet is sent
477 * get_rx_max_coalesced_frames()
478 * get Maximum number of packets to be sent before a TX interrupt.
479 * set_coalesce_usecs()
480 * set usecs to delay a TX interrupt after a packet is sent
481 * set_coalesce_frames()
482 * set Maximum number of packets to be sent before a TX interrupt.
483 * get_mac_addr()
484 * get mac address
485 * set_mac_addr()
486 * set mac address
487 * add_uc_addr
488 * Add unicast addr to mac table
489 * rm_uc_addr
490 * Remove unicast addr from mac table
491 * set_mc_addr()
492 * Set multicast address
493 * add_mc_addr
494 * Add multicast address to mac table
495 * rm_mc_addr
496 * Remove multicast address from mac table
497 * update_stats()
498 * Update Old network device statistics
499 * get_mac_stats()
500 * get mac pause statistics including tx_cnt and rx_cnt
501 * get_ethtool_stats()
502 * Get ethtool network device statistics
503 * get_strings()
504 * Get a set of strings that describe the requested objects
505 * get_sset_count()
506 * Get number of strings that @get_strings will write
507 * update_led_status()
508 * Update the led status
509 * set_led_id()
510 * Set led id
511 * get_regs()
512 * Get regs dump
513 * get_regs_len()
514 * Get the len of the regs dump
515 * get_rss_key_size()
516 * Get rss key size
517 * get_rss()
518 * Get rss table
519 * set_rss()
520 * Set rss table
521 * get_tc_size()
522 * Get tc size of handle
523 * get_vector()
524 * Get vector number and vector information
525 * put_vector()
526 * Put the vector in hdev
527 * map_ring_to_vector()
528 * Map rings to vector
529 * unmap_ring_from_vector()
530 * Unmap rings from vector
531 * reset_queue()
532 * Reset queue
533 * get_fw_version()
534 * Get firmware version
535 * get_mdix_mode()
536 * Get media typr of phy
537 * enable_vlan_filter()
538 * Enable vlan filter
539 * set_vlan_filter()
540 * Set vlan filter config of Ports
541 * set_vf_vlan_filter()
542 * Set vlan filter config of vf
543 * enable_hw_strip_rxvtag()
544 * Enable/disable hardware strip vlan tag of packets received
545 * set_gro_en
546 * Enable/disable HW GRO
547 * add_arfs_entry
548 * Check the 5-tuples of flow, and create flow director rule
549 * get_vf_config
550 * Get the VF configuration setting by the host
551 * set_vf_link_state
552 * Set VF link status
553 * set_vf_spoofchk
554 * Enable/disable spoof check for specified vf
555 * set_vf_trust
556 * Enable/disable trust for specified vf, if the vf being trusted, then
557 * it can enable promisc mode
558 * set_vf_rate
559 * Set the max tx rate of specified vf.
560 * set_vf_mac
561 * Configure the default MAC for specified VF
562 * get_module_eeprom
563 * Get the optical module eeprom info.
564 * add_cls_flower
565 * Add clsflower rule
566 * del_cls_flower
567 * Delete clsflower rule
568 * cls_flower_active
569 * Check if any cls flower rule exist
570 * dbg_read_cmd
571 * Execute debugfs read command.
572 * set_tx_hwts_info
573 * Save information for 1588 tx packet
574 * get_rx_hwts
575 * Get 1588 rx hwstamp
576 * get_ts_info
577 * Get phc info
578 * clean_vf_config
579 * Clean residual vf info after disable sriov
580 * get_wol
581 * Get wake on lan info
582 * set_wol
583 * Config wake on lan
584 */
585struct hnae3_ae_ops {
586 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
587 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
588 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
589 enum hnae3_reset_type rst_type);
590 void (*reset_done)(struct hnae3_ae_dev *ae_dev);
591 int (*init_client_instance)(struct hnae3_client *client,
592 struct hnae3_ae_dev *ae_dev);
593 void (*uninit_client_instance)(struct hnae3_client *client,
594 struct hnae3_ae_dev *ae_dev);
595 int (*start)(struct hnae3_handle *handle);
596 void (*stop)(struct hnae3_handle *handle);
597 int (*client_start)(struct hnae3_handle *handle);
598 void (*client_stop)(struct hnae3_handle *handle);
599 int (*get_status)(struct hnae3_handle *handle);
600 void (*get_ksettings_an_result)(struct hnae3_handle *handle,
601 u8 *auto_neg, u32 *speed, u8 *duplex,
602 u32 *lane_num);
603
604 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
605 u8 duplex, u8 lane_num);
606
607 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
608 u8 *module_type);
609 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
610 void (*get_fec_stats)(struct hnae3_handle *handle,
611 struct ethtool_fec_stats *fec_stats);
612 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
613 u8 *fec_mode);
614 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
615 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
616 int (*set_loopback)(struct hnae3_handle *handle,
617 enum hnae3_loop loop_mode, bool en);
618
619 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
620 bool en_mc_pmc);
621 void (*request_update_promisc_mode)(struct hnae3_handle *handle);
622 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
623
624 void (*get_pauseparam)(struct hnae3_handle *handle,
625 u32 *auto_neg, u32 *rx_en, u32 *tx_en);
626 int (*set_pauseparam)(struct hnae3_handle *handle,
627 u32 auto_neg, u32 rx_en, u32 tx_en);
628
629 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
630 int (*get_autoneg)(struct hnae3_handle *handle);
631 int (*restart_autoneg)(struct hnae3_handle *handle);
632 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
633
634 void (*get_coalesce_usecs)(struct hnae3_handle *handle,
635 u32 *tx_usecs, u32 *rx_usecs);
636 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
637 u32 *tx_frames, u32 *rx_frames);
638 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
639 int (*set_coalesce_frames)(struct hnae3_handle *handle,
640 u32 coalesce_frames);
641 void (*get_coalesce_range)(struct hnae3_handle *handle,
642 u32 *tx_frames_low, u32 *rx_frames_low,
643 u32 *tx_frames_high, u32 *rx_frames_high,
644 u32 *tx_usecs_low, u32 *rx_usecs_low,
645 u32 *tx_usecs_high, u32 *rx_usecs_high);
646
647 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
648 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
649 bool is_first);
650 int (*do_ioctl)(struct hnae3_handle *handle,
651 struct ifreq *ifr, int cmd);
652 int (*add_uc_addr)(struct hnae3_handle *handle,
653 const unsigned char *addr);
654 int (*rm_uc_addr)(struct hnae3_handle *handle,
655 const unsigned char *addr);
656 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
657 int (*add_mc_addr)(struct hnae3_handle *handle,
658 const unsigned char *addr);
659 int (*rm_mc_addr)(struct hnae3_handle *handle,
660 const unsigned char *addr);
661 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
662 void (*update_stats)(struct hnae3_handle *handle);
663 void (*get_stats)(struct hnae3_handle *handle, u64 *data);
664 void (*get_mac_stats)(struct hnae3_handle *handle,
665 struct hns3_mac_stats *mac_stats);
666 void (*get_strings)(struct hnae3_handle *handle,
667 u32 stringset, u8 *data);
668 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
669
670 void (*get_regs)(struct hnae3_handle *handle, u32 *version,
671 void *data);
672 int (*get_regs_len)(struct hnae3_handle *handle);
673
674 u32 (*get_rss_key_size)(struct hnae3_handle *handle);
675 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
676 u8 *hfunc);
677 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
678 const u8 *key, const u8 hfunc);
679 int (*set_rss_tuple)(struct hnae3_handle *handle,
680 struct ethtool_rxnfc *cmd);
681 int (*get_rss_tuple)(struct hnae3_handle *handle,
682 struct ethtool_rxnfc *cmd);
683
684 int (*get_tc_size)(struct hnae3_handle *handle);
685
686 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
687 struct hnae3_vector_info *vector_info);
688 int (*put_vector)(struct hnae3_handle *handle, int vector_num);
689 int (*map_ring_to_vector)(struct hnae3_handle *handle,
690 int vector_num,
691 struct hnae3_ring_chain_node *vr_chain);
692 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
693 int vector_num,
694 struct hnae3_ring_chain_node *vr_chain);
695
696 int (*reset_queue)(struct hnae3_handle *handle);
697 u32 (*get_fw_version)(struct hnae3_handle *handle);
698 void (*get_mdix_mode)(struct hnae3_handle *handle,
699 u8 *tp_mdix_ctrl, u8 *tp_mdix);
700
701 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
702 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
703 u16 vlan_id, bool is_kill);
704 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
705 u16 vlan, u8 qos, __be16 proto);
706 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
707 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
708 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
709 unsigned long *addr);
710 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
711 enum hnae3_reset_type rst_type);
712 void (*get_channels)(struct hnae3_handle *handle,
713 struct ethtool_channels *ch);
714 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
715 u16 *alloc_tqps, u16 *max_rss_size);
716 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
717 bool rxfh_configured);
718 void (*get_flowctrl_adv)(struct hnae3_handle *handle,
719 u32 *flowctrl_adv);
720 int (*set_led_id)(struct hnae3_handle *handle,
721 enum ethtool_phys_id_state status);
722 void (*get_link_mode)(struct hnae3_handle *handle,
723 unsigned long *supported,
724 unsigned long *advertising);
725 int (*add_fd_entry)(struct hnae3_handle *handle,
726 struct ethtool_rxnfc *cmd);
727 int (*del_fd_entry)(struct hnae3_handle *handle,
728 struct ethtool_rxnfc *cmd);
729 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
730 struct ethtool_rxnfc *cmd);
731 int (*get_fd_rule_info)(struct hnae3_handle *handle,
732 struct ethtool_rxnfc *cmd);
733 int (*get_fd_all_rules)(struct hnae3_handle *handle,
734 struct ethtool_rxnfc *cmd, u32 *rule_locs);
735 void (*enable_fd)(struct hnae3_handle *handle, bool enable);
736 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
737 u16 flow_id, struct flow_keys *fkeys);
738 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
739 char *buf, int len);
740 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
741 bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
742 bool (*ae_dev_resetting)(struct hnae3_handle *handle);
743 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
744 int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
745 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
746 void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
747 int (*mac_connect_phy)(struct hnae3_handle *handle);
748 void (*mac_disconnect_phy)(struct hnae3_handle *handle);
749 int (*get_vf_config)(struct hnae3_handle *handle, int vf,
750 struct ifla_vf_info *ivf);
751 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
752 int link_state);
753 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
754 bool enable);
755 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
756 int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
757 int min_tx_rate, int max_tx_rate, bool force);
758 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
759 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
760 u32 len, u8 *data);
761 bool (*get_cmdq_stat)(struct hnae3_handle *handle);
762 int (*add_cls_flower)(struct hnae3_handle *handle,
763 struct flow_cls_offload *cls_flower, int tc);
764 int (*del_cls_flower)(struct hnae3_handle *handle,
765 struct flow_cls_offload *cls_flower);
766 bool (*cls_flower_active)(struct hnae3_handle *handle);
767 int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
768 struct ethtool_link_ksettings *cmd);
769 int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
770 const struct ethtool_link_ksettings *cmd);
771 bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
772 struct sk_buff *skb);
773 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
774 u32 nsec, u32 sec);
775 int (*get_ts_info)(struct hnae3_handle *handle,
776 struct ethtool_ts_info *info);
777 int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
778 u32 *status_code);
779 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
780 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,
781 u8 *tc_map_mode, u8 *priority);
782 void (*get_wol)(struct hnae3_handle *handle,
783 struct ethtool_wolinfo *wol);
784 int (*set_wol)(struct hnae3_handle *handle,
785 struct ethtool_wolinfo *wol);
786};
787
788struct hnae3_dcb_ops {
789 /* IEEE 802.1Qaz std */
790 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
791 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
792 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
793 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
794 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);
795 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);
796
797 /* DCBX configuration */
798 u8 (*getdcbx)(struct hnae3_handle *);
799 u8 (*setdcbx)(struct hnae3_handle *, u8);
800
801 int (*setup_tc)(struct hnae3_handle *handle,
802 struct tc_mqprio_qopt_offload *mqprio_qopt);
803};
804
805struct hnae3_ae_algo {
806 const struct hnae3_ae_ops *ops;
807 struct list_head node;
808 const struct pci_device_id *pdev_id_table;
809};
810
811#define HNAE3_INT_NAME_LEN 32
812#define HNAE3_ITR_COUNTDOWN_START 100
813
814#define HNAE3_MAX_TC 8
815#define HNAE3_MAX_USER_PRIO 8
816struct hnae3_tc_info {
817 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
818 u16 tqp_count[HNAE3_MAX_TC];
819 u16 tqp_offset[HNAE3_MAX_TC];
820 u8 max_tc; /* Total number of TCs */
821 u8 num_tc; /* Total number of enabled TCs */
822 bool mqprio_active;
823 bool mqprio_destroy;
824 bool dcb_ets_active;
825};
826
827#define HNAE3_MAX_DSCP 64
828#define HNAE3_PRIO_ID_INVALID 0xff
829struct hnae3_knic_private_info {
830 struct net_device *netdev; /* Set by KNIC client when init instance */
831 u16 rss_size; /* Allocated RSS queues */
832 u16 req_rss_size;
833 u16 rx_buf_len;
834 u16 num_tx_desc;
835 u16 num_rx_desc;
836 u32 tx_spare_buf_size;
837
838 struct hnae3_tc_info tc_info;
839 u8 tc_map_mode;
840 u8 dscp_app_cnt;
841 u8 dscp_prio[HNAE3_MAX_DSCP];
842
843 u16 num_tqps; /* total number of TQPs in this handle */
844 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */
845 const struct hnae3_dcb_ops *dcb_ops;
846
847 u16 int_rl_setting;
848 void __iomem *io_base;
849};
850
851struct hnae3_roce_private_info {
852 struct net_device *netdev;
853 void __iomem *roce_io_base;
854 void __iomem *roce_mem_base;
855 int base_vector;
856 int num_vectors;
857
858 /* The below attributes defined for RoCE client, hnae3 gives
859 * initial values to them, and RoCE client can modify and use
860 * them.
861 */
862 unsigned long reset_state;
863 unsigned long instance_state;
864 unsigned long state;
865};
866
867#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
868#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
869#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
870#define HNAE3_SUPPORT_VF BIT(3)
871#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
872#define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5)
873
874#define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */
875#define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */
876#define HNAE3_BPE BIT(2) /* broadcast promisc enable */
877#define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */
878#define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */
879#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
880#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
881
882enum hnae3_pflag {
883 HNAE3_PFLAG_LIMIT_PROMISC,
884 HNAE3_PFLAG_MAX
885};
886
887struct hnae3_handle {
888 struct hnae3_client *client;
889 struct pci_dev *pdev;
890 void *priv;
891 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */
892 u64 flags; /* Indicate the capabilities for this handle */
893
894 union {
895 struct net_device *netdev; /* first member */
896 struct hnae3_knic_private_info kinfo;
897 struct hnae3_roce_private_info rinfo;
898 };
899
900 u32 numa_node_mask; /* for multi-chip support */
901
902 enum hnae3_port_base_vlan_state port_base_vlan_state;
903
904 u8 netdev_flags;
905 struct dentry *hnae3_dbgfs;
906 /* protects concurrent contention between debugfs commands */
907 struct mutex dbgfs_lock;
908 char **dbgfs_buf;
909
910 /* Network interface message level enabled bits */
911 u32 msg_enable;
912
913 unsigned long supported_pflags;
914 unsigned long priv_flags;
915};
916
917#define hnae3_set_field(origin, mask, shift, val) \
918 do { \
919 (origin) &= (~(mask)); \
920 (origin) |= ((val) << (shift)) & (mask); \
921 } while (0)
922#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
923
924#define hnae3_set_bit(origin, shift, val) \
925 hnae3_set_field(origin, 0x1 << (shift), shift, val)
926#define hnae3_get_bit(origin, shift) \
927 hnae3_get_field(origin, 0x1 << (shift), shift)
928
929#define HNAE3_FORMAT_MAC_ADDR_LEN 18
930#define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0
931#define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4
932#define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5
933
934static inline void hnae3_format_mac_addr(char *format_mac_addr,
935 const u8 *mac_addr)
936{
937 snprintf(buf: format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, fmt: "%02x:**:**:**:%02x:%02x",
938 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
939 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
940 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
941}
942
943int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
944void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
945
946void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
947void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
948void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
949
950void hnae3_unregister_client(struct hnae3_client *client);
951int hnae3_register_client(struct hnae3_client *client);
952
953void hnae3_set_client_init_flag(struct hnae3_client *client,
954 struct hnae3_ae_dev *ae_dev,
955 unsigned int inited);
956#endif
957

source code of linux/drivers/net/ethernet/hisilicon/hns3/hnae3.h