| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* Copyright (c) 2018-2019 Hisilicon Limited. */ |
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| 3 | |
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| 4 | #ifndef __HCLGE_DEBUGFS_H |
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| 5 | #define __HCLGE_DEBUGFS_H |
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| 6 | |
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| 7 | #include <linux/etherdevice.h> |
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| 8 | #include "hclge_cmd.h" |
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| 9 | |
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| 10 | #define HCLGE_DBG_MNG_TBL_MAX 64 |
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| 11 | |
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| 12 | #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) |
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| 13 | #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) |
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| 14 | #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) |
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| 15 | #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) |
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| 16 | #define HCLGE_DBG_MNG_DROP_B BIT(13) |
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| 17 | #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF |
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| 18 | #define HCLGE_DBG_MNG_PF_ID 0x0007 |
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| 19 | #define HCLGE_DBG_MNG_VF_ID 0x00FF |
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| 20 | |
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| 21 | /* Get DFX BD number offset */ |
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| 22 | #define HCLGE_DBG_DFX_BIOS_OFFSET 1 |
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| 23 | #define HCLGE_DBG_DFX_SSU_0_OFFSET 2 |
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| 24 | #define HCLGE_DBG_DFX_SSU_1_OFFSET 3 |
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| 25 | #define HCLGE_DBG_DFX_IGU_OFFSET 4 |
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| 26 | #define HCLGE_DBG_DFX_RPU_0_OFFSET 5 |
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| 27 | |
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| 28 | #define HCLGE_DBG_DFX_RPU_1_OFFSET 6 |
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| 29 | #define HCLGE_DBG_DFX_NCSI_OFFSET 7 |
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| 30 | #define HCLGE_DBG_DFX_RTC_OFFSET 8 |
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| 31 | #define HCLGE_DBG_DFX_PPP_OFFSET 9 |
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| 32 | #define HCLGE_DBG_DFX_RCB_OFFSET 10 |
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| 33 | #define HCLGE_DBG_DFX_TQP_OFFSET 11 |
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| 34 | |
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| 35 | #define HCLGE_DBG_DFX_SSU_2_OFFSET 12 |
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| 36 | |
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| 37 | struct hclge_qos_pri_map_cmd { |
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| 38 | u8 pri0_tc : 4, |
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| 39 | pri1_tc : 4; |
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| 40 | u8 pri2_tc : 4, |
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| 41 | pri3_tc : 4; |
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| 42 | u8 pri4_tc : 4, |
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| 43 | pri5_tc : 4; |
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| 44 | u8 pri6_tc : 4, |
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| 45 | pri7_tc : 4; |
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| 46 | u8 vlan_pri : 4, |
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| 47 | rev : 4; |
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| 48 | }; |
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| 49 | |
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| 50 | struct hclge_dbg_bitmap_cmd { |
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| 51 | union { |
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| 52 | u8 bitmap; |
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| 53 | struct { |
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| 54 | u8 bit0 : 1, |
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| 55 | bit1 : 1, |
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| 56 | bit2 : 1, |
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| 57 | bit3 : 1, |
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| 58 | bit4 : 1, |
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| 59 | bit5 : 1, |
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| 60 | bit6 : 1, |
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| 61 | bit7 : 1; |
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| 62 | }; |
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| 63 | }; |
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| 64 | }; |
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| 65 | |
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| 66 | struct hclge_dbg_reg_common_msg { |
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| 67 | int msg_num; |
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| 68 | int offset; |
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| 69 | enum hclge_opcode_type cmd; |
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| 70 | }; |
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| 71 | |
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| 72 | struct hclge_dbg_tcam_msg { |
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| 73 | u8 stage; |
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| 74 | u32 loc; |
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| 75 | }; |
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| 76 | |
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| 77 | #define HCLGE_DBG_MAX_DFX_MSG_LEN 60 |
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| 78 | struct hclge_dbg_dfx_message { |
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| 79 | int flag; |
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| 80 | char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; |
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| 81 | }; |
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| 82 | |
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| 83 | #define HCLGE_DBG_MAC_REG_TYPE_LEN 32 |
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| 84 | struct hclge_dbg_reg_type_info { |
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| 85 | enum hnae3_dbg_cmd cmd; |
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| 86 | const struct hclge_dbg_dfx_message *dfx_msg; |
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| 87 | struct hclge_dbg_reg_common_msg reg_msg; |
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| 88 | }; |
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| 89 | |
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| 90 | struct hclge_dbg_func { |
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| 91 | enum hnae3_dbg_cmd cmd; |
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| 92 | int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len); |
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| 93 | int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd, |
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| 94 | char *buf, int len); |
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| 95 | }; |
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| 96 | |
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| 97 | struct hclge_dbg_status_dfx_info { |
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| 98 | u32 offset; |
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| 99 | char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; |
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| 100 | }; |
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| 101 | |
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| 102 | static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { |
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| 103 | {false, "Reserved" }, |
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| 104 | {true, "BP_CPU_STATE" }, |
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| 105 | {true, "DFX_MSIX_INFO_NIC_0" }, |
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| 106 | {true, "DFX_MSIX_INFO_NIC_1" }, |
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| 107 | {true, "DFX_MSIX_INFO_NIC_2" }, |
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| 108 | {true, "DFX_MSIX_INFO_NIC_3" }, |
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| 109 | |
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| 110 | {true, "DFX_MSIX_INFO_ROC_0" }, |
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| 111 | {true, "DFX_MSIX_INFO_ROC_1" }, |
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| 112 | {true, "DFX_MSIX_INFO_ROC_2" }, |
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| 113 | {true, "DFX_MSIX_INFO_ROC_3" }, |
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| 114 | {false, "Reserved" }, |
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| 115 | {false, "Reserved" }, |
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| 116 | }; |
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| 117 | |
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| 118 | static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { |
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| 119 | {false, "Reserved" }, |
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| 120 | {true, "SSU_ETS_PORT_STATUS" }, |
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| 121 | {true, "SSU_ETS_TCG_STATUS" }, |
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| 122 | {false, "Reserved" }, |
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| 123 | {false, "Reserved" }, |
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| 124 | {true, "SSU_BP_STATUS_0" }, |
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| 125 | |
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| 126 | {true, "SSU_BP_STATUS_1" }, |
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| 127 | {true, "SSU_BP_STATUS_2" }, |
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| 128 | {true, "SSU_BP_STATUS_3" }, |
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| 129 | {true, "SSU_BP_STATUS_4" }, |
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| 130 | {true, "SSU_BP_STATUS_5" }, |
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| 131 | {true, "SSU_MAC_TX_PFC_IND" }, |
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| 132 | |
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| 133 | {true, "MAC_SSU_RX_PFC_IND" }, |
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| 134 | {true, "BTMP_AGEING_ST_B0" }, |
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| 135 | {true, "BTMP_AGEING_ST_B1" }, |
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| 136 | {true, "BTMP_AGEING_ST_B2" }, |
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| 137 | {false, "Reserved" }, |
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| 138 | {false, "Reserved" }, |
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| 139 | |
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| 140 | {true, "FULL_DROP_NUM" }, |
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| 141 | {true, "PART_DROP_NUM" }, |
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| 142 | {true, "PPP_KEY_DROP_NUM" }, |
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| 143 | {true, "PPP_RLT_DROP_NUM" }, |
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| 144 | {true, "LO_PRI_UNICAST_RLT_DROP_NUM" }, |
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| 145 | {true, "HI_PRI_MULTICAST_RLT_DROP_NUM" }, |
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| 146 | |
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| 147 | {true, "LO_PRI_MULTICAST_RLT_DROP_NUM" }, |
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| 148 | {true, "NCSI_PACKET_CURR_BUFFER_CNT" }, |
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| 149 | {true, "BTMP_AGEING_RLS_CNT_BANK0" }, |
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| 150 | {true, "BTMP_AGEING_RLS_CNT_BANK1" }, |
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| 151 | {true, "BTMP_AGEING_RLS_CNT_BANK2" }, |
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| 152 | {true, "SSU_MB_RD_RLT_DROP_CNT" }, |
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| 153 | |
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| 154 | {true, "SSU_PPP_MAC_KEY_NUM_L" }, |
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| 155 | {true, "SSU_PPP_MAC_KEY_NUM_H" }, |
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| 156 | {true, "SSU_PPP_HOST_KEY_NUM_L" }, |
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| 157 | {true, "SSU_PPP_HOST_KEY_NUM_H" }, |
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| 158 | {true, "PPP_SSU_MAC_RLT_NUM_L" }, |
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| 159 | {true, "PPP_SSU_MAC_RLT_NUM_H" }, |
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| 160 | |
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| 161 | {true, "PPP_SSU_HOST_RLT_NUM_L" }, |
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| 162 | {true, "PPP_SSU_HOST_RLT_NUM_H" }, |
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| 163 | {true, "NCSI_RX_PACKET_IN_CNT_L" }, |
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| 164 | {true, "NCSI_RX_PACKET_IN_CNT_H" }, |
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| 165 | {true, "NCSI_TX_PACKET_OUT_CNT_L" }, |
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| 166 | {true, "NCSI_TX_PACKET_OUT_CNT_H" }, |
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| 167 | |
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| 168 | {true, "SSU_KEY_DROP_NUM" }, |
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| 169 | {true, "MB_UNCOPY_NUM" }, |
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| 170 | {true, "RX_OQ_DROP_PKT_CNT" }, |
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| 171 | {true, "TX_OQ_DROP_PKT_CNT" }, |
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| 172 | {true, "BANK_UNBALANCE_DROP_CNT" }, |
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| 173 | {true, "BANK_UNBALANCE_RX_DROP_CNT" }, |
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| 174 | |
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| 175 | {true, "NIC_L2_ERR_DROP_PKT_CNT" }, |
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| 176 | {true, "ROC_L2_ERR_DROP_PKT_CNT" }, |
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| 177 | {true, "NIC_L2_ERR_DROP_PKT_CNT_RX" }, |
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| 178 | {true, "ROC_L2_ERR_DROP_PKT_CNT_RX" }, |
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| 179 | {true, "RX_OQ_GLB_DROP_PKT_CNT" }, |
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| 180 | {false, "Reserved" }, |
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| 181 | |
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| 182 | {true, "LO_PRI_UNICAST_CUR_CNT" }, |
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| 183 | {true, "HI_PRI_MULTICAST_CUR_CNT" }, |
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| 184 | {true, "LO_PRI_MULTICAST_CUR_CNT" }, |
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| 185 | {false, "Reserved" }, |
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| 186 | {false, "Reserved" }, |
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| 187 | {false, "Reserved" }, |
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| 188 | }; |
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| 189 | |
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| 190 | static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { |
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| 191 | {true, "prt_id" }, |
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| 192 | {true, "PACKET_TC_CURR_BUFFER_CNT_0" }, |
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| 193 | {true, "PACKET_TC_CURR_BUFFER_CNT_1" }, |
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| 194 | {true, "PACKET_TC_CURR_BUFFER_CNT_2" }, |
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| 195 | {true, "PACKET_TC_CURR_BUFFER_CNT_3" }, |
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| 196 | {true, "PACKET_TC_CURR_BUFFER_CNT_4" }, |
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| 197 | |
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| 198 | {true, "PACKET_TC_CURR_BUFFER_CNT_5" }, |
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| 199 | {true, "PACKET_TC_CURR_BUFFER_CNT_6" }, |
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| 200 | {true, "PACKET_TC_CURR_BUFFER_CNT_7" }, |
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| 201 | {true, "PACKET_CURR_BUFFER_CNT" }, |
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| 202 | {false, "Reserved" }, |
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| 203 | {false, "Reserved" }, |
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| 204 | |
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| 205 | {true, "RX_PACKET_IN_CNT_L" }, |
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| 206 | {true, "RX_PACKET_IN_CNT_H" }, |
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| 207 | {true, "RX_PACKET_OUT_CNT_L" }, |
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| 208 | {true, "RX_PACKET_OUT_CNT_H" }, |
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| 209 | {true, "TX_PACKET_IN_CNT_L" }, |
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| 210 | {true, "TX_PACKET_IN_CNT_H" }, |
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| 211 | |
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| 212 | {true, "TX_PACKET_OUT_CNT_L" }, |
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| 213 | {true, "TX_PACKET_OUT_CNT_H" }, |
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| 214 | {true, "ROC_RX_PACKET_IN_CNT_L" }, |
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| 215 | {true, "ROC_RX_PACKET_IN_CNT_H" }, |
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| 216 | {true, "ROC_TX_PACKET_OUT_CNT_L" }, |
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| 217 | {true, "ROC_TX_PACKET_OUT_CNT_H" }, |
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| 218 | |
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| 219 | {true, "RX_PACKET_TC_IN_CNT_0_L" }, |
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| 220 | {true, "RX_PACKET_TC_IN_CNT_0_H" }, |
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| 221 | {true, "RX_PACKET_TC_IN_CNT_1_L" }, |
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| 222 | {true, "RX_PACKET_TC_IN_CNT_1_H" }, |
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| 223 | {true, "RX_PACKET_TC_IN_CNT_2_L" }, |
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| 224 | {true, "RX_PACKET_TC_IN_CNT_2_H" }, |
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| 225 | |
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| 226 | {true, "RX_PACKET_TC_IN_CNT_3_L" }, |
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| 227 | {true, "RX_PACKET_TC_IN_CNT_3_H" }, |
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| 228 | {true, "RX_PACKET_TC_IN_CNT_4_L" }, |
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| 229 | {true, "RX_PACKET_TC_IN_CNT_4_H" }, |
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| 230 | {true, "RX_PACKET_TC_IN_CNT_5_L" }, |
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| 231 | {true, "RX_PACKET_TC_IN_CNT_5_H" }, |
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| 232 | |
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| 233 | {true, "RX_PACKET_TC_IN_CNT_6_L" }, |
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| 234 | {true, "RX_PACKET_TC_IN_CNT_6_H" }, |
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| 235 | {true, "RX_PACKET_TC_IN_CNT_7_L" }, |
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| 236 | {true, "RX_PACKET_TC_IN_CNT_7_H" }, |
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| 237 | {true, "RX_PACKET_TC_OUT_CNT_0_L" }, |
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| 238 | {true, "RX_PACKET_TC_OUT_CNT_0_H" }, |
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| 239 | |
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| 240 | {true, "RX_PACKET_TC_OUT_CNT_1_L" }, |
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| 241 | {true, "RX_PACKET_TC_OUT_CNT_1_H" }, |
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| 242 | {true, "RX_PACKET_TC_OUT_CNT_2_L" }, |
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| 243 | {true, "RX_PACKET_TC_OUT_CNT_2_H" }, |
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| 244 | {true, "RX_PACKET_TC_OUT_CNT_3_L" }, |
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| 245 | {true, "RX_PACKET_TC_OUT_CNT_3_H" }, |
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| 246 | |
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| 247 | {true, "RX_PACKET_TC_OUT_CNT_4_L" }, |
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| 248 | {true, "RX_PACKET_TC_OUT_CNT_4_H" }, |
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| 249 | {true, "RX_PACKET_TC_OUT_CNT_5_L" }, |
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| 250 | {true, "RX_PACKET_TC_OUT_CNT_5_H" }, |
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| 251 | {true, "RX_PACKET_TC_OUT_CNT_6_L" }, |
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| 252 | {true, "RX_PACKET_TC_OUT_CNT_6_H" }, |
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| 253 | |
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| 254 | {true, "RX_PACKET_TC_OUT_CNT_7_L" }, |
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| 255 | {true, "RX_PACKET_TC_OUT_CNT_7_H" }, |
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| 256 | {true, "TX_PACKET_TC_IN_CNT_0_L" }, |
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| 257 | {true, "TX_PACKET_TC_IN_CNT_0_H" }, |
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| 258 | {true, "TX_PACKET_TC_IN_CNT_1_L" }, |
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| 259 | {true, "TX_PACKET_TC_IN_CNT_1_H" }, |
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| 260 | |
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| 261 | {true, "TX_PACKET_TC_IN_CNT_2_L" }, |
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| 262 | {true, "TX_PACKET_TC_IN_CNT_2_H" }, |
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| 263 | {true, "TX_PACKET_TC_IN_CNT_3_L" }, |
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| 264 | {true, "TX_PACKET_TC_IN_CNT_3_H" }, |
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| 265 | {true, "TX_PACKET_TC_IN_CNT_4_L" }, |
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| 266 | {true, "TX_PACKET_TC_IN_CNT_4_H" }, |
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| 267 | |
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| 268 | {true, "TX_PACKET_TC_IN_CNT_5_L" }, |
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| 269 | {true, "TX_PACKET_TC_IN_CNT_5_H" }, |
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| 270 | {true, "TX_PACKET_TC_IN_CNT_6_L" }, |
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| 271 | {true, "TX_PACKET_TC_IN_CNT_6_H" }, |
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| 272 | {true, "TX_PACKET_TC_IN_CNT_7_L" }, |
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| 273 | {true, "TX_PACKET_TC_IN_CNT_7_H" }, |
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| 274 | |
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| 275 | {true, "TX_PACKET_TC_OUT_CNT_0_L" }, |
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| 276 | {true, "TX_PACKET_TC_OUT_CNT_0_H" }, |
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| 277 | {true, "TX_PACKET_TC_OUT_CNT_1_L" }, |
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| 278 | {true, "TX_PACKET_TC_OUT_CNT_1_H" }, |
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| 279 | {true, "TX_PACKET_TC_OUT_CNT_2_L" }, |
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| 280 | {true, "TX_PACKET_TC_OUT_CNT_2_H" }, |
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| 281 | |
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| 282 | {true, "TX_PACKET_TC_OUT_CNT_3_L" }, |
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| 283 | {true, "TX_PACKET_TC_OUT_CNT_3_H" }, |
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| 284 | {true, "TX_PACKET_TC_OUT_CNT_4_L" }, |
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| 285 | {true, "TX_PACKET_TC_OUT_CNT_4_H" }, |
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| 286 | {true, "TX_PACKET_TC_OUT_CNT_5_L" }, |
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| 287 | {true, "TX_PACKET_TC_OUT_CNT_5_H" }, |
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| 288 | |
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| 289 | {true, "TX_PACKET_TC_OUT_CNT_6_L" }, |
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| 290 | {true, "TX_PACKET_TC_OUT_CNT_6_H" }, |
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| 291 | {true, "TX_PACKET_TC_OUT_CNT_7_L" }, |
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| 292 | {true, "TX_PACKET_TC_OUT_CNT_7_H" }, |
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| 293 | {false, "Reserved" }, |
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| 294 | {false, "Reserved" }, |
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| 295 | }; |
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| 296 | |
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| 297 | static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { |
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| 298 | {true, "OQ_INDEX" }, |
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| 299 | {true, "QUEUE_CNT" }, |
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| 300 | {false, "Reserved" }, |
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| 301 | {false, "Reserved" }, |
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| 302 | {false, "Reserved" }, |
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| 303 | {false, "Reserved" }, |
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| 304 | }; |
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| 305 | |
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| 306 | static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { |
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| 307 | {true, "prt_id" }, |
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| 308 | {true, "IGU_RX_ERR_PKT" }, |
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| 309 | {true, "IGU_RX_NO_SOF_PKT" }, |
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| 310 | {true, "EGU_TX_1588_SHORT_PKT" }, |
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| 311 | {true, "EGU_TX_1588_PKT" }, |
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| 312 | {true, "EGU_TX_ERR_PKT" }, |
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| 313 | |
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| 314 | {true, "IGU_RX_OUT_L2_PKT" }, |
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| 315 | {true, "IGU_RX_OUT_L3_PKT" }, |
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| 316 | {true, "IGU_RX_OUT_L4_PKT" }, |
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| 317 | {true, "IGU_RX_IN_L2_PKT" }, |
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| 318 | {true, "IGU_RX_IN_L3_PKT" }, |
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| 319 | {true, "IGU_RX_IN_L4_PKT" }, |
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| 320 | |
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| 321 | {true, "IGU_RX_EL3E_PKT" }, |
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| 322 | {true, "IGU_RX_EL4E_PKT" }, |
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| 323 | {true, "IGU_RX_L3E_PKT" }, |
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| 324 | {true, "IGU_RX_L4E_PKT" }, |
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| 325 | {true, "IGU_RX_ROCEE_PKT" }, |
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| 326 | {true, "IGU_RX_OUT_UDP0_PKT" }, |
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| 327 | |
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| 328 | {true, "IGU_RX_IN_UDP0_PKT" }, |
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| 329 | {true, "IGU_MC_CAR_DROP_PKT_L" }, |
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| 330 | {true, "IGU_MC_CAR_DROP_PKT_H" }, |
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| 331 | {true, "IGU_BC_CAR_DROP_PKT_L" }, |
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| 332 | {true, "IGU_BC_CAR_DROP_PKT_H" }, |
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| 333 | {false, "Reserved" }, |
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| 334 | |
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| 335 | {true, "IGU_RX_OVERSIZE_PKT_L" }, |
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| 336 | {true, "IGU_RX_OVERSIZE_PKT_H" }, |
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| 337 | {true, "IGU_RX_UNDERSIZE_PKT_L" }, |
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| 338 | {true, "IGU_RX_UNDERSIZE_PKT_H" }, |
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| 339 | {true, "IGU_RX_OUT_ALL_PKT_L" }, |
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| 340 | {true, "IGU_RX_OUT_ALL_PKT_H" }, |
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| 341 | |
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| 342 | {true, "IGU_TX_OUT_ALL_PKT_L" }, |
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| 343 | {true, "IGU_TX_OUT_ALL_PKT_H" }, |
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| 344 | {true, "IGU_RX_UNI_PKT_L" }, |
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| 345 | {true, "IGU_RX_UNI_PKT_H" }, |
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| 346 | {true, "IGU_RX_MULTI_PKT_L" }, |
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| 347 | {true, "IGU_RX_MULTI_PKT_H" }, |
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| 348 | |
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| 349 | {true, "IGU_RX_BROAD_PKT_L" }, |
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| 350 | {true, "IGU_RX_BROAD_PKT_H" }, |
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| 351 | {true, "EGU_TX_OUT_ALL_PKT_L" }, |
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| 352 | {true, "EGU_TX_OUT_ALL_PKT_H" }, |
|---|
| 353 | {true, "EGU_TX_UNI_PKT_L" }, |
|---|
| 354 | {true, "EGU_TX_UNI_PKT_H" }, |
|---|
| 355 | |
|---|
| 356 | {true, "EGU_TX_MULTI_PKT_L" }, |
|---|
| 357 | {true, "EGU_TX_MULTI_PKT_H" }, |
|---|
| 358 | {true, "EGU_TX_BROAD_PKT_L" }, |
|---|
| 359 | {true, "EGU_TX_BROAD_PKT_H" }, |
|---|
| 360 | {true, "IGU_TX_KEY_NUM_L" }, |
|---|
| 361 | {true, "IGU_TX_KEY_NUM_H" }, |
|---|
| 362 | |
|---|
| 363 | {true, "IGU_RX_NON_TUN_PKT_L" }, |
|---|
| 364 | {true, "IGU_RX_NON_TUN_PKT_H" }, |
|---|
| 365 | {true, "IGU_RX_TUN_PKT_L" }, |
|---|
| 366 | {true, "IGU_RX_TUN_PKT_H" }, |
|---|
| 367 | {false, "Reserved" }, |
|---|
| 368 | {false, "Reserved" }, |
|---|
| 369 | }; |
|---|
| 370 | |
|---|
| 371 | static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { |
|---|
| 372 | {true, "tc_queue_num" }, |
|---|
| 373 | {true, "FSM_DFX_ST0" }, |
|---|
| 374 | {true, "FSM_DFX_ST1" }, |
|---|
| 375 | {true, "RPU_RX_PKT_DROP_CNT" }, |
|---|
| 376 | {true, "BUF_WAIT_TIMEOUT" }, |
|---|
| 377 | {true, "BUF_WAIT_TIMEOUT_QID" }, |
|---|
| 378 | }; |
|---|
| 379 | |
|---|
| 380 | static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { |
|---|
| 381 | {false, "Reserved" }, |
|---|
| 382 | {true, "FIFO_DFX_ST0" }, |
|---|
| 383 | {true, "FIFO_DFX_ST1" }, |
|---|
| 384 | {true, "FIFO_DFX_ST2" }, |
|---|
| 385 | {true, "FIFO_DFX_ST3" }, |
|---|
| 386 | {true, "FIFO_DFX_ST4" }, |
|---|
| 387 | |
|---|
| 388 | {true, "FIFO_DFX_ST5" }, |
|---|
| 389 | {false, "Reserved" }, |
|---|
| 390 | {false, "Reserved" }, |
|---|
| 391 | {false, "Reserved" }, |
|---|
| 392 | {false, "Reserved" }, |
|---|
| 393 | {false, "Reserved" }, |
|---|
| 394 | }; |
|---|
| 395 | |
|---|
| 396 | static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { |
|---|
| 397 | {false, "Reserved" }, |
|---|
| 398 | {true, "NCSI_EGU_TX_FIFO_STS" }, |
|---|
| 399 | {true, "NCSI_PAUSE_STATUS" }, |
|---|
| 400 | {true, "NCSI_RX_CTRL_DMAC_ERR_CNT" }, |
|---|
| 401 | {true, "NCSI_RX_CTRL_SMAC_ERR_CNT" }, |
|---|
| 402 | {true, "NCSI_RX_CTRL_CKS_ERR_CNT" }, |
|---|
| 403 | |
|---|
| 404 | {true, "NCSI_RX_CTRL_PKT_CNT" }, |
|---|
| 405 | {true, "NCSI_RX_PT_DMAC_ERR_CNT" }, |
|---|
| 406 | {true, "NCSI_RX_PT_SMAC_ERR_CNT" }, |
|---|
| 407 | {true, "NCSI_RX_PT_PKT_CNT" }, |
|---|
| 408 | {true, "NCSI_RX_FCS_ERR_CNT" }, |
|---|
| 409 | {true, "NCSI_TX_CTRL_DMAC_ERR_CNT" }, |
|---|
| 410 | |
|---|
| 411 | {true, "NCSI_TX_CTRL_SMAC_ERR_CNT" }, |
|---|
| 412 | {true, "NCSI_TX_CTRL_PKT_CNT" }, |
|---|
| 413 | {true, "NCSI_TX_PT_DMAC_ERR_CNT" }, |
|---|
| 414 | {true, "NCSI_TX_PT_SMAC_ERR_CNT" }, |
|---|
| 415 | {true, "NCSI_TX_PT_PKT_CNT" }, |
|---|
| 416 | {true, "NCSI_TX_PT_PKT_TRUNC_CNT" }, |
|---|
| 417 | |
|---|
| 418 | {true, "NCSI_TX_PT_PKT_ERR_CNT" }, |
|---|
| 419 | {true, "NCSI_TX_CTRL_PKT_ERR_CNT" }, |
|---|
| 420 | {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT" }, |
|---|
| 421 | {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT" }, |
|---|
| 422 | {false, "Reserved" }, |
|---|
| 423 | {false, "Reserved" }, |
|---|
| 424 | |
|---|
| 425 | {true, "NCSI_MAC_RX_OCTETS_OK" }, |
|---|
| 426 | {true, "NCSI_MAC_RX_OCTETS_BAD" }, |
|---|
| 427 | {true, "NCSI_MAC_RX_UC_PKTS" }, |
|---|
| 428 | {true, "NCSI_MAC_RX_MC_PKTS" }, |
|---|
| 429 | {true, "NCSI_MAC_RX_BC_PKTS" }, |
|---|
| 430 | {true, "NCSI_MAC_RX_PKTS_64OCTETS" }, |
|---|
| 431 | |
|---|
| 432 | {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS" }, |
|---|
| 433 | {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS" }, |
|---|
| 434 | {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS" }, |
|---|
| 435 | {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS" }, |
|---|
| 436 | {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS" }, |
|---|
| 437 | {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS" }, |
|---|
| 438 | |
|---|
| 439 | {true, "NCSI_MAC_RX_FCS_ERRORS" }, |
|---|
| 440 | {true, "NCSI_MAC_RX_LONG_ERRORS" }, |
|---|
| 441 | {true, "NCSI_MAC_RX_JABBER_ERRORS" }, |
|---|
| 442 | {true, "NCSI_MAC_RX_RUNT_ERR_CNT" }, |
|---|
| 443 | {true, "NCSI_MAC_RX_SHORT_ERR_CNT" }, |
|---|
| 444 | {true, "NCSI_MAC_RX_FILT_PKT_CNT" }, |
|---|
| 445 | |
|---|
| 446 | {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT" }, |
|---|
| 447 | {true, "NCSI_MAC_TX_OCTETS_OK" }, |
|---|
| 448 | {true, "NCSI_MAC_TX_OCTETS_BAD" }, |
|---|
| 449 | {true, "NCSI_MAC_TX_UC_PKTS" }, |
|---|
| 450 | {true, "NCSI_MAC_TX_MC_PKTS" }, |
|---|
| 451 | {true, "NCSI_MAC_TX_BC_PKTS" }, |
|---|
| 452 | |
|---|
| 453 | {true, "NCSI_MAC_TX_PKTS_64OCTETS" }, |
|---|
| 454 | {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS" }, |
|---|
| 455 | {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS" }, |
|---|
| 456 | {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS" }, |
|---|
| 457 | {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS" }, |
|---|
| 458 | {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS" }, |
|---|
| 459 | |
|---|
| 460 | {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS" }, |
|---|
| 461 | {true, "NCSI_MAC_TX_UNDERRUN" }, |
|---|
| 462 | {true, "NCSI_MAC_TX_CRC_ERROR" }, |
|---|
| 463 | {true, "NCSI_MAC_TX_PAUSE_FRAMES" }, |
|---|
| 464 | {true, "NCSI_MAC_RX_PAD_PKTS" }, |
|---|
| 465 | {true, "NCSI_MAC_RX_PAUSE_FRAMES" }, |
|---|
| 466 | }; |
|---|
| 467 | |
|---|
| 468 | static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { |
|---|
| 469 | {false, "Reserved" }, |
|---|
| 470 | {true, "LGE_IGU_AFIFO_DFX_0" }, |
|---|
| 471 | {true, "LGE_IGU_AFIFO_DFX_1" }, |
|---|
| 472 | {true, "LGE_IGU_AFIFO_DFX_2" }, |
|---|
| 473 | {true, "LGE_IGU_AFIFO_DFX_3" }, |
|---|
| 474 | {true, "LGE_IGU_AFIFO_DFX_4" }, |
|---|
| 475 | |
|---|
| 476 | {true, "LGE_IGU_AFIFO_DFX_5" }, |
|---|
| 477 | {true, "LGE_IGU_AFIFO_DFX_6" }, |
|---|
| 478 | {true, "LGE_IGU_AFIFO_DFX_7" }, |
|---|
| 479 | {true, "LGE_EGU_AFIFO_DFX_0" }, |
|---|
| 480 | {true, "LGE_EGU_AFIFO_DFX_1" }, |
|---|
| 481 | {true, "LGE_EGU_AFIFO_DFX_2" }, |
|---|
| 482 | |
|---|
| 483 | {true, "LGE_EGU_AFIFO_DFX_3" }, |
|---|
| 484 | {true, "LGE_EGU_AFIFO_DFX_4" }, |
|---|
| 485 | {true, "LGE_EGU_AFIFO_DFX_5" }, |
|---|
| 486 | {true, "LGE_EGU_AFIFO_DFX_6" }, |
|---|
| 487 | {true, "LGE_EGU_AFIFO_DFX_7" }, |
|---|
| 488 | {true, "CGE_IGU_AFIFO_DFX_0" }, |
|---|
| 489 | |
|---|
| 490 | {true, "CGE_IGU_AFIFO_DFX_1" }, |
|---|
| 491 | {true, "CGE_EGU_AFIFO_DFX_0" }, |
|---|
| 492 | {true, "CGE_EGU_AFIFO_DFX_1" }, |
|---|
| 493 | {false, "Reserved" }, |
|---|
| 494 | {false, "Reserved" }, |
|---|
| 495 | {false, "Reserved" }, |
|---|
| 496 | }; |
|---|
| 497 | |
|---|
| 498 | static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { |
|---|
| 499 | {false, "Reserved" }, |
|---|
| 500 | {true, "DROP_FROM_PRT_PKT_CNT" }, |
|---|
| 501 | {true, "DROP_FROM_HOST_PKT_CNT" }, |
|---|
| 502 | {true, "DROP_TX_VLAN_PROC_CNT" }, |
|---|
| 503 | {true, "DROP_MNG_CNT" }, |
|---|
| 504 | {true, "DROP_FD_CNT" }, |
|---|
| 505 | |
|---|
| 506 | {true, "DROP_NO_DST_CNT" }, |
|---|
| 507 | {true, "DROP_MC_MBID_FULL_CNT" }, |
|---|
| 508 | {true, "DROP_SC_FILTERED" }, |
|---|
| 509 | {true, "PPP_MC_DROP_PKT_CNT" }, |
|---|
| 510 | {true, "DROP_PT_CNT" }, |
|---|
| 511 | {true, "DROP_MAC_ANTI_SPOOF_CNT" }, |
|---|
| 512 | |
|---|
| 513 | {true, "DROP_IG_VFV_CNT" }, |
|---|
| 514 | {true, "DROP_IG_PRTV_CNT" }, |
|---|
| 515 | {true, "DROP_CNM_PFC_PAUSE_CNT" }, |
|---|
| 516 | {true, "DROP_TORUS_TC_CNT" }, |
|---|
| 517 | {true, "DROP_TORUS_LPBK_CNT" }, |
|---|
| 518 | {true, "PPP_HFS_STS" }, |
|---|
| 519 | |
|---|
| 520 | {true, "PPP_MC_RSLT_STS" }, |
|---|
| 521 | {true, "PPP_P3U_STS" }, |
|---|
| 522 | {true, "PPP_RSLT_DESCR_STS" }, |
|---|
| 523 | {true, "PPP_UMV_STS_0" }, |
|---|
| 524 | {true, "PPP_UMV_STS_1" }, |
|---|
| 525 | {true, "PPP_VFV_STS" }, |
|---|
| 526 | |
|---|
| 527 | {true, "PPP_GRO_KEY_CNT" }, |
|---|
| 528 | {true, "PPP_GRO_INFO_CNT" }, |
|---|
| 529 | {true, "PPP_GRO_DROP_CNT" }, |
|---|
| 530 | {true, "PPP_GRO_OUT_CNT" }, |
|---|
| 531 | {true, "PPP_GRO_KEY_MATCH_DATA_CNT" }, |
|---|
| 532 | {true, "PPP_GRO_KEY_MATCH_TCAM_CNT" }, |
|---|
| 533 | |
|---|
| 534 | {true, "PPP_GRO_INFO_MATCH_CNT" }, |
|---|
| 535 | {true, "PPP_GRO_FREE_ENTRY_CNT" }, |
|---|
| 536 | {true, "PPP_GRO_INNER_DFX_SIGNAL" }, |
|---|
| 537 | {false, "Reserved" }, |
|---|
| 538 | {false, "Reserved" }, |
|---|
| 539 | {false, "Reserved" }, |
|---|
| 540 | |
|---|
| 541 | {true, "GET_RX_PKT_CNT_L" }, |
|---|
| 542 | {true, "GET_RX_PKT_CNT_H" }, |
|---|
| 543 | {true, "GET_TX_PKT_CNT_L" }, |
|---|
| 544 | {true, "GET_TX_PKT_CNT_H" }, |
|---|
| 545 | {true, "SEND_UC_PRT2HOST_PKT_CNT_L" }, |
|---|
| 546 | {true, "SEND_UC_PRT2HOST_PKT_CNT_H" }, |
|---|
| 547 | |
|---|
| 548 | {true, "SEND_UC_PRT2PRT_PKT_CNT_L" }, |
|---|
| 549 | {true, "SEND_UC_PRT2PRT_PKT_CNT_H" }, |
|---|
| 550 | {true, "SEND_UC_HOST2HOST_PKT_CNT_L" }, |
|---|
| 551 | {true, "SEND_UC_HOST2HOST_PKT_CNT_H" }, |
|---|
| 552 | {true, "SEND_UC_HOST2PRT_PKT_CNT_L" }, |
|---|
| 553 | {true, "SEND_UC_HOST2PRT_PKT_CNT_H" }, |
|---|
| 554 | |
|---|
| 555 | {true, "SEND_MC_FROM_PRT_CNT_L" }, |
|---|
| 556 | {true, "SEND_MC_FROM_PRT_CNT_H" }, |
|---|
| 557 | {true, "SEND_MC_FROM_HOST_CNT_L" }, |
|---|
| 558 | {true, "SEND_MC_FROM_HOST_CNT_H" }, |
|---|
| 559 | {true, "SSU_MC_RD_CNT_L" }, |
|---|
| 560 | {true, "SSU_MC_RD_CNT_H" }, |
|---|
| 561 | |
|---|
| 562 | {true, "SSU_MC_DROP_CNT_L" }, |
|---|
| 563 | {true, "SSU_MC_DROP_CNT_H" }, |
|---|
| 564 | {true, "SSU_MC_RD_PKT_CNT_L" }, |
|---|
| 565 | {true, "SSU_MC_RD_PKT_CNT_H" }, |
|---|
| 566 | {true, "PPP_MC_2HOST_PKT_CNT_L" }, |
|---|
| 567 | {true, "PPP_MC_2HOST_PKT_CNT_H" }, |
|---|
| 568 | |
|---|
| 569 | {true, "PPP_MC_2PRT_PKT_CNT_L" }, |
|---|
| 570 | {true, "PPP_MC_2PRT_PKT_CNT_H" }, |
|---|
| 571 | {true, "NTSNOS_PKT_CNT_L" }, |
|---|
| 572 | {true, "NTSNOS_PKT_CNT_H" }, |
|---|
| 573 | {true, "NTUP_PKT_CNT_L" }, |
|---|
| 574 | {true, "NTUP_PKT_CNT_H" }, |
|---|
| 575 | |
|---|
| 576 | {true, "NTLCL_PKT_CNT_L" }, |
|---|
| 577 | {true, "NTLCL_PKT_CNT_H" }, |
|---|
| 578 | {true, "NTTGT_PKT_CNT_L" }, |
|---|
| 579 | {true, "NTTGT_PKT_CNT_H" }, |
|---|
| 580 | {true, "RTNS_PKT_CNT_L" }, |
|---|
| 581 | {true, "RTNS_PKT_CNT_H" }, |
|---|
| 582 | |
|---|
| 583 | {true, "RTLPBK_PKT_CNT_L" }, |
|---|
| 584 | {true, "RTLPBK_PKT_CNT_H" }, |
|---|
| 585 | {true, "NR_PKT_CNT_L" }, |
|---|
| 586 | {true, "NR_PKT_CNT_H" }, |
|---|
| 587 | {true, "RR_PKT_CNT_L" }, |
|---|
| 588 | {true, "RR_PKT_CNT_H" }, |
|---|
| 589 | |
|---|
| 590 | {true, "MNG_TBL_HIT_CNT_L" }, |
|---|
| 591 | {true, "MNG_TBL_HIT_CNT_H" }, |
|---|
| 592 | {true, "FD_TBL_HIT_CNT_L" }, |
|---|
| 593 | {true, "FD_TBL_HIT_CNT_H" }, |
|---|
| 594 | {true, "FD_LKUP_CNT_L" }, |
|---|
| 595 | {true, "FD_LKUP_CNT_H" }, |
|---|
| 596 | |
|---|
| 597 | {true, "BC_HIT_CNT_L" }, |
|---|
| 598 | {true, "BC_HIT_CNT_H" }, |
|---|
| 599 | {true, "UM_TBL_UC_HIT_CNT_L" }, |
|---|
| 600 | {true, "UM_TBL_UC_HIT_CNT_H" }, |
|---|
| 601 | {true, "UM_TBL_MC_HIT_CNT_L" }, |
|---|
| 602 | {true, "UM_TBL_MC_HIT_CNT_H" }, |
|---|
| 603 | |
|---|
| 604 | {true, "UM_TBL_VMDQ1_HIT_CNT_L" }, |
|---|
| 605 | {true, "UM_TBL_VMDQ1_HIT_CNT_H" }, |
|---|
| 606 | {true, "MTA_TBL_HIT_CNT_L" }, |
|---|
| 607 | {true, "MTA_TBL_HIT_CNT_H" }, |
|---|
| 608 | {true, "FWD_BONDING_HIT_CNT_L" }, |
|---|
| 609 | {true, "FWD_BONDING_HIT_CNT_H" }, |
|---|
| 610 | |
|---|
| 611 | {true, "PROMIS_TBL_HIT_CNT_L" }, |
|---|
| 612 | {true, "PROMIS_TBL_HIT_CNT_H" }, |
|---|
| 613 | {true, "GET_TUNL_PKT_CNT_L" }, |
|---|
| 614 | {true, "GET_TUNL_PKT_CNT_H" }, |
|---|
| 615 | {true, "GET_BMC_PKT_CNT_L" }, |
|---|
| 616 | {true, "GET_BMC_PKT_CNT_H" }, |
|---|
| 617 | |
|---|
| 618 | {true, "SEND_UC_PRT2BMC_PKT_CNT_L" }, |
|---|
| 619 | {true, "SEND_UC_PRT2BMC_PKT_CNT_H" }, |
|---|
| 620 | {true, "SEND_UC_HOST2BMC_PKT_CNT_L" }, |
|---|
| 621 | {true, "SEND_UC_HOST2BMC_PKT_CNT_H" }, |
|---|
| 622 | {true, "SEND_UC_BMC2HOST_PKT_CNT_L" }, |
|---|
| 623 | {true, "SEND_UC_BMC2HOST_PKT_CNT_H" }, |
|---|
| 624 | |
|---|
| 625 | {true, "SEND_UC_BMC2PRT_PKT_CNT_L" }, |
|---|
| 626 | {true, "SEND_UC_BMC2PRT_PKT_CNT_H" }, |
|---|
| 627 | {true, "PPP_MC_2BMC_PKT_CNT_L" }, |
|---|
| 628 | {true, "PPP_MC_2BMC_PKT_CNT_H" }, |
|---|
| 629 | {true, "VLAN_MIRR_CNT_L" }, |
|---|
| 630 | {true, "VLAN_MIRR_CNT_H" }, |
|---|
| 631 | |
|---|
| 632 | {true, "IG_MIRR_CNT_L" }, |
|---|
| 633 | {true, "IG_MIRR_CNT_H" }, |
|---|
| 634 | {true, "EG_MIRR_CNT_L" }, |
|---|
| 635 | {true, "EG_MIRR_CNT_H" }, |
|---|
| 636 | {true, "RX_DEFAULT_HOST_HIT_CNT_L" }, |
|---|
| 637 | {true, "RX_DEFAULT_HOST_HIT_CNT_H" }, |
|---|
| 638 | |
|---|
| 639 | {true, "LAN_PAIR_CNT_L" }, |
|---|
| 640 | {true, "LAN_PAIR_CNT_H" }, |
|---|
| 641 | {true, "UM_TBL_MC_HIT_PKT_CNT_L" }, |
|---|
| 642 | {true, "UM_TBL_MC_HIT_PKT_CNT_H" }, |
|---|
| 643 | {true, "MTA_TBL_HIT_PKT_CNT_L" }, |
|---|
| 644 | {true, "MTA_TBL_HIT_PKT_CNT_H" }, |
|---|
| 645 | |
|---|
| 646 | {true, "PROMIS_TBL_HIT_PKT_CNT_L" }, |
|---|
| 647 | {true, "PROMIS_TBL_HIT_PKT_CNT_H" }, |
|---|
| 648 | {false, "Reserved" }, |
|---|
| 649 | {false, "Reserved" }, |
|---|
| 650 | {false, "Reserved" }, |
|---|
| 651 | {false, "Reserved" }, |
|---|
| 652 | }; |
|---|
| 653 | |
|---|
| 654 | static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { |
|---|
| 655 | {false, "Reserved" }, |
|---|
| 656 | {true, "FSM_DFX_ST0" }, |
|---|
| 657 | {true, "FSM_DFX_ST1" }, |
|---|
| 658 | {true, "FSM_DFX_ST2" }, |
|---|
| 659 | {true, "FIFO_DFX_ST0" }, |
|---|
| 660 | {true, "FIFO_DFX_ST1" }, |
|---|
| 661 | |
|---|
| 662 | {true, "FIFO_DFX_ST2" }, |
|---|
| 663 | {true, "FIFO_DFX_ST3" }, |
|---|
| 664 | {true, "FIFO_DFX_ST4" }, |
|---|
| 665 | {true, "FIFO_DFX_ST5" }, |
|---|
| 666 | {true, "FIFO_DFX_ST6" }, |
|---|
| 667 | {true, "FIFO_DFX_ST7" }, |
|---|
| 668 | |
|---|
| 669 | {true, "FIFO_DFX_ST8" }, |
|---|
| 670 | {true, "FIFO_DFX_ST9" }, |
|---|
| 671 | {true, "FIFO_DFX_ST10" }, |
|---|
| 672 | {true, "FIFO_DFX_ST11" }, |
|---|
| 673 | {true, "Q_CREDIT_VLD_0" }, |
|---|
| 674 | {true, "Q_CREDIT_VLD_1" }, |
|---|
| 675 | |
|---|
| 676 | {true, "Q_CREDIT_VLD_2" }, |
|---|
| 677 | {true, "Q_CREDIT_VLD_3" }, |
|---|
| 678 | {true, "Q_CREDIT_VLD_4" }, |
|---|
| 679 | {true, "Q_CREDIT_VLD_5" }, |
|---|
| 680 | {true, "Q_CREDIT_VLD_6" }, |
|---|
| 681 | {true, "Q_CREDIT_VLD_7" }, |
|---|
| 682 | |
|---|
| 683 | {true, "Q_CREDIT_VLD_8" }, |
|---|
| 684 | {true, "Q_CREDIT_VLD_9" }, |
|---|
| 685 | {true, "Q_CREDIT_VLD_10" }, |
|---|
| 686 | {true, "Q_CREDIT_VLD_11" }, |
|---|
| 687 | {true, "Q_CREDIT_VLD_12" }, |
|---|
| 688 | {true, "Q_CREDIT_VLD_13" }, |
|---|
| 689 | |
|---|
| 690 | {true, "Q_CREDIT_VLD_14" }, |
|---|
| 691 | {true, "Q_CREDIT_VLD_15" }, |
|---|
| 692 | {true, "Q_CREDIT_VLD_16" }, |
|---|
| 693 | {true, "Q_CREDIT_VLD_17" }, |
|---|
| 694 | {true, "Q_CREDIT_VLD_18" }, |
|---|
| 695 | {true, "Q_CREDIT_VLD_19" }, |
|---|
| 696 | |
|---|
| 697 | {true, "Q_CREDIT_VLD_20" }, |
|---|
| 698 | {true, "Q_CREDIT_VLD_21" }, |
|---|
| 699 | {true, "Q_CREDIT_VLD_22" }, |
|---|
| 700 | {true, "Q_CREDIT_VLD_23" }, |
|---|
| 701 | {true, "Q_CREDIT_VLD_24" }, |
|---|
| 702 | {true, "Q_CREDIT_VLD_25" }, |
|---|
| 703 | |
|---|
| 704 | {true, "Q_CREDIT_VLD_26" }, |
|---|
| 705 | {true, "Q_CREDIT_VLD_27" }, |
|---|
| 706 | {true, "Q_CREDIT_VLD_28" }, |
|---|
| 707 | {true, "Q_CREDIT_VLD_29" }, |
|---|
| 708 | {true, "Q_CREDIT_VLD_30" }, |
|---|
| 709 | {true, "Q_CREDIT_VLD_31" }, |
|---|
| 710 | |
|---|
| 711 | {true, "GRO_BD_SERR_CNT" }, |
|---|
| 712 | {true, "GRO_CONTEXT_SERR_CNT" }, |
|---|
| 713 | {true, "RX_STASH_CFG_SERR_CNT" }, |
|---|
| 714 | {true, "AXI_RD_FBD_SERR_CNT" }, |
|---|
| 715 | {true, "GRO_BD_MERR_CNT" }, |
|---|
| 716 | {true, "GRO_CONTEXT_MERR_CNT" }, |
|---|
| 717 | |
|---|
| 718 | {true, "RX_STASH_CFG_MERR_CNT" }, |
|---|
| 719 | {true, "AXI_RD_FBD_MERR_CNT" }, |
|---|
| 720 | {false, "Reserved" }, |
|---|
| 721 | {false, "Reserved" }, |
|---|
| 722 | {false, "Reserved" }, |
|---|
| 723 | {false, "Reserved" }, |
|---|
| 724 | }; |
|---|
| 725 | |
|---|
| 726 | static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { |
|---|
| 727 | {true, "q_num" }, |
|---|
| 728 | {true, "RCB_CFG_RX_RING_TAIL" }, |
|---|
| 729 | {true, "RCB_CFG_RX_RING_HEAD" }, |
|---|
| 730 | {true, "RCB_CFG_RX_RING_FBDNUM" }, |
|---|
| 731 | {true, "RCB_CFG_RX_RING_OFFSET" }, |
|---|
| 732 | {true, "RCB_CFG_RX_RING_FBDOFFSET" }, |
|---|
| 733 | |
|---|
| 734 | {true, "RCB_CFG_RX_RING_PKTNUM_RECORD" }, |
|---|
| 735 | {true, "RCB_CFG_TX_RING_TAIL" }, |
|---|
| 736 | {true, "RCB_CFG_TX_RING_HEAD" }, |
|---|
| 737 | {true, "RCB_CFG_TX_RING_FBDNUM" }, |
|---|
| 738 | {true, "RCB_CFG_TX_RING_OFFSET" }, |
|---|
| 739 | {true, "RCB_CFG_TX_RING_EBDNUM" }, |
|---|
| 740 | }; |
|---|
| 741 | |
|---|
| 742 | #define HCLGE_DBG_INFO_LEN 256 |
|---|
| 743 | #define HCLGE_DBG_VLAN_FLTR_INFO_LEN 256 |
|---|
| 744 | #define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN 512 |
|---|
| 745 | #define HCLGE_DBG_ID_LEN 16 |
|---|
| 746 | #define HCLGE_DBG_ITEM_NAME_LEN 32 |
|---|
| 747 | #define HCLGE_DBG_DATA_STR_LEN 32 |
|---|
| 748 | #define HCLGE_DBG_TM_INFO_LEN 256 |
|---|
| 749 | |
|---|
| 750 | #define HCLGE_BILLION_NANO_SECONDS 1000000000 |
|---|
| 751 | |
|---|
| 752 | struct hclge_dbg_item { |
|---|
| 753 | char name[HCLGE_DBG_ITEM_NAME_LEN]; |
|---|
| 754 | u16 interval; /* blank numbers after the item */ |
|---|
| 755 | }; |
|---|
| 756 | |
|---|
| 757 | struct hclge_dbg_vlan_cfg { |
|---|
| 758 | u16 pvid; |
|---|
| 759 | u8 accept_tag1; |
|---|
| 760 | u8 accept_tag2; |
|---|
| 761 | u8 accept_untag1; |
|---|
| 762 | u8 accept_untag2; |
|---|
| 763 | u8 insert_tag1; |
|---|
| 764 | u8 insert_tag2; |
|---|
| 765 | u8 shift_tag; |
|---|
| 766 | u8 strip_tag1; |
|---|
| 767 | u8 strip_tag2; |
|---|
| 768 | u8 drop_tag1; |
|---|
| 769 | u8 drop_tag2; |
|---|
| 770 | u8 pri_only1; |
|---|
| 771 | u8 pri_only2; |
|---|
| 772 | }; |
|---|
| 773 | |
|---|
| 774 | #endif |
|---|
| 775 | |
|---|
