1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Huawei HiNIC PCI Express Linux driver |
4 | * Copyright(c) 2017 Huawei Technologies Co., Ltd |
5 | */ |
6 | |
7 | #include <linux/pci.h> |
8 | #include <linux/device.h> |
9 | #include <linux/errno.h> |
10 | #include <linux/io.h> |
11 | #include <linux/types.h> |
12 | #include <linux/bitops.h> |
13 | #include <linux/delay.h> |
14 | |
15 | #include "hinic_hw_csr.h" |
16 | #include "hinic_hw_if.h" |
17 | |
18 | #define PCIE_ATTR_ENTRY 0 |
19 | |
20 | #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) |
21 | |
22 | #define WAIT_HWIF_READY_TIMEOUT 10000 |
23 | |
24 | #define HINIC_SELFTEST_RESULT 0x883C |
25 | |
26 | /** |
27 | * hinic_msix_attr_set - set message attribute for msix entry |
28 | * @hwif: the HW interface of a pci function device |
29 | * @msix_index: msix_index |
30 | * @pending_limit: the maximum pending interrupt events (unit 8) |
31 | * @coalesc_timer: coalesc period for interrupt (unit 8 us) |
32 | * @lli_timer: replenishing period for low latency credit (unit 8 us) |
33 | * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) |
34 | * @resend_timer: maximum wait for resending msix (unit coalesc period) |
35 | * |
36 | * Return 0 - Success, negative - Failure |
37 | **/ |
38 | int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, |
39 | u8 pending_limit, u8 coalesc_timer, |
40 | u8 lli_timer, u8 lli_credit_limit, |
41 | u8 resend_timer) |
42 | { |
43 | u32 msix_ctrl, addr; |
44 | |
45 | if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) |
46 | return -EINVAL; |
47 | |
48 | msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | |
49 | HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | |
50 | HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | |
51 | HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | |
52 | HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); |
53 | |
54 | addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); |
55 | |
56 | hinic_hwif_write_reg(hwif, reg: addr, val: msix_ctrl); |
57 | return 0; |
58 | } |
59 | |
60 | /** |
61 | * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry |
62 | * @hwif: the HW interface of a pci function device |
63 | * @msix_index: msix_index |
64 | * |
65 | * Return 0 - Success, negative - Failure |
66 | **/ |
67 | int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) |
68 | { |
69 | u32 msix_ctrl, addr; |
70 | |
71 | if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) |
72 | return -EINVAL; |
73 | |
74 | msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); |
75 | addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); |
76 | |
77 | hinic_hwif_write_reg(hwif, reg: addr, val: msix_ctrl); |
78 | return 0; |
79 | } |
80 | |
81 | /** |
82 | * hinic_set_pf_action - set action on pf channel |
83 | * @hwif: the HW interface of a pci function device |
84 | * @action: action on pf channel |
85 | **/ |
86 | void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) |
87 | { |
88 | u32 attr5; |
89 | |
90 | if (HINIC_IS_VF(hwif)) |
91 | return; |
92 | |
93 | attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); |
94 | attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); |
95 | attr5 |= HINIC_FA5_SET(action, PF_ACTION); |
96 | |
97 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, val: attr5); |
98 | } |
99 | |
100 | enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) |
101 | { |
102 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); |
103 | |
104 | return HINIC_FA4_GET(attr4, OUTBOUND_STATE); |
105 | } |
106 | |
107 | void hinic_outbound_state_set(struct hinic_hwif *hwif, |
108 | enum hinic_outbound_state outbound_state) |
109 | { |
110 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); |
111 | |
112 | attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); |
113 | attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); |
114 | |
115 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, val: attr4); |
116 | } |
117 | |
118 | enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) |
119 | { |
120 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); |
121 | |
122 | return HINIC_FA4_GET(attr4, DB_STATE); |
123 | } |
124 | |
125 | void hinic_db_state_set(struct hinic_hwif *hwif, |
126 | enum hinic_db_state db_state) |
127 | { |
128 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); |
129 | |
130 | attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); |
131 | attr4 |= HINIC_FA4_SET(db_state, DB_STATE); |
132 | |
133 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, val: attr4); |
134 | } |
135 | |
136 | void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, |
137 | enum hinic_msix_state flag) |
138 | { |
139 | u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + |
140 | HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; |
141 | u32 mask_bits; |
142 | |
143 | mask_bits = readl(addr: hwif->intr_regs_base + offset); |
144 | mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; |
145 | |
146 | if (flag) |
147 | mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; |
148 | |
149 | writel(val: mask_bits, addr: hwif->intr_regs_base + offset); |
150 | } |
151 | |
152 | /** |
153 | * hwif_ready - test if the HW is ready for use |
154 | * @hwif: the HW interface of a pci function device |
155 | * |
156 | * Return 0 - Success, negative - Failure |
157 | **/ |
158 | static int hwif_ready(struct hinic_hwif *hwif) |
159 | { |
160 | u32 addr, attr1; |
161 | |
162 | addr = HINIC_CSR_FUNC_ATTR1_ADDR; |
163 | attr1 = hinic_hwif_read_reg(hwif, reg: addr); |
164 | |
165 | if (!HINIC_FA1_GET(attr1, MGMT_INIT_STATUS)) |
166 | return -EBUSY; |
167 | |
168 | if (HINIC_IS_VF(hwif)) { |
169 | if (!HINIC_FA1_GET(attr1, PF_INIT_STATUS)) |
170 | return -EBUSY; |
171 | } |
172 | |
173 | return 0; |
174 | } |
175 | |
176 | static int wait_hwif_ready(struct hinic_hwif *hwif) |
177 | { |
178 | unsigned long timeout = 0; |
179 | |
180 | do { |
181 | if (!hwif_ready(hwif)) |
182 | return 0; |
183 | |
184 | usleep_range(min: 999, max: 1000); |
185 | timeout++; |
186 | } while (timeout <= WAIT_HWIF_READY_TIMEOUT); |
187 | |
188 | dev_err(&hwif->pdev->dev, "Wait for hwif timeout\n" ); |
189 | |
190 | return -EBUSY; |
191 | } |
192 | |
193 | /** |
194 | * set_hwif_attr - set the attributes in the relevant members in hwif |
195 | * @hwif: the HW interface of a pci function device |
196 | * @attr0: the first attribute that was read from the hw |
197 | * @attr1: the second attribute that was read from the hw |
198 | * @attr2: the third attribute that was read from the hw |
199 | **/ |
200 | static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1, |
201 | u32 attr2) |
202 | { |
203 | hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); |
204 | hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); |
205 | hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); |
206 | hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); |
207 | |
208 | hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); |
209 | hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); |
210 | hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); |
211 | hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); |
212 | hwif->attr.global_vf_id_of_pf = HINIC_FA2_GET(attr2, |
213 | GLOBAL_VF_ID_OF_PF); |
214 | } |
215 | |
216 | /** |
217 | * read_hwif_attr - read the attributes and set members in hwif |
218 | * @hwif: the HW interface of a pci function device |
219 | **/ |
220 | static void read_hwif_attr(struct hinic_hwif *hwif) |
221 | { |
222 | u32 addr, attr0, attr1, attr2; |
223 | |
224 | addr = HINIC_CSR_FUNC_ATTR0_ADDR; |
225 | attr0 = hinic_hwif_read_reg(hwif, reg: addr); |
226 | |
227 | addr = HINIC_CSR_FUNC_ATTR1_ADDR; |
228 | attr1 = hinic_hwif_read_reg(hwif, reg: addr); |
229 | |
230 | addr = HINIC_CSR_FUNC_ATTR2_ADDR; |
231 | attr2 = hinic_hwif_read_reg(hwif, reg: addr); |
232 | |
233 | set_hwif_attr(hwif, attr0, attr1, attr2); |
234 | } |
235 | |
236 | /** |
237 | * set_ppf - try to set hwif as ppf and set the type of hwif in this case |
238 | * @hwif: the HW interface of a pci function device |
239 | **/ |
240 | static void set_ppf(struct hinic_hwif *hwif) |
241 | { |
242 | struct hinic_func_attr *attr = &hwif->attr; |
243 | u32 addr, val, ppf_election; |
244 | |
245 | /* Read Modify Write */ |
246 | addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); |
247 | |
248 | val = hinic_hwif_read_reg(hwif, reg: addr); |
249 | val = HINIC_PPF_ELECTION_CLEAR(val, IDX); |
250 | |
251 | ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); |
252 | |
253 | val |= ppf_election; |
254 | hinic_hwif_write_reg(hwif, reg: addr, val); |
255 | |
256 | /* check PPF */ |
257 | val = hinic_hwif_read_reg(hwif, reg: addr); |
258 | |
259 | attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); |
260 | if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) |
261 | attr->func_type = HINIC_PPF; |
262 | } |
263 | |
264 | /** |
265 | * set_dma_attr - set the dma attributes in the HW |
266 | * @hwif: the HW interface of a pci function device |
267 | * @entry_idx: the entry index in the dma table |
268 | * @st: PCIE TLP steering tag |
269 | * @at: PCIE TLP AT field |
270 | * @ph: PCIE TLP Processing Hint field |
271 | * @no_snooping: PCIE TLP No snooping |
272 | * @tph_en: PCIE TLP Processing Hint Enable |
273 | **/ |
274 | static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, |
275 | u8 st, u8 at, u8 ph, |
276 | enum hinic_pcie_nosnoop no_snooping, |
277 | enum hinic_pcie_tph tph_en) |
278 | { |
279 | u32 addr, val, dma_attr_entry; |
280 | |
281 | /* Read Modify Write */ |
282 | addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); |
283 | |
284 | val = hinic_hwif_read_reg(hwif, reg: addr); |
285 | val = HINIC_DMA_ATTR_CLEAR(val, ST) & |
286 | HINIC_DMA_ATTR_CLEAR(val, AT) & |
287 | HINIC_DMA_ATTR_CLEAR(val, PH) & |
288 | HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & |
289 | HINIC_DMA_ATTR_CLEAR(val, TPH_EN); |
290 | |
291 | dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | |
292 | HINIC_DMA_ATTR_SET(at, AT) | |
293 | HINIC_DMA_ATTR_SET(ph, PH) | |
294 | HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | |
295 | HINIC_DMA_ATTR_SET(tph_en, TPH_EN); |
296 | |
297 | val |= dma_attr_entry; |
298 | hinic_hwif_write_reg(hwif, reg: addr, val); |
299 | } |
300 | |
301 | /** |
302 | * dma_attr_init - initialize the default dma attributes |
303 | * @hwif: the HW interface of a pci function device |
304 | **/ |
305 | static void dma_attr_init(struct hinic_hwif *hwif) |
306 | { |
307 | set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, |
308 | HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, |
309 | no_snooping: HINIC_PCIE_SNOOP, tph_en: HINIC_PCIE_TPH_DISABLE); |
310 | } |
311 | |
312 | u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif) |
313 | { |
314 | if (!hwif) |
315 | return 0; |
316 | |
317 | return hwif->attr.global_vf_id_of_pf; |
318 | } |
319 | |
320 | u16 hinic_global_func_id_hw(struct hinic_hwif *hwif) |
321 | { |
322 | u32 addr, attr0; |
323 | |
324 | addr = HINIC_CSR_FUNC_ATTR0_ADDR; |
325 | attr0 = hinic_hwif_read_reg(hwif, reg: addr); |
326 | |
327 | return HINIC_FA0_GET(attr0, FUNC_IDX); |
328 | } |
329 | |
330 | u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif) |
331 | { |
332 | u32 addr, attr0; |
333 | |
334 | addr = HINIC_CSR_FUNC_ATTR0_ADDR; |
335 | attr0 = hinic_hwif_read_reg(hwif, reg: addr); |
336 | |
337 | return HINIC_FA0_GET(attr0, PF_IDX); |
338 | } |
339 | |
340 | static void __print_selftest_reg(struct hinic_hwif *hwif) |
341 | { |
342 | u32 addr, attr0, attr1; |
343 | |
344 | addr = HINIC_CSR_FUNC_ATTR1_ADDR; |
345 | attr1 = hinic_hwif_read_reg(hwif, reg: addr); |
346 | |
347 | if (attr1 == HINIC_PCIE_LINK_DOWN) { |
348 | dev_err(&hwif->pdev->dev, "PCIE is link down\n" ); |
349 | return; |
350 | } |
351 | |
352 | addr = HINIC_CSR_FUNC_ATTR0_ADDR; |
353 | attr0 = hinic_hwif_read_reg(hwif, reg: addr); |
354 | if (HINIC_FA0_GET(attr0, FUNC_TYPE) != HINIC_VF && |
355 | !HINIC_FA0_GET(attr0, PCI_INTF_IDX)) |
356 | dev_err(&hwif->pdev->dev, "Selftest reg: 0x%08x\n" , |
357 | hinic_hwif_read_reg(hwif, HINIC_SELFTEST_RESULT)); |
358 | } |
359 | |
360 | /** |
361 | * hinic_init_hwif - initialize the hw interface |
362 | * @hwif: the HW interface of a pci function device |
363 | * @pdev: the pci device for accessing PCI resources |
364 | * |
365 | * Return 0 - Success, negative - Failure |
366 | **/ |
367 | int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) |
368 | { |
369 | int err; |
370 | |
371 | hwif->pdev = pdev; |
372 | |
373 | hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); |
374 | if (!hwif->cfg_regs_bar) { |
375 | dev_err(&pdev->dev, "Failed to map configuration regs\n" ); |
376 | return -ENOMEM; |
377 | } |
378 | |
379 | hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); |
380 | if (!hwif->intr_regs_base) { |
381 | dev_err(&pdev->dev, "Failed to map configuration regs\n" ); |
382 | err = -ENOMEM; |
383 | goto err_map_intr_bar; |
384 | } |
385 | |
386 | err = wait_hwif_ready(hwif); |
387 | if (err) { |
388 | dev_err(&pdev->dev, "HW interface is not ready\n" ); |
389 | __print_selftest_reg(hwif); |
390 | goto err_hwif_ready; |
391 | } |
392 | |
393 | read_hwif_attr(hwif); |
394 | |
395 | if (HINIC_IS_PF(hwif)) |
396 | set_ppf(hwif); |
397 | |
398 | /* No transactionss before DMA is initialized */ |
399 | dma_attr_init(hwif); |
400 | return 0; |
401 | |
402 | err_hwif_ready: |
403 | iounmap(addr: hwif->intr_regs_base); |
404 | |
405 | err_map_intr_bar: |
406 | iounmap(addr: hwif->cfg_regs_bar); |
407 | |
408 | return err; |
409 | } |
410 | |
411 | /** |
412 | * hinic_free_hwif - free the HW interface |
413 | * @hwif: the HW interface of a pci function device |
414 | **/ |
415 | void hinic_free_hwif(struct hinic_hwif *hwif) |
416 | { |
417 | iounmap(addr: hwif->intr_regs_base); |
418 | iounmap(addr: hwif->cfg_regs_bar); |
419 | } |
420 | |