1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4	/* 82562G 10/100 Network Connection
5	* 82562G-2 10/100 Network Connection
6	* 82562GT 10/100 Network Connection
7	* 82562GT-2 10/100 Network Connection
8	* 82562V 10/100 Network Connection
9	* 82562V-2 10/100 Network Connection
10	* 82566DC-2 Gigabit Network Connection
11	* 82566DC Gigabit Network Connection
12	* 82566DM-2 Gigabit Network Connection
13	* 82566DM Gigabit Network Connection
14	* 82566MC Gigabit Network Connection
15	* 82566MM Gigabit Network Connection
16	* 82567LM Gigabit Network Connection
17	* 82567LF Gigabit Network Connection
18	* 82567V Gigabit Network Connection
19	* 82567LM-2 Gigabit Network Connection
20	* 82567LF-2 Gigabit Network Connection
21	* 82567V-2 Gigabit Network Connection
22	* 82567LF-3 Gigabit Network Connection
23	* 82567LM-3 Gigabit Network Connection
24	* 82567LM-4 Gigabit Network Connection
25	* 82577LM Gigabit Network Connection
26	* 82577LC Gigabit Network Connection
27	* 82578DM Gigabit Network Connection
28	* 82578DC Gigabit Network Connection
29	* 82579LM Gigabit Network Connection
30	* 82579V Gigabit Network Connection
31	* Ethernet Connection I217-LM
32	* Ethernet Connection I217-V
33	* Ethernet Connection I218-V
34	* Ethernet Connection I218-LM
35	* Ethernet Connection (2) I218-LM
36	* Ethernet Connection (2) I218-V
37	* Ethernet Connection (3) I218-LM
38	* Ethernet Connection (3) I218-V
39	*/
40
41	#include "e1000.h"
42
43	/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44	/* Offset 04h HSFSTS */
45	union ich8_hws_flash_status {
46	struct ich8_hsfsts {
47	u16 flcdone:1; /* bit 0 Flash Cycle Done */
48	u16 flcerr:1; /* bit 1 Flash Cycle Error */
49	u16 dael:1; /* bit 2 Direct Access error Log */
50	u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51	u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52	u16 reserved1:2; /* bit 13:6 Reserved */
53	u16 reserved2:6; /* bit 13:6 Reserved */
54	u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55	u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56	} hsf_status;
57	u16 regval;
58	};
59
60	/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61	/* Offset 06h FLCTL */
62	union ich8_hws_flash_ctrl {
63	struct ich8_hsflctl {
64	u16 flcgo:1; /* 0 Flash Cycle Go */
65	u16 flcycle:2; /* 2:1 Flash Cycle */
66	u16 reserved:5; /* 7:3 Reserved */
67	u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68	u16 flockdn:6; /* 15:10 Reserved */
69	} hsf_ctrl;
70	u16 regval;
71	};
72
73	/* ICH Flash Region Access Permissions */
74	union ich8_hws_flash_regacc {
75	struct ich8_flracc {
76	u32 grra:8; /* 0:7 GbE region Read Access */
77	u32 grwa:8; /* 8:15 GbE region Write Access */
78	u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79	u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80	} hsf_flregacc;
81	u16 regval;
82	};
83
84	/* ICH Flash Protected Region */
85	union ich8_flash_protected_range {
86	struct ich8_pr {
87	u32 base:13; /* 0:12 Protected Range Base */
88	u32 reserved1:2; /* 13:14 Reserved */
89	u32 rpe:1; /* 15 Read Protection Enable */
90	u32 limit:13; /* 16:28 Protected Range Limit */
91	u32 reserved2:2; /* 29:30 Reserved */
92	u32 wpe:1; /* 31 Write Protection Enable */
93	} range;
94	u32 regval;
95	};
96
97	static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98	static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99	static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100	static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101	u32 offset, u8 byte);
102	static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103	u8 *data);
104	static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105	u16 *data);
106	static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107	u8 size, u16 *data);
108	static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109	u32 *data);
110	static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111	u32 offset, u32 *data);
112	static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113	u32 offset, u32 data);
114	static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115	u32 offset, u32 dword);
116	static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117	static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118	static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119	static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120	static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121	static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122	static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123	static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124	static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125	static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126	static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127	static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128	static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129	static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130	static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131	static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132	static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133	static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134	static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135	static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136	static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137	static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138	static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139	static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141	static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142	{
143	return readw(addr: hw->flash_address + reg);
144	}
145
146	static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147	{
148	return readl(addr: hw->flash_address + reg);
149	}
150
151	static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152	{
153	writew(val, addr: hw->flash_address + reg);
154	}
155
156	static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157	{
158	writel(val, addr: hw->flash_address + reg);
159	}
160
161	#define er16flash(reg) __er16flash(hw, (reg))
162	#define er32flash(reg) __er32flash(hw, (reg))
163	#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164	#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166	/**
167	* e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168	* @hw: pointer to the HW structure
169	*
170	* Test access to the PHY registers by reading the PHY ID registers. If
171	* the PHY ID is already known (e.g. resume path) compare it with known ID,
172	* otherwise assume the read PHY ID is correct if it is valid.
173	*
174	* Assumes the sw/fw/hw semaphore is already acquired.
175	**/
176	static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177	{
178	u16 phy_reg = 0;
179	u32 phy_id = 0;
180	s32 ret_val = 0;
181	u16 retry_count;
182	u32 mac_reg = 0;
183
184	for (retry_count = 0; retry_count < 2; retry_count++) {
185	ret_val = e1e_rphy_locked(hw, MII_PHYSID1, data: &phy_reg);
186	if (ret_val || (phy_reg == 0xFFFF))
187	continue;
188	phy_id = (u32)(phy_reg << 16);
189
190	ret_val = e1e_rphy_locked(hw, MII_PHYSID2, data: &phy_reg);
191	if (ret_val || (phy_reg == 0xFFFF)) {
192	phy_id = 0;
193	continue;
194	}
195	phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196	break;
197	}
198
199	if (hw->phy.id) {
200	if (hw->phy.id == phy_id)
201	goto out;
202	} else if (phy_id) {
203	hw->phy.id = phy_id;
204	hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205	goto out;
206	}
207
208	/* In case the PHY needs to be in mdio slow mode,
209	* set slow mode and try to get the PHY id again.
210	*/
211	if (hw->mac.type < e1000_pch_lpt) {
212	hw->phy.ops.release(hw);
213	ret_val = e1000_set_mdio_slow_mode_hv(hw);
214	if (!ret_val)
215	ret_val = e1000e_get_phy_id(hw);
216	hw->phy.ops.acquire(hw);
217	}
218
219	if (ret_val)
220	return false;
221	out:
222	if (hw->mac.type >= e1000_pch_lpt) {
223	/* Only unforce SMBus if ME is not active */
224	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225	/* Switching PHY interface always returns MDI error
226	* so disable retry mechanism to avoid wasting time
227	*/
228	e1000e_disable_phy_retry(hw);
229
230	/* Unforce SMBus mode in PHY */
231	e1e_rphy_locked(hw, CV_SMB_CTRL, data: &phy_reg);
232	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
233	e1e_wphy_locked(hw, CV_SMB_CTRL, data: phy_reg);
234
235	e1000e_enable_phy_retry(hw);
236
237	/* Unforce SMBus mode in MAC */
238	mac_reg = er32(CTRL_EXT);
239	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
240	ew32(CTRL_EXT, mac_reg);
241	}
242	}
243
244	return true;
245	}
246
247	/**
248	* e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
249	* @hw: pointer to the HW structure
250	*
251	* Toggling the LANPHYPC pin value fully power-cycles the PHY and is
252	* used to reset the PHY to a quiescent state when necessary.
253	**/
254	static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
255	{
256	u32 mac_reg;
257
258	/* Set Phy Config Counter to 50msec */
259	mac_reg = er32(FEXTNVM3);
260	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
261	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
262	ew32(FEXTNVM3, mac_reg);
263
264	/* Toggle LANPHYPC Value bit */
265	mac_reg = er32(CTRL);
266	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
267	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
268	ew32(CTRL, mac_reg);
269	e1e_flush();
270	usleep_range(min: 10, max: 20);
271	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
272	ew32(CTRL, mac_reg);
273	e1e_flush();
274
275	if (hw->mac.type < e1000_pch_lpt) {
276	msleep(msecs: 50);
277	} else {
278	u16 count = 20;
279
280	do {
281	usleep_range(min: 5000, max: 6000);
282	} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
283
284	msleep(msecs: 30);
285	}
286	}
287
288	/**
289	* e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
290	* @hw: pointer to the HW structure
291	*
292	* Workarounds/flow necessary for PHY initialization during driver load
293	* and resume paths.
294	**/
295	static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
296	{
297	struct e1000_adapter *adapter = hw->adapter;
298	u32 mac_reg, fwsm = er32(FWSM);
299	s32 ret_val;
300
301	/* Gate automatic PHY configuration by hardware on managed and
302	* non-managed 82579 and newer adapters.
303	*/
304	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
305
306	/* It is not possible to be certain of the current state of ULP
307	* so forcibly disable it.
308	*/
309	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
310	ret_val = e1000_disable_ulp_lpt_lp(hw, force: true);
311	if (ret_val)
312	e_warn("Failed to disable ULP\n");
313
314	ret_val = hw->phy.ops.acquire(hw);
315	if (ret_val) {
316	e_dbg("Failed to initialize PHY flow\n");
317	goto out;
318	}
319
320	/* There is no guarantee that the PHY is accessible at this time
321	* so disable retry mechanism to avoid wasting time
322	*/
323	e1000e_disable_phy_retry(hw);
324
325	/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326	* inaccessible and resetting the PHY is not blocked, toggle the
327	* LANPHYPC Value bit to force the interconnect to PCIe mode.
328	*/
329	switch (hw->mac.type) {
330	case e1000_pch_lpt:
331	case e1000_pch_spt:
332	case e1000_pch_cnp:
333	case e1000_pch_tgp:
334	case e1000_pch_adp:
335	case e1000_pch_mtp:
336	case e1000_pch_lnp:
337	case e1000_pch_ptp:
338	case e1000_pch_nvp:
339	if (e1000_phy_is_accessible_pchlan(hw))
340	break;
341
342	/* Before toggling LANPHYPC, see if PHY is accessible by
343	* forcing MAC to SMBus mode first.
344	*/
345	mac_reg = er32(CTRL_EXT);
346	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
347	ew32(CTRL_EXT, mac_reg);
348
349	/* Wait 50 milliseconds for MAC to finish any retries
350	* that it might be trying to perform from previous
351	* attempts to acknowledge any phy read requests.
352	*/
353	msleep(msecs: 50);
354
355	fallthrough;
356	case e1000_pch2lan:
357	if (e1000_phy_is_accessible_pchlan(hw))
358	break;
359
360	fallthrough;
361	case e1000_pchlan:
362	if ((hw->mac.type == e1000_pchlan) &&
363	(fwsm & E1000_ICH_FWSM_FW_VALID))
364	break;
365
366	if (hw->phy.ops.check_reset_block(hw)) {
367	e_dbg("Required LANPHYPC toggle blocked by ME\n");
368	ret_val = -E1000_ERR_PHY;
369	break;
370	}
371
372	/* Toggle LANPHYPC Value bit */
373	e1000_toggle_lanphypc_pch_lpt(hw);
374	if (hw->mac.type >= e1000_pch_lpt) {
375	if (e1000_phy_is_accessible_pchlan(hw))
376	break;
377
378	/* Toggling LANPHYPC brings the PHY out of SMBus mode
379	* so ensure that the MAC is also out of SMBus mode
380	*/
381	mac_reg = er32(CTRL_EXT);
382	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
383	ew32(CTRL_EXT, mac_reg);
384
385	if (e1000_phy_is_accessible_pchlan(hw))
386	break;
387
388	ret_val = -E1000_ERR_PHY;
389	}
390	break;
391	default:
392	break;
393	}
394
395	e1000e_enable_phy_retry(hw);
396
397	hw->phy.ops.release(hw);
398	if (!ret_val) {
399
400	/* Check to see if able to reset PHY. Print error if not */
401	if (hw->phy.ops.check_reset_block(hw)) {
402	e_err("Reset blocked by ME\n");
403	goto out;
404	}
405
406	/* Reset the PHY before any access to it. Doing so, ensures
407	* that the PHY is in a known good state before we read/write
408	* PHY registers. The generic reset is sufficient here,
409	* because we haven't determined the PHY type yet.
410	*/
411	ret_val = e1000e_phy_hw_reset_generic(hw);
412	if (ret_val)
413	goto out;
414
415	/* On a successful reset, possibly need to wait for the PHY
416	* to quiesce to an accessible state before returning control
417	* to the calling function. If the PHY does not quiesce, then
418	* return E1000E_BLK_PHY_RESET, as this is the condition that
419	* the PHY is in.
420	*/
421	ret_val = hw->phy.ops.check_reset_block(hw);
422	if (ret_val)
423	e_err("ME blocked access to PHY after reset\n");
424	}
425
426	out:
427	/* Ungate automatic PHY configuration on non-managed 82579 */
428	if ((hw->mac.type == e1000_pch2lan) &&
429	!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
430	usleep_range(min: 10000, max: 11000);
431	e1000_gate_hw_phy_config_ich8lan(hw, gate: false);
432	}
433
434	return ret_val;
435	}
436
437	/**
438	* e1000_init_phy_params_pchlan - Initialize PHY function pointers
439	* @hw: pointer to the HW structure
440	*
441	* Initialize family-specific PHY parameters and function pointers.
442	**/
443	static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
444	{
445	struct e1000_phy_info *phy = &hw->phy;
446	s32 ret_val;
447
448	phy->addr = 1;
449	phy->reset_delay_us = 100;
450
451	phy->ops.set_page = e1000_set_page_igp;
452	phy->ops.read_reg = e1000_read_phy_reg_hv;
453	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
454	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
455	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
456	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
457	phy->ops.write_reg = e1000_write_phy_reg_hv;
458	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
459	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
460	phy->ops.power_up = e1000_power_up_phy_copper;
461	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
462	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
463
464	phy->id = e1000_phy_unknown;
465
466	if (hw->mac.type == e1000_pch_mtp) {
467	phy->retry_count = 2;
468	e1000e_enable_phy_retry(hw);
469	}
470
471	ret_val = e1000_init_phy_workarounds_pchlan(hw);
472	if (ret_val)
473	return ret_val;
474
475	if (phy->id == e1000_phy_unknown)
476	switch (hw->mac.type) {
477	default:
478	ret_val = e1000e_get_phy_id(hw);
479	if (ret_val)
480	return ret_val;
481	if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
482	break;
483	fallthrough;
484	case e1000_pch2lan:
485	case e1000_pch_lpt:
486	case e1000_pch_spt:
487	case e1000_pch_cnp:
488	case e1000_pch_tgp:
489	case e1000_pch_adp:
490	case e1000_pch_mtp:
491	case e1000_pch_lnp:
492	case e1000_pch_ptp:
493	case e1000_pch_nvp:
494	/* In case the PHY needs to be in mdio slow mode,
495	* set slow mode and try to get the PHY id again.
496	*/
497	ret_val = e1000_set_mdio_slow_mode_hv(hw);
498	if (ret_val)
499	return ret_val;
500	ret_val = e1000e_get_phy_id(hw);
501	if (ret_val)
502	return ret_val;
503	break;
504	}
505	phy->type = e1000e_get_phy_type_from_id(phy_id: phy->id);
506
507	switch (phy->type) {
508	case e1000_phy_82577:
509	case e1000_phy_82579:
510	case e1000_phy_i217:
511	phy->ops.check_polarity = e1000_check_polarity_82577;
512	phy->ops.force_speed_duplex =
513	e1000_phy_force_speed_duplex_82577;
514	phy->ops.get_cable_length = e1000_get_cable_length_82577;
515	phy->ops.get_info = e1000_get_phy_info_82577;
516	phy->ops.commit = e1000e_phy_sw_reset;
517	break;
518	case e1000_phy_82578:
519	phy->ops.check_polarity = e1000_check_polarity_m88;
520	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
521	phy->ops.get_cable_length = e1000e_get_cable_length_m88;
522	phy->ops.get_info = e1000e_get_phy_info_m88;
523	break;
524	default:
525	ret_val = -E1000_ERR_PHY;
526	break;
527	}
528
529	return ret_val;
530	}
531
532	/**
533	* e1000_init_phy_params_ich8lan - Initialize PHY function pointers
534	* @hw: pointer to the HW structure
535	*
536	* Initialize family-specific PHY parameters and function pointers.
537	**/
538	static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
539	{
540	struct e1000_phy_info *phy = &hw->phy;
541	s32 ret_val;
542	u16 i = 0;
543
544	phy->addr = 1;
545	phy->reset_delay_us = 100;
546
547	phy->ops.power_up = e1000_power_up_phy_copper;
548	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
549
550	/* We may need to do this twice - once for IGP and if that fails,
551	* we'll set BM func pointers and try again
552	*/
553	ret_val = e1000e_determine_phy_address(hw);
554	if (ret_val) {
555	phy->ops.write_reg = e1000e_write_phy_reg_bm;
556	phy->ops.read_reg = e1000e_read_phy_reg_bm;
557	ret_val = e1000e_determine_phy_address(hw);
558	if (ret_val) {
559	e_dbg("Cannot determine PHY addr. Erroring out\n");
560	return ret_val;
561	}
562	}
563
564	phy->id = 0;
565	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy_id: phy->id)) &&
566	(i++ < 100)) {
567	usleep_range(min: 1000, max: 1100);
568	ret_val = e1000e_get_phy_id(hw);
569	if (ret_val)
570	return ret_val;
571	}
572
573	/* Verify phy id */
574	switch (phy->id) {
575	case IGP03E1000_E_PHY_ID:
576	phy->type = e1000_phy_igp_3;
577	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
578	phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
579	phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
580	phy->ops.get_info = e1000e_get_phy_info_igp;
581	phy->ops.check_polarity = e1000_check_polarity_igp;
582	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
583	break;
584	case IFE_E_PHY_ID:
585	case IFE_PLUS_E_PHY_ID:
586	case IFE_C_E_PHY_ID:
587	phy->type = e1000_phy_ife;
588	phy->autoneg_mask = E1000_ALL_NOT_GIG;
589	phy->ops.get_info = e1000_get_phy_info_ife;
590	phy->ops.check_polarity = e1000_check_polarity_ife;
591	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
592	break;
593	case BME1000_E_PHY_ID:
594	phy->type = e1000_phy_bm;
595	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
596	phy->ops.read_reg = e1000e_read_phy_reg_bm;
597	phy->ops.write_reg = e1000e_write_phy_reg_bm;
598	phy->ops.commit = e1000e_phy_sw_reset;
599	phy->ops.get_info = e1000e_get_phy_info_m88;
600	phy->ops.check_polarity = e1000_check_polarity_m88;
601	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
602	break;
603	default:
604	return -E1000_ERR_PHY;
605	}
606
607	return 0;
608	}
609
610	/**
611	* e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
612	* @hw: pointer to the HW structure
613	*
614	* Initialize family-specific NVM parameters and function
615	* pointers.
616	**/
617	static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
618	{
619	struct e1000_nvm_info *nvm = &hw->nvm;
620	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
621	u32 gfpreg, sector_base_addr, sector_end_addr;
622	u16 i;
623	u32 nvm_size;
624
625	nvm->type = e1000_nvm_flash_sw;
626
627	if (hw->mac.type >= e1000_pch_spt) {
628	/* in SPT, gfpreg doesn't exist. NVM size is taken from the
629	* STRAP register. This is because in SPT the GbE Flash region
630	* is no longer accessed through the flash registers. Instead,
631	* the mechanism has changed, and the Flash region access
632	* registers are now implemented in GbE memory space.
633	*/
634	nvm->flash_base_addr = 0;
635	nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
636	* NVM_SIZE_MULTIPLIER;
637	nvm->flash_bank_size = nvm_size / 2;
638	/* Adjust to word count */
639	nvm->flash_bank_size /= sizeof(u16);
640	/* Set the base address for flash register access */
641	hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
642	} else {
643	/* Can't read flash registers if register set isn't mapped. */
644	if (!hw->flash_address) {
645	e_dbg("ERROR: Flash registers not mapped\n");
646	return -E1000_ERR_CONFIG;
647	}
648
649	gfpreg = er32flash(ICH_FLASH_GFPREG);
650
651	/* sector_X_addr is a "sector"-aligned address (4096 bytes)
652	* Add 1 to sector_end_addr since this sector is included in
653	* the overall size.
654	*/
655	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
656	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
657
658	/* flash_base_addr is byte-aligned */
659	nvm->flash_base_addr = sector_base_addr
660	<< FLASH_SECTOR_ADDR_SHIFT;
661
662	/* find total size of the NVM, then cut in half since the total
663	* size represents two separate NVM banks.
664	*/
665	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
666	<< FLASH_SECTOR_ADDR_SHIFT);
667	nvm->flash_bank_size /= 2;
668	/* Adjust to word count */
669	nvm->flash_bank_size /= sizeof(u16);
670	}
671
672	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
673
674	/* Clear shadow ram */
675	for (i = 0; i < nvm->word_size; i++) {
676	dev_spec->shadow_ram[i].modified = false;
677	dev_spec->shadow_ram[i].value = 0xFFFF;
678	}
679
680	return 0;
681	}
682
683	/**
684	* e1000_init_mac_params_ich8lan - Initialize MAC function pointers
685	* @hw: pointer to the HW structure
686	*
687	* Initialize family-specific MAC parameters and function
688	* pointers.
689	**/
690	static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
691	{
692	struct e1000_mac_info *mac = &hw->mac;
693
694	/* Set media type function pointer */
695	hw->phy.media_type = e1000_media_type_copper;
696
697	/* Set mta register count */
698	mac->mta_reg_count = 32;
699	/* Set rar entry count */
700	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
701	if (mac->type == e1000_ich8lan)
702	mac->rar_entry_count--;
703	/* FWSM register */
704	mac->has_fwsm = true;
705	/* ARC subsystem not supported */
706	mac->arc_subsystem_valid = false;
707	/* Adaptive IFS supported */
708	mac->adaptive_ifs = true;
709
710	/* LED and other operations */
711	switch (mac->type) {
712	case e1000_ich8lan:
713	case e1000_ich9lan:
714	case e1000_ich10lan:
715	/* check management mode */
716	mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
717	/* ID LED init */
718	mac->ops.id_led_init = e1000e_id_led_init_generic;
719	/* blink LED */
720	mac->ops.blink_led = e1000e_blink_led_generic;
721	/* setup LED */
722	mac->ops.setup_led = e1000e_setup_led_generic;
723	/* cleanup LED */
724	mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
725	/* turn on/off LED */
726	mac->ops.led_on = e1000_led_on_ich8lan;
727	mac->ops.led_off = e1000_led_off_ich8lan;
728	break;
729	case e1000_pch2lan:
730	mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
731	mac->ops.rar_set = e1000_rar_set_pch2lan;
732	fallthrough;
733	case e1000_pch_lpt:
734	case e1000_pch_spt:
735	case e1000_pch_cnp:
736	case e1000_pch_tgp:
737	case e1000_pch_adp:
738	case e1000_pch_mtp:
739	case e1000_pch_lnp:
740	case e1000_pch_ptp:
741	case e1000_pch_nvp:
742	case e1000_pchlan:
743	/* check management mode */
744	mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
745	/* ID LED init */
746	mac->ops.id_led_init = e1000_id_led_init_pchlan;
747	/* setup LED */
748	mac->ops.setup_led = e1000_setup_led_pchlan;
749	/* cleanup LED */
750	mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
751	/* turn on/off LED */
752	mac->ops.led_on = e1000_led_on_pchlan;
753	mac->ops.led_off = e1000_led_off_pchlan;
754	break;
755	default:
756	break;
757	}
758
759	if (mac->type >= e1000_pch_lpt) {
760	mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
761	mac->ops.rar_set = e1000_rar_set_pch_lpt;
762	mac->ops.setup_physical_interface =
763	e1000_setup_copper_link_pch_lpt;
764	mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
765	}
766
767	/* Enable PCS Lock-loss workaround for ICH8 */
768	if (mac->type == e1000_ich8lan)
769	e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, state: true);
770
771	return 0;
772	}
773
774	/**
775	* __e1000_access_emi_reg_locked - Read/write EMI register
776	* @hw: pointer to the HW structure
777	* @address: EMI address to program
778	* @data: pointer to value to read/write from/to the EMI address
779	* @read: boolean flag to indicate read or write
780	*
781	* This helper function assumes the SW/FW/HW Semaphore is already acquired.
782	**/
783	static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
784	u16 *data, bool read)
785	{
786	s32 ret_val;
787
788	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, data: address);
789	if (ret_val)
790	return ret_val;
791
792	if (read)
793	ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
794	else
795	ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, data: *data);
796
797	return ret_val;
798	}
799
800	/**
801	* e1000_read_emi_reg_locked - Read Extended Management Interface register
802	* @hw: pointer to the HW structure
803	* @addr: EMI address to program
804	* @data: value to be read from the EMI address
805	*
806	* Assumes the SW/FW/HW Semaphore is already acquired.
807	**/
808	s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
809	{
810	return __e1000_access_emi_reg_locked(hw, address: addr, data, read: true);
811	}
812
813	/**
814	* e1000_write_emi_reg_locked - Write Extended Management Interface register
815	* @hw: pointer to the HW structure
816	* @addr: EMI address to program
817	* @data: value to be written to the EMI address
818	*
819	* Assumes the SW/FW/HW Semaphore is already acquired.
820	**/
821	s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
822	{
823	return __e1000_access_emi_reg_locked(hw, address: addr, data: &data, read: false);
824	}
825
826	/**
827	* e1000_set_eee_pchlan - Enable/disable EEE support
828	* @hw: pointer to the HW structure
829	*
830	* Enable/disable EEE based on setting in dev_spec structure, the duplex of
831	* the link and the EEE capabilities of the link partner. The LPI Control
832	* register bits will remain set only if/when link is up.
833	*
834	* EEE LPI must not be asserted earlier than one second after link is up.
835	* On 82579, EEE LPI should not be enabled until such time otherwise there
836	* can be link issues with some switches. Other devices can have EEE LPI
837	* enabled immediately upon link up since they have a timer in hardware which
838	* prevents LPI from being asserted too early.
839	**/
840	s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
841	{
842	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
843	s32 ret_val;
844	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
845
846	switch (hw->phy.type) {
847	case e1000_phy_82579:
848	lpa = I82579_EEE_LP_ABILITY;
849	pcs_status = I82579_EEE_PCS_STATUS;
850	adv_addr = I82579_EEE_ADVERTISEMENT;
851	break;
852	case e1000_phy_i217:
853	lpa = I217_EEE_LP_ABILITY;
854	pcs_status = I217_EEE_PCS_STATUS;
855	adv_addr = I217_EEE_ADVERTISEMENT;
856	break;
857	default:
858	return 0;
859	}
860
861	ret_val = hw->phy.ops.acquire(hw);
862	if (ret_val)
863	return ret_val;
864
865	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, data: &lpi_ctrl);
866	if (ret_val)
867	goto release;
868
869	/* Clear bits that enable EEE in various speeds */
870	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
871
872	/* Enable EEE if not disabled by user */
873	if (!dev_spec->eee_disable) {
874	/* Save off link partner's EEE ability */
875	ret_val = e1000_read_emi_reg_locked(hw, addr: lpa,
876	data: &dev_spec->eee_lp_ability);
877	if (ret_val)
878	goto release;
879
880	/* Read EEE advertisement */
881	ret_val = e1000_read_emi_reg_locked(hw, addr: adv_addr, data: &adv);
882	if (ret_val)
883	goto release;
884
885	/* Enable EEE only for speeds in which the link partner is
886	* EEE capable and for which we advertise EEE.
887	*/
888	if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
889	lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
890
891	if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
892	e1e_rphy_locked(hw, MII_LPA, data: &data);
893	if (data & LPA_100FULL)
894	lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
895	else
896	/* EEE is not supported in 100Half, so ignore
897	* partner's EEE in 100 ability if full-duplex
898	* is not advertised.
899	*/
900	dev_spec->eee_lp_ability &=
901	~I82579_EEE_100_SUPPORTED;
902	}
903	}
904
905	if (hw->phy.type == e1000_phy_82579) {
906	ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
907	data: &data);
908	if (ret_val)
909	goto release;
910
911	data &= ~I82579_LPI_100_PLL_SHUT;
912	ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
913	data);
914	}
915
916	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
917	ret_val = e1000_read_emi_reg_locked(hw, addr: pcs_status, data: &data);
918	if (ret_val)
919	goto release;
920
921	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, data: lpi_ctrl);
922	release:
923	hw->phy.ops.release(hw);
924
925	return ret_val;
926	}
927
928	/**
929	* e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
930	* @hw: pointer to the HW structure
931	* @link: link up bool flag
932	*
933	* When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
934	* preventing further DMA write requests. Workaround the issue by disabling
935	* the de-assertion of the clock request when in 1Gpbs mode.
936	* Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
937	* speeds in order to avoid Tx hangs.
938	**/
939	static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
940	{
941	u32 fextnvm6 = er32(FEXTNVM6);
942	u32 status = er32(STATUS);
943	s32 ret_val = 0;
944	u16 reg;
945
946	if (link && (status & E1000_STATUS_SPEED_1000)) {
947	ret_val = hw->phy.ops.acquire(hw);
948	if (ret_val)
949	return ret_val;
950
951	ret_val =
952	e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
953	data: &reg);
954	if (ret_val)
955	goto release;
956
957	ret_val =
958	e1000e_write_kmrn_reg_locked(hw,
959	E1000_KMRNCTRLSTA_K1_CONFIG,
960	data: reg &
961	~E1000_KMRNCTRLSTA_K1_ENABLE);
962	if (ret_val)
963	goto release;
964
965	usleep_range(min: 10, max: 20);
966
967	ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
968
969	ret_val =
970	e1000e_write_kmrn_reg_locked(hw,
971	E1000_KMRNCTRLSTA_K1_CONFIG,
972	data: reg);
973	release:
974	hw->phy.ops.release(hw);
975	} else {
976	/* clear FEXTNVM6 bit 8 on link down or 10/100 */
977	fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
978
979	if ((hw->phy.revision > 5) || !link ||
980	((status & E1000_STATUS_SPEED_100) &&
981	(status & E1000_STATUS_FD)))
982	goto update_fextnvm6;
983
984	ret_val = e1e_rphy(hw, I217_INBAND_CTRL, data: &reg);
985	if (ret_val)
986	return ret_val;
987
988	/* Clear link status transmit timeout */
989	reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
990
991	if (status & E1000_STATUS_SPEED_100) {
992	/* Set inband Tx timeout to 5x10us for 100Half */
993	reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
994
995	/* Do not extend the K1 entry latency for 100Half */
996	fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
997	} else {
998	/* Set inband Tx timeout to 50x10us for 10Full/Half */
999	reg |= 50 <<
1000	I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1001
1002	/* Extend the K1 entry latency for 10 Mbps */
1003	fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1004	}
1005
1006	ret_val = e1e_wphy(hw, I217_INBAND_CTRL, data: reg);
1007	if (ret_val)
1008	return ret_val;
1009
1010	update_fextnvm6:
1011	ew32(FEXTNVM6, fextnvm6);
1012	}
1013
1014	return ret_val;
1015	}
1016
1017	/**
1018	* e1000_platform_pm_pch_lpt - Set platform power management values
1019	* @hw: pointer to the HW structure
1020	* @link: bool indicating link status
1021	*
1022	* Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1023	* GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1024	* when link is up (which must not exceed the maximum latency supported
1025	* by the platform), otherwise specify there is no LTR requirement.
1026	* Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1027	* latencies in the LTR Extended Capability Structure in the PCIe Extended
1028	* Capability register set, on this device LTR is set by writing the
1029	* equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1030	* set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1031	* message to the PMC.
1032	**/
1033	static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1034	{
1035	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1036	link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1037	u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1038	u32 lat_enc_d = 0; /* latency decoded */
1039	u16 lat_enc = 0; /* latency encoded */
1040
1041	if (link) {
1042	u16 speed, duplex, scale = 0;
1043	u16 max_snoop, max_nosnoop;
1044	u16 max_ltr_enc; /* max LTR latency encoded */
1045	u64 value;
1046	u32 rxa;
1047
1048	if (!hw->adapter->max_frame_size) {
1049	e_dbg("max_frame_size not set.\n");
1050	return -E1000_ERR_CONFIG;
1051	}
1052
1053	hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1054	if (!speed) {
1055	e_dbg("Speed not set.\n");
1056	return -E1000_ERR_CONFIG;
1057	}
1058
1059	/* Rx Packet Buffer Allocation size (KB) */
1060	rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1061
1062	/* Determine the maximum latency tolerated by the device.
1063	*
1064	* Per the PCIe spec, the tolerated latencies are encoded as
1065	* a 3-bit encoded scale (only 0-5 are valid) multiplied by
1066	* a 10-bit value (0-1023) to provide a range from 1 ns to
1067	* 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1068	* 1=2^5ns, 2=2^10ns,...5=2^25ns.
1069	*/
1070	rxa *= 512;
1071	value = (rxa > hw->adapter->max_frame_size) ?
1072	(rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1073	0;
1074
1075	while (value > PCI_LTR_VALUE_MASK) {
1076	scale++;
1077	value = DIV_ROUND_UP(value, BIT(5));
1078	}
1079	if (scale > E1000_LTRV_SCALE_MAX) {
1080	e_dbg("Invalid LTR latency scale %d\n", scale);
1081	return -E1000_ERR_CONFIG;
1082	}
1083	lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1084
1085	/* Determine the maximum latency tolerated by the platform */
1086	pci_read_config_word(dev: hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1087	val: &max_snoop);
1088	pci_read_config_word(dev: hw->adapter->pdev,
1089	E1000_PCI_LTR_CAP_LPT + 2, val: &max_nosnoop);
1090	max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1091
1092	lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1093	(1U << (E1000_LTRV_SCALE_FACTOR *
1094	FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc)));
1095
1096	max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1097	(1U << (E1000_LTRV_SCALE_FACTOR *
1098	FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc)));
1099
1100	if (lat_enc_d > max_ltr_enc_d)
1101	lat_enc = max_ltr_enc;
1102	}
1103
1104	/* Set Snoop and No-Snoop latencies the same */
1105	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1106	ew32(LTRV, reg);
1107
1108	return 0;
1109	}
1110
1111	/**
1112	* e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1113	* @hw: pointer to the HW structure
1114	* @to_sx: boolean indicating a system power state transition to Sx
1115	*
1116	* When link is down, configure ULP mode to significantly reduce the power
1117	* to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1118	* ME firmware to start the ULP configuration. If not on an ME enabled
1119	* system, configure the ULP mode by software.
1120	*/
1121	s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1122	{
1123	u32 mac_reg;
1124	s32 ret_val = 0;
1125	u16 phy_reg;
1126	u16 oem_reg = 0;
1127
1128	if ((hw->mac.type < e1000_pch_lpt) ||
1129	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1130	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1131	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1132	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1133	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1134	return 0;
1135
1136	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1137	/* Request ME configure ULP mode in the PHY */
1138	mac_reg = er32(H2ME);
1139	mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1140	ew32(H2ME, mac_reg);
1141
1142	goto out;
1143	}
1144
1145	if (!to_sx) {
1146	int i = 0;
1147
1148	/* Poll up to 5 seconds for Cable Disconnected indication */
1149	while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1150	/* Bail if link is re-acquired */
1151	if (er32(STATUS) & E1000_STATUS_LU)
1152	return -E1000_ERR_PHY;
1153
1154	if (i++ == 100)
1155	break;
1156
1157	msleep(msecs: 50);
1158	}
1159	e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1160	(er32(FEXT) &
1161	E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1162	}
1163
1164	ret_val = hw->phy.ops.acquire(hw);
1165	if (ret_val)
1166	goto out;
1167
1168	/* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1169	* LPLU and disable Gig speed when entering ULP
1170	*/
1171	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1172	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1173	data: &oem_reg);
1174	if (ret_val)
1175	goto release;
1176
1177	phy_reg = oem_reg;
1178	phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1179
1180	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1181	data: phy_reg);
1182
1183	if (ret_val)
1184	goto release;
1185	}
1186
1187	/* Set Inband ULP Exit, Reset to SMBus mode and
1188	* Disable SMBus Release on PERST# in PHY
1189	*/
1190	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: &phy_reg);
1191	if (ret_val)
1192	goto release;
1193	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1195	if (to_sx) {
1196	if (er32(WUFC) & E1000_WUFC_LNKC)
1197	phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1198	else
1199	phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200
1201	phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202	phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1203	} else {
1204	phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205	phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206	phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1207	}
1208	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1209
1210	/* Set Disable SMBus Release on PERST# in MAC */
1211	mac_reg = er32(FEXTNVM7);
1212	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213	ew32(FEXTNVM7, mac_reg);
1214
1215	/* Commit ULP changes in PHY by starting auto ULP configuration */
1216	phy_reg |= I218_ULP_CONFIG1_START;
1217	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1218
1219	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1220	to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1221	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1222	data: oem_reg);
1223	if (ret_val)
1224	goto release;
1225	}
1226
1227	release:
1228	hw->phy.ops.release(hw);
1229	out:
1230	if (ret_val)
1231	e_dbg("Error in ULP enable flow: %d\n", ret_val);
1232	else
1233	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1234
1235	return ret_val;
1236	}
1237
1238	/**
1239	* e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1240	* @hw: pointer to the HW structure
1241	* @force: boolean indicating whether or not to force disabling ULP
1242	*
1243	* Un-configure ULP mode when link is up, the system is transitioned from
1244	* Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1245	* system, poll for an indication from ME that ULP has been un-configured.
1246	* If not on an ME enabled system, un-configure the ULP mode by software.
1247	*
1248	* During nominal operation, this function is called when link is acquired
1249	* to disable ULP mode (force=false); otherwise, for example when unloading
1250	* the driver or during Sx->S0 transitions, this is called with force=true
1251	* to forcibly disable ULP.
1252	*/
1253	static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1254	{
1255	s32 ret_val = 0;
1256	u32 mac_reg;
1257	u16 phy_reg;
1258	int i = 0;
1259
1260	if ((hw->mac.type < e1000_pch_lpt) ||
1261	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1262	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1263	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1264	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1265	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1266	return 0;
1267
1268	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1269	struct e1000_adapter *adapter = hw->adapter;
1270	bool firmware_bug = false;
1271
1272	if (force) {
1273	/* Request ME un-configure ULP mode in the PHY */
1274	mac_reg = er32(H2ME);
1275	mac_reg &= ~E1000_H2ME_ULP;
1276	mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1277	ew32(H2ME, mac_reg);
1278	}
1279
1280	/* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1281	* If this takes more than 1 second, show a warning indicating a
1282	* firmware bug
1283	*/
1284	while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1285	if (i++ == 250) {
1286	ret_val = -E1000_ERR_PHY;
1287	goto out;
1288	}
1289	if (i > 100 && !firmware_bug)
1290	firmware_bug = true;
1291
1292	usleep_range(min: 10000, max: 11000);
1293	}
1294	if (firmware_bug)
1295	e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1296	i * 10);
1297	else
1298	e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1299	i * 10);
1300
1301	if (force) {
1302	mac_reg = er32(H2ME);
1303	mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1304	ew32(H2ME, mac_reg);
1305	} else {
1306	/* Clear H2ME.ULP after ME ULP configuration */
1307	mac_reg = er32(H2ME);
1308	mac_reg &= ~E1000_H2ME_ULP;
1309	ew32(H2ME, mac_reg);
1310	}
1311
1312	goto out;
1313	}
1314
1315	ret_val = hw->phy.ops.acquire(hw);
1316	if (ret_val)
1317	goto out;
1318
1319	if (force)
1320	/* Toggle LANPHYPC Value bit */
1321	e1000_toggle_lanphypc_pch_lpt(hw);
1322
1323	/* Switching PHY interface always returns MDI error
1324	* so disable retry mechanism to avoid wasting time
1325	*/
1326	e1000e_disable_phy_retry(hw);
1327
1328	/* Unforce SMBus mode in PHY */
1329	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: &phy_reg);
1330	if (ret_val) {
1331	/* The MAC might be in PCIe mode, so temporarily force to
1332	* SMBus mode in order to access the PHY.
1333	*/
1334	mac_reg = er32(CTRL_EXT);
1335	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1336	ew32(CTRL_EXT, mac_reg);
1337
1338	msleep(msecs: 50);
1339
1340	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1341	data: &phy_reg);
1342	if (ret_val)
1343	goto release;
1344	}
1345	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1346	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: phy_reg);
1347
1348	e1000e_enable_phy_retry(hw);
1349
1350	/* Unforce SMBus mode in MAC */
1351	mac_reg = er32(CTRL_EXT);
1352	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1353	ew32(CTRL_EXT, mac_reg);
1354
1355	/* When ULP mode was previously entered, K1 was disabled by the
1356	* hardware. Re-Enable K1 in the PHY when exiting ULP.
1357	*/
1358	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, data: &phy_reg);
1359	if (ret_val)
1360	goto release;
1361	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1362	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, data: phy_reg);
1363
1364	/* Clear ULP enabled configuration */
1365	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: &phy_reg);
1366	if (ret_val)
1367	goto release;
1368	phy_reg &= ~(I218_ULP_CONFIG1_IND |
1369	I218_ULP_CONFIG1_STICKY_ULP |
1370	I218_ULP_CONFIG1_RESET_TO_SMBUS |
1371	I218_ULP_CONFIG1_WOL_HOST |
1372	I218_ULP_CONFIG1_INBAND_EXIT |
1373	I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1374	I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1375	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1376	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1377
1378	/* Commit ULP changes by starting auto ULP configuration */
1379	phy_reg |= I218_ULP_CONFIG1_START;
1380	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1381
1382	/* Clear Disable SMBus Release on PERST# in MAC */
1383	mac_reg = er32(FEXTNVM7);
1384	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1385	ew32(FEXTNVM7, mac_reg);
1386
1387	release:
1388	hw->phy.ops.release(hw);
1389	if (force) {
1390	e1000_phy_hw_reset(hw);
1391	msleep(msecs: 50);
1392	}
1393	out:
1394	if (ret_val)
1395	e_dbg("Error in ULP disable flow: %d\n", ret_val);
1396	else
1397	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1398
1399	return ret_val;
1400	}
1401
1402	/**
1403	* e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1404	* @hw: pointer to the HW structure
1405	*
1406	* Checks to see of the link status of the hardware has changed. If a
1407	* change in link status has been detected, then we read the PHY registers
1408	* to get the current speed/duplex if link exists.
1409	**/
1410	static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1411	{
1412	struct e1000_mac_info *mac = &hw->mac;
1413	s32 ret_val, tipg_reg = 0;
1414	u16 emi_addr, emi_val = 0;
1415	bool link;
1416	u16 phy_reg;
1417
1418	/* We only want to go out to the PHY registers to see if Auto-Neg
1419	* has completed and/or if our link status has changed. The
1420	* get_link_status flag is set upon receiving a Link Status
1421	* Change or Rx Sequence Error interrupt.
1422	*/
1423	if (!mac->get_link_status)
1424	return 0;
1425	mac->get_link_status = false;
1426
1427	/* First we want to see if the MII Status Register reports
1428	* link. If so, then we want to get the current speed/duplex
1429	* of the PHY.
1430	*/
1431	ret_val = e1000e_phy_has_link_generic(hw, iterations: 1, usec_interval: 0, success: &link);
1432	if (ret_val)
1433	goto out;
1434
1435	if (hw->mac.type == e1000_pchlan) {
1436	ret_val = e1000_k1_gig_workaround_hv(hw, link);
1437	if (ret_val)
1438	goto out;
1439	}
1440
1441	/* When connected at 10Mbps half-duplex, some parts are excessively
1442	* aggressive resulting in many collisions. To avoid this, increase
1443	* the IPG and reduce Rx latency in the PHY.
1444	*/
1445	if ((hw->mac.type >= e1000_pch2lan) && link) {
1446	u16 speed, duplex;
1447
1448	e1000e_get_speed_and_duplex_copper(hw, speed: &speed, duplex: &duplex);
1449	tipg_reg = er32(TIPG);
1450	tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1451
1452	if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1453	tipg_reg |= 0xFF;
1454	/* Reduce Rx latency in analog PHY */
1455	emi_val = 0;
1456	} else if (hw->mac.type >= e1000_pch_spt &&
1457	duplex == FULL_DUPLEX && speed != SPEED_1000) {
1458	tipg_reg |= 0xC;
1459	emi_val = 1;
1460	} else {
1461
1462	/* Roll back the default values */
1463	tipg_reg |= 0x08;
1464	emi_val = 1;
1465	}
1466
1467	ew32(TIPG, tipg_reg);
1468
1469	ret_val = hw->phy.ops.acquire(hw);
1470	if (ret_val)
1471	goto out;
1472
1473	if (hw->mac.type == e1000_pch2lan)
1474	emi_addr = I82579_RX_CONFIG;
1475	else
1476	emi_addr = I217_RX_CONFIG;
1477	ret_val = e1000_write_emi_reg_locked(hw, addr: emi_addr, data: emi_val);
1478
1479	if (hw->mac.type >= e1000_pch_lpt) {
1480	u16 phy_reg;
1481
1482	e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, data: &phy_reg);
1483	phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1484	if (speed == SPEED_100 || speed == SPEED_10)
1485	phy_reg |= 0x3E8;
1486	else
1487	phy_reg |= 0xFA;
1488	e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, data: phy_reg);
1489
1490	if (speed == SPEED_1000) {
1491	hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1492	&phy_reg);
1493
1494	phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1495
1496	hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1497	phy_reg);
1498	}
1499	}
1500	hw->phy.ops.release(hw);
1501
1502	if (ret_val)
1503	goto out;
1504
1505	if (hw->mac.type >= e1000_pch_spt) {
1506	u16 data;
1507	u16 ptr_gap;
1508
1509	if (speed == SPEED_1000) {
1510	ret_val = hw->phy.ops.acquire(hw);
1511	if (ret_val)
1512	goto out;
1513
1514	ret_val = e1e_rphy_locked(hw,
1515	PHY_REG(776, 20),
1516	data: &data);
1517	if (ret_val) {
1518	hw->phy.ops.release(hw);
1519	goto out;
1520	}
1521
1522	ptr_gap = (data & (0x3FF << 2)) >> 2;
1523	if (ptr_gap < 0x18) {
1524	data &= ~(0x3FF << 2);
1525	data |= (0x18 << 2);
1526	ret_val =
1527	e1e_wphy_locked(hw,
1528	PHY_REG(776, 20),
1529	data);
1530	}
1531	hw->phy.ops.release(hw);
1532	if (ret_val)
1533	goto out;
1534	} else {
1535	ret_val = hw->phy.ops.acquire(hw);
1536	if (ret_val)
1537	goto out;
1538
1539	ret_val = e1e_wphy_locked(hw,
1540	PHY_REG(776, 20),
1541	data: 0xC023);
1542	hw->phy.ops.release(hw);
1543	if (ret_val)
1544	goto out;
1545
1546	}
1547	}
1548	}
1549
1550	/* I217 Packet Loss issue:
1551	* ensure that FEXTNVM4 Beacon Duration is set correctly
1552	* on power up.
1553	* Set the Beacon Duration for I217 to 8 usec
1554	*/
1555	if (hw->mac.type >= e1000_pch_lpt) {
1556	u32 mac_reg;
1557
1558	mac_reg = er32(FEXTNVM4);
1559	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1560	mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1561	ew32(FEXTNVM4, mac_reg);
1562	}
1563
1564	/* Work-around I218 hang issue */
1565	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1566	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1567	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1568	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1569	ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1570	if (ret_val)
1571	goto out;
1572	}
1573	if (hw->mac.type >= e1000_pch_lpt) {
1574	/* Set platform power management values for
1575	* Latency Tolerance Reporting (LTR)
1576	*/
1577	ret_val = e1000_platform_pm_pch_lpt(hw, link);
1578	if (ret_val)
1579	goto out;
1580	}
1581
1582	/* Clear link partner's EEE ability */
1583	hw->dev_spec.ich8lan.eee_lp_ability = 0;
1584
1585	if (hw->mac.type >= e1000_pch_lpt) {
1586	u32 fextnvm6 = er32(FEXTNVM6);
1587
1588	if (hw->mac.type == e1000_pch_spt) {
1589	/* FEXTNVM6 K1-off workaround - for SPT only */
1590	u32 pcieanacfg = er32(PCIEANACFG);
1591
1592	if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1593	fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1594	else
1595	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1596	}
1597
1598	ew32(FEXTNVM6, fextnvm6);
1599	}
1600
1601	if (!link)
1602	goto out;
1603
1604	switch (hw->mac.type) {
1605	case e1000_pch2lan:
1606	ret_val = e1000_k1_workaround_lv(hw);
1607	if (ret_val)
1608	return ret_val;
1609	fallthrough;
1610	case e1000_pchlan:
1611	if (hw->phy.type == e1000_phy_82578) {
1612	ret_val = e1000_link_stall_workaround_hv(hw);
1613	if (ret_val)
1614	return ret_val;
1615	}
1616
1617	/* Workaround for PCHx parts in half-duplex:
1618	* Set the number of preambles removed from the packet
1619	* when it is passed from the PHY to the MAC to prevent
1620	* the MAC from misinterpreting the packet type.
1621	*/
1622	e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, data: &phy_reg);
1623	phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1624
1625	if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1626	phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1627
1628	e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, data: phy_reg);
1629	break;
1630	default:
1631	break;
1632	}
1633
1634	/* Check if there was DownShift, must be checked
1635	* immediately after link-up
1636	*/
1637	e1000e_check_downshift(hw);
1638
1639	/* Enable/Disable EEE after link up */
1640	if (hw->phy.type > e1000_phy_82579) {
1641	ret_val = e1000_set_eee_pchlan(hw);
1642	if (ret_val)
1643	return ret_val;
1644	}
1645
1646	/* If we are forcing speed/duplex, then we simply return since
1647	* we have already determined whether we have link or not.
1648	*/
1649	if (!mac->autoneg)
1650	return -E1000_ERR_CONFIG;
1651
1652	/* Auto-Neg is enabled. Auto Speed Detection takes care
1653	* of MAC speed/duplex configuration. So we only need to
1654	* configure Collision Distance in the MAC.
1655	*/
1656	mac->ops.config_collision_dist(hw);
1657
1658	/* Configure Flow Control now that Auto-Neg has completed.
1659	* First, we need to restore the desired flow control
1660	* settings because we may have had to re-autoneg with a
1661	* different link partner.
1662	*/
1663	ret_val = e1000e_config_fc_after_link_up(hw);
1664	if (ret_val)
1665	e_dbg("Error configuring flow control\n");
1666
1667	return ret_val;
1668
1669	out:
1670	mac->get_link_status = true;
1671	return ret_val;
1672	}
1673
1674	static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1675	{
1676	struct e1000_hw *hw = &adapter->hw;
1677	s32 rc;
1678
1679	rc = e1000_init_mac_params_ich8lan(hw);
1680	if (rc)
1681	return rc;
1682
1683	rc = e1000_init_nvm_params_ich8lan(hw);
1684	if (rc)
1685	return rc;
1686
1687	switch (hw->mac.type) {
1688	case e1000_ich8lan:
1689	case e1000_ich9lan:
1690	case e1000_ich10lan:
1691	rc = e1000_init_phy_params_ich8lan(hw);
1692	break;
1693	case e1000_pchlan:
1694	case e1000_pch2lan:
1695	case e1000_pch_lpt:
1696	case e1000_pch_spt:
1697	case e1000_pch_cnp:
1698	case e1000_pch_tgp:
1699	case e1000_pch_adp:
1700	case e1000_pch_mtp:
1701	case e1000_pch_lnp:
1702	case e1000_pch_ptp:
1703	case e1000_pch_nvp:
1704	rc = e1000_init_phy_params_pchlan(hw);
1705	break;
1706	default:
1707	break;
1708	}
1709	if (rc)
1710	return rc;
1711
1712	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1713	* on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1714	*/
1715	if ((adapter->hw.phy.type == e1000_phy_ife) ||
1716	((adapter->hw.mac.type >= e1000_pch2lan) &&
1717	(!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1718	adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1719	adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1720
1721	hw->mac.ops.blink_led = NULL;
1722	}
1723
1724	if ((adapter->hw.mac.type == e1000_ich8lan) &&
1725	(adapter->hw.phy.type != e1000_phy_ife))
1726	adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1727
1728	/* Enable workaround for 82579 w/ ME enabled */
1729	if ((adapter->hw.mac.type == e1000_pch2lan) &&
1730	(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1731	adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1732
1733	return 0;
1734	}
1735
1736	static DEFINE_MUTEX(nvm_mutex);
1737
1738	/**
1739	* e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1740	* @hw: pointer to the HW structure
1741	*
1742	* Acquires the mutex for performing NVM operations.
1743	**/
1744	static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1745	{
1746	mutex_lock(&nvm_mutex);
1747
1748	return 0;
1749	}
1750
1751	/**
1752	* e1000_release_nvm_ich8lan - Release NVM mutex
1753	* @hw: pointer to the HW structure
1754	*
1755	* Releases the mutex used while performing NVM operations.
1756	**/
1757	static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1758	{
1759	mutex_unlock(lock: &nvm_mutex);
1760	}
1761
1762	/**
1763	* e1000_acquire_swflag_ich8lan - Acquire software control flag
1764	* @hw: pointer to the HW structure
1765	*
1766	* Acquires the software control flag for performing PHY and select
1767	* MAC CSR accesses.
1768	**/
1769	static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1770	{
1771	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1772	s32 ret_val = 0;
1773
1774	if (test_and_set_bit(nr: __E1000_ACCESS_SHARED_RESOURCE,
1775	addr: &hw->adapter->state)) {
1776	e_dbg("contention for Phy access\n");
1777	return -E1000_ERR_PHY;
1778	}
1779
1780	while (timeout) {
1781	extcnf_ctrl = er32(EXTCNF_CTRL);
1782	if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1783	break;
1784
1785	mdelay(1);
1786	timeout--;
1787	}
1788
1789	if (!timeout) {
1790	e_dbg("SW has already locked the resource.\n");
1791	ret_val = -E1000_ERR_CONFIG;
1792	goto out;
1793	}
1794
1795	timeout = SW_FLAG_TIMEOUT;
1796
1797	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1798	ew32(EXTCNF_CTRL, extcnf_ctrl);
1799
1800	while (timeout) {
1801	extcnf_ctrl = er32(EXTCNF_CTRL);
1802	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1803	break;
1804
1805	mdelay(1);
1806	timeout--;
1807	}
1808
1809	if (!timeout) {
1810	e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1811	er32(FWSM), extcnf_ctrl);
1812	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1813	ew32(EXTCNF_CTRL, extcnf_ctrl);
1814	ret_val = -E1000_ERR_CONFIG;
1815	goto out;
1816	}
1817
1818	out:
1819	if (ret_val)
1820	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
1821
1822	return ret_val;
1823	}
1824
1825	/**
1826	* e1000_release_swflag_ich8lan - Release software control flag
1827	* @hw: pointer to the HW structure
1828	*
1829	* Releases the software control flag for performing PHY and select
1830	* MAC CSR accesses.
1831	**/
1832	static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1833	{
1834	u32 extcnf_ctrl;
1835
1836	extcnf_ctrl = er32(EXTCNF_CTRL);
1837
1838	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1839	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1840	ew32(EXTCNF_CTRL, extcnf_ctrl);
1841	} else {
1842	e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1843	}
1844
1845	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
1846	}
1847
1848	/**
1849	* e1000_check_mng_mode_ich8lan - Checks management mode
1850	* @hw: pointer to the HW structure
1851	*
1852	* This checks if the adapter has any manageability enabled.
1853	* This is a function pointer entry point only called by read/write
1854	* routines for the PHY and NVM parts.
1855	**/
1856	static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1857	{
1858	u32 fwsm;
1859
1860	fwsm = er32(FWSM);
1861	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1862	((fwsm & E1000_FWSM_MODE_MASK) ==
1863	(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1864	}
1865
1866	/**
1867	* e1000_check_mng_mode_pchlan - Checks management mode
1868	* @hw: pointer to the HW structure
1869	*
1870	* This checks if the adapter has iAMT enabled.
1871	* This is a function pointer entry point only called by read/write
1872	* routines for the PHY and NVM parts.
1873	**/
1874	static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1875	{
1876	u32 fwsm;
1877
1878	fwsm = er32(FWSM);
1879	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1880	(fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1881	}
1882
1883	/**
1884	* e1000_rar_set_pch2lan - Set receive address register
1885	* @hw: pointer to the HW structure
1886	* @addr: pointer to the receive address
1887	* @index: receive address array register
1888	*
1889	* Sets the receive address array register at index to the address passed
1890	* in by addr. For 82579, RAR[0] is the base address register that is to
1891	* contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1892	* Use SHRA[0-3] in place of those reserved for ME.
1893	**/
1894	static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1895	{
1896	u32 rar_low, rar_high;
1897
1898	/* HW expects these in little endian so we reverse the byte order
1899	* from network order (big endian) to little endian
1900	*/
1901	rar_low = ((u32)addr[0] |
1902	((u32)addr[1] << 8) |
1903	((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1904
1905	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1906
1907	/* If MAC address zero, no need to set the AV bit */
1908	if (rar_low || rar_high)
1909	rar_high |= E1000_RAH_AV;
1910
1911	if (index == 0) {
1912	ew32(RAL(index), rar_low);
1913	e1e_flush();
1914	ew32(RAH(index), rar_high);
1915	e1e_flush();
1916	return 0;
1917	}
1918
1919	/* RAR[1-6] are owned by manageability. Skip those and program the
1920	* next address into the SHRA register array.
1921	*/
1922	if (index < (u32)(hw->mac.rar_entry_count)) {
1923	s32 ret_val;
1924
1925	ret_val = e1000_acquire_swflag_ich8lan(hw);
1926	if (ret_val)
1927	goto out;
1928
1929	ew32(SHRAL(index - 1), rar_low);
1930	e1e_flush();
1931	ew32(SHRAH(index - 1), rar_high);
1932	e1e_flush();
1933
1934	e1000_release_swflag_ich8lan(hw);
1935
1936	/* verify the register updates */
1937	if ((er32(SHRAL(index - 1)) == rar_low) &&
1938	(er32(SHRAH(index - 1)) == rar_high))
1939	return 0;
1940
1941	e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1942	(index - 1), er32(FWSM));
1943	}
1944
1945	out:
1946	e_dbg("Failed to write receive address at index %d\n", index);
1947	return -E1000_ERR_CONFIG;
1948	}
1949
1950	/**
1951	* e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1952	* @hw: pointer to the HW structure
1953	*
1954	* Get the number of available receive registers that the Host can
1955	* program. SHRA[0-10] are the shared receive address registers
1956	* that are shared between the Host and manageability engine (ME).
1957	* ME can reserve any number of addresses and the host needs to be
1958	* able to tell how many available registers it has access to.
1959	**/
1960	static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1961	{
1962	u32 wlock_mac;
1963	u32 num_entries;
1964
1965	wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1966	wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1967
1968	switch (wlock_mac) {
1969	case 0:
1970	/* All SHRA[0..10] and RAR[0] available */
1971	num_entries = hw->mac.rar_entry_count;
1972	break;
1973	case 1:
1974	/* Only RAR[0] available */
1975	num_entries = 1;
1976	break;
1977	default:
1978	/* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1979	num_entries = wlock_mac + 1;
1980	break;
1981	}
1982
1983	return num_entries;
1984	}
1985
1986	/**
1987	* e1000_rar_set_pch_lpt - Set receive address registers
1988	* @hw: pointer to the HW structure
1989	* @addr: pointer to the receive address
1990	* @index: receive address array register
1991	*
1992	* Sets the receive address register array at index to the address passed
1993	* in by addr. For LPT, RAR[0] is the base address register that is to
1994	* contain the MAC address. SHRA[0-10] are the shared receive address
1995	* registers that are shared between the Host and manageability engine (ME).
1996	**/
1997	static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1998	{
1999	u32 rar_low, rar_high;
2000	u32 wlock_mac;
2001
2002	/* HW expects these in little endian so we reverse the byte order
2003	* from network order (big endian) to little endian
2004	*/
2005	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
2006	((u32)addr[2] << 16) | ((u32)addr[3] << 24));
2007
2008	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
2009
2010	/* If MAC address zero, no need to set the AV bit */
2011	if (rar_low || rar_high)
2012	rar_high |= E1000_RAH_AV;
2013
2014	if (index == 0) {
2015	ew32(RAL(index), rar_low);
2016	e1e_flush();
2017	ew32(RAH(index), rar_high);
2018	e1e_flush();
2019	return 0;
2020	}
2021
2022	/* The manageability engine (ME) can lock certain SHRAR registers that
2023	* it is using - those registers are unavailable for use.
2024	*/
2025	if (index < hw->mac.rar_entry_count) {
2026	wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2027	wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2028
2029	/* Check if all SHRAR registers are locked */
2030	if (wlock_mac == 1)
2031	goto out;
2032
2033	if ((wlock_mac == 0) || (index <= wlock_mac)) {
2034	s32 ret_val;
2035
2036	ret_val = e1000_acquire_swflag_ich8lan(hw);
2037
2038	if (ret_val)
2039	goto out;
2040
2041	ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2042	e1e_flush();
2043	ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2044	e1e_flush();
2045
2046	e1000_release_swflag_ich8lan(hw);
2047
2048	/* verify the register updates */
2049	if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2050	(er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2051	return 0;
2052	}
2053	}
2054
2055	out:
2056	e_dbg("Failed to write receive address at index %d\n", index);
2057	return -E1000_ERR_CONFIG;
2058	}
2059
2060	/**
2061	* e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2062	* @hw: pointer to the HW structure
2063	*
2064	* Checks if firmware is blocking the reset of the PHY.
2065	* This is a function pointer entry point only called by
2066	* reset routines.
2067	**/
2068	static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2069	{
2070	bool blocked = false;
2071	int i = 0;
2072
2073	while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2074	(i++ < 30))
2075	usleep_range(min: 10000, max: 11000);
2076	return blocked ? E1000_BLK_PHY_RESET : 0;
2077	}
2078
2079	/**
2080	* e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2081	* @hw: pointer to the HW structure
2082	*
2083	* Assumes semaphore already acquired.
2084	*
2085	**/
2086	static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2087	{
2088	u16 phy_data;
2089	u32 strap = er32(STRAP);
2090	u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap);
2091	s32 ret_val;
2092
2093	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2094
2095	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, data: &phy_data);
2096	if (ret_val)
2097	return ret_val;
2098
2099	phy_data &= ~HV_SMB_ADDR_MASK;
2100	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2101	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2102
2103	if (hw->phy.type == e1000_phy_i217) {
2104	/* Restore SMBus frequency */
2105	if (freq--) {
2106	phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2107	phy_data |= (freq & BIT(0)) <<
2108	HV_SMB_ADDR_FREQ_LOW_SHIFT;
2109	phy_data |= (freq & BIT(1)) <<
2110	(HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2111	} else {
2112	e_dbg("Unsupported SMB frequency in PHY\n");
2113	}
2114	}
2115
2116	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, data: phy_data);
2117	}
2118
2119	/**
2120	* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2121	* @hw: pointer to the HW structure
2122	*
2123	* SW should configure the LCD from the NVM extended configuration region
2124	* as a workaround for certain parts.
2125	**/
2126	static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2127	{
2128	struct e1000_phy_info *phy = &hw->phy;
2129	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2130	s32 ret_val = 0;
2131	u16 word_addr, reg_data, reg_addr, phy_page = 0;
2132
2133	/* Initialize the PHY from the NVM on ICH platforms. This
2134	* is needed due to an issue where the NVM configuration is
2135	* not properly autoloaded after power transitions.
2136	* Therefore, after each PHY reset, we will load the
2137	* configuration data out of the NVM manually.
2138	*/
2139	switch (hw->mac.type) {
2140	case e1000_ich8lan:
2141	if (phy->type != e1000_phy_igp_3)
2142	return ret_val;
2143
2144	if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2145	(hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2146	sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2147	break;
2148	}
2149	fallthrough;
2150	case e1000_pchlan:
2151	case e1000_pch2lan:
2152	case e1000_pch_lpt:
2153	case e1000_pch_spt:
2154	case e1000_pch_cnp:
2155	case e1000_pch_tgp:
2156	case e1000_pch_adp:
2157	case e1000_pch_mtp:
2158	case e1000_pch_lnp:
2159	case e1000_pch_ptp:
2160	case e1000_pch_nvp:
2161	sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2162	break;
2163	default:
2164	return ret_val;
2165	}
2166
2167	ret_val = hw->phy.ops.acquire(hw);
2168	if (ret_val)
2169	return ret_val;
2170
2171	data = er32(FEXTNVM);
2172	if (!(data & sw_cfg_mask))
2173	goto release;
2174
2175	/* Make sure HW does not configure LCD from PHY
2176	* extended configuration before SW configuration
2177	*/
2178	data = er32(EXTCNF_CTRL);
2179	if ((hw->mac.type < e1000_pch2lan) &&
2180	(data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2181	goto release;
2182
2183	cnf_size = er32(EXTCNF_SIZE);
2184	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2185	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2186	if (!cnf_size)
2187	goto release;
2188
2189	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2190	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2191
2192	if (((hw->mac.type == e1000_pchlan) &&
2193	!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2194	(hw->mac.type > e1000_pchlan)) {
2195	/* HW configures the SMBus address and LEDs when the
2196	* OEM and LCD Write Enable bits are set in the NVM.
2197	* When both NVM bits are cleared, SW will configure
2198	* them instead.
2199	*/
2200	ret_val = e1000_write_smbus_addr(hw);
2201	if (ret_val)
2202	goto release;
2203
2204	data = er32(LEDCTL);
2205	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2206	data: (u16)data);
2207	if (ret_val)
2208	goto release;
2209	}
2210
2211	/* Configure LCD from extended configuration region. */
2212
2213	/* cnf_base_addr is in DWORD */
2214	word_addr = (u16)(cnf_base_addr << 1);
2215
2216	for (i = 0; i < cnf_size; i++) {
2217	ret_val = e1000_read_nvm(hw, offset: (word_addr + i * 2), words: 1, data: &reg_data);
2218	if (ret_val)
2219	goto release;
2220
2221	ret_val = e1000_read_nvm(hw, offset: (word_addr + i * 2 + 1),
2222	words: 1, data: &reg_addr);
2223	if (ret_val)
2224	goto release;
2225
2226	/* Save off the PHY page for future writes. */
2227	if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2228	phy_page = reg_data;
2229	continue;
2230	}
2231
2232	reg_addr &= PHY_REG_MASK;
2233	reg_addr |= phy_page;
2234
2235	ret_val = e1e_wphy_locked(hw, offset: (u32)reg_addr, data: reg_data);
2236	if (ret_val)
2237	goto release;
2238	}
2239
2240	release:
2241	hw->phy.ops.release(hw);
2242	return ret_val;
2243	}
2244
2245	/**
2246	* e1000_k1_gig_workaround_hv - K1 Si workaround
2247	* @hw: pointer to the HW structure
2248	* @link: link up bool flag
2249	*
2250	* If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2251	* from a lower speed. This workaround disables K1 whenever link is at 1Gig
2252	* If link is down, the function will restore the default K1 setting located
2253	* in the NVM.
2254	**/
2255	static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2256	{
2257	s32 ret_val = 0;
2258	u16 status_reg = 0;
2259	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2260
2261	if (hw->mac.type != e1000_pchlan)
2262	return 0;
2263
2264	/* Wrap the whole flow with the sw flag */
2265	ret_val = hw->phy.ops.acquire(hw);
2266	if (ret_val)
2267	return ret_val;
2268
2269	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2270	if (link) {
2271	if (hw->phy.type == e1000_phy_82578) {
2272	ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2273	data: &status_reg);
2274	if (ret_val)
2275	goto release;
2276
2277	status_reg &= (BM_CS_STATUS_LINK_UP |
2278	BM_CS_STATUS_RESOLVED |
2279	BM_CS_STATUS_SPEED_MASK);
2280
2281	if (status_reg == (BM_CS_STATUS_LINK_UP |
2282	BM_CS_STATUS_RESOLVED |
2283	BM_CS_STATUS_SPEED_1000))
2284	k1_enable = false;
2285	}
2286
2287	if (hw->phy.type == e1000_phy_82577) {
2288	ret_val = e1e_rphy_locked(hw, HV_M_STATUS, data: &status_reg);
2289	if (ret_val)
2290	goto release;
2291
2292	status_reg &= (HV_M_STATUS_LINK_UP |
2293	HV_M_STATUS_AUTONEG_COMPLETE |
2294	HV_M_STATUS_SPEED_MASK);
2295
2296	if (status_reg == (HV_M_STATUS_LINK_UP |
2297	HV_M_STATUS_AUTONEG_COMPLETE |
2298	HV_M_STATUS_SPEED_1000))
2299	k1_enable = false;
2300	}
2301
2302	/* Link stall fix for link up */
2303	ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), data: 0x0100);
2304	if (ret_val)
2305	goto release;
2306
2307	} else {
2308	/* Link stall fix for link down */
2309	ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), data: 0x4100);
2310	if (ret_val)
2311	goto release;
2312	}
2313
2314	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2315
2316	release:
2317	hw->phy.ops.release(hw);
2318
2319	return ret_val;
2320	}
2321
2322	/**
2323	* e1000_configure_k1_ich8lan - Configure K1 power state
2324	* @hw: pointer to the HW structure
2325	* @k1_enable: K1 state to configure
2326	*
2327	* Configure the K1 power state based on the provided parameter.
2328	* Assumes semaphore already acquired.
2329	*
2330	* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2331	**/
2332	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2333	{
2334	s32 ret_val;
2335	u32 ctrl_reg = 0;
2336	u32 ctrl_ext = 0;
2337	u32 reg = 0;
2338	u16 kmrn_reg = 0;
2339
2340	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2341	data: &kmrn_reg);
2342	if (ret_val)
2343	return ret_val;
2344
2345	if (k1_enable)
2346	kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2347	else
2348	kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2349
2350	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2351	data: kmrn_reg);
2352	if (ret_val)
2353	return ret_val;
2354
2355	usleep_range(min: 20, max: 40);
2356	ctrl_ext = er32(CTRL_EXT);
2357	ctrl_reg = er32(CTRL);
2358
2359	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2360	reg |= E1000_CTRL_FRCSPD;
2361	ew32(CTRL, reg);
2362
2363	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2364	e1e_flush();
2365	usleep_range(min: 20, max: 40);
2366	ew32(CTRL, ctrl_reg);
2367	ew32(CTRL_EXT, ctrl_ext);
2368	e1e_flush();
2369	usleep_range(min: 20, max: 40);
2370
2371	return 0;
2372	}
2373
2374	/**
2375	* e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2376	* @hw: pointer to the HW structure
2377	* @d0_state: boolean if entering d0 or d3 device state
2378	*
2379	* SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2380	* collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2381	* in NVM determines whether HW should configure LPLU and Gbe Disable.
2382	**/
2383	static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2384	{
2385	s32 ret_val = 0;
2386	u32 mac_reg;
2387	u16 oem_reg;
2388
2389	if (hw->mac.type < e1000_pchlan)
2390	return ret_val;
2391
2392	ret_val = hw->phy.ops.acquire(hw);
2393	if (ret_val)
2394	return ret_val;
2395
2396	if (hw->mac.type == e1000_pchlan) {
2397	mac_reg = er32(EXTCNF_CTRL);
2398	if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2399	goto release;
2400	}
2401
2402	mac_reg = er32(FEXTNVM);
2403	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2404	goto release;
2405
2406	mac_reg = er32(PHY_CTRL);
2407
2408	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, data: &oem_reg);
2409	if (ret_val)
2410	goto release;
2411
2412	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2413
2414	if (d0_state) {
2415	if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2416	oem_reg |= HV_OEM_BITS_GBE_DIS;
2417
2418	if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2419	oem_reg |= HV_OEM_BITS_LPLU;
2420	} else {
2421	if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2422	E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2423	oem_reg |= HV_OEM_BITS_GBE_DIS;
2424
2425	if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2426	E1000_PHY_CTRL_NOND0A_LPLU))
2427	oem_reg |= HV_OEM_BITS_LPLU;
2428	}
2429
2430	/* Set Restart auto-neg to activate the bits */
2431	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2432	!hw->phy.ops.check_reset_block(hw))
2433	oem_reg |= HV_OEM_BITS_RESTART_AN;
2434
2435	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, data: oem_reg);
2436
2437	release:
2438	hw->phy.ops.release(hw);
2439
2440	return ret_val;
2441	}
2442
2443	/**
2444	* e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2445	* @hw: pointer to the HW structure
2446	**/
2447	static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2448	{
2449	s32 ret_val;
2450	u16 data;
2451
2452	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, data: &data);
2453	if (ret_val)
2454	return ret_val;
2455
2456	data |= HV_KMRN_MDIO_SLOW;
2457
2458	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2459
2460	return ret_val;
2461	}
2462
2463	/**
2464	* e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2465	* @hw: pointer to the HW structure
2466	*
2467	* A series of PHY workarounds to be done after every PHY reset.
2468	**/
2469	static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2470	{
2471	s32 ret_val = 0;
2472	u16 phy_data;
2473
2474	if (hw->mac.type != e1000_pchlan)
2475	return 0;
2476
2477	/* Set MDIO slow mode before any other MDIO access */
2478	if (hw->phy.type == e1000_phy_82577) {
2479	ret_val = e1000_set_mdio_slow_mode_hv(hw);
2480	if (ret_val)
2481	return ret_val;
2482	}
2483
2484	if (((hw->phy.type == e1000_phy_82577) &&
2485	((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2486	((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2487	/* Disable generation of early preamble */
2488	ret_val = e1e_wphy(hw, PHY_REG(769, 25), data: 0x4431);
2489	if (ret_val)
2490	return ret_val;
2491
2492	/* Preamble tuning for SSC */
2493	ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, data: 0xA204);
2494	if (ret_val)
2495	return ret_val;
2496	}
2497
2498	if (hw->phy.type == e1000_phy_82578) {
2499	/* Return registers to default by doing a soft reset then
2500	* writing 0x3140 to the control register.
2501	*/
2502	if (hw->phy.revision < 2) {
2503	e1000e_phy_sw_reset(hw);
2504	ret_val = e1e_wphy(hw, MII_BMCR, data: 0x3140);
2505	if (ret_val)
2506	return ret_val;
2507	}
2508	}
2509
2510	/* Select page 0 */
2511	ret_val = hw->phy.ops.acquire(hw);
2512	if (ret_val)
2513	return ret_val;
2514
2515	hw->phy.addr = 1;
2516	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, data: 0);
2517	hw->phy.ops.release(hw);
2518	if (ret_val)
2519	return ret_val;
2520
2521	/* Configure the K1 Si workaround during phy reset assuming there is
2522	* link so that it disables K1 if link is in 1Gbps.
2523	*/
2524	ret_val = e1000_k1_gig_workaround_hv(hw, link: true);
2525	if (ret_val)
2526	return ret_val;
2527
2528	/* Workaround for link disconnects on a busy hub in half duplex */
2529	ret_val = hw->phy.ops.acquire(hw);
2530	if (ret_val)
2531	return ret_val;
2532	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, data: &phy_data);
2533	if (ret_val)
2534	goto release;
2535	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, data: phy_data & 0x00FF);
2536	if (ret_val)
2537	goto release;
2538
2539	/* set MSE higher to enable link to stay up when noise is high */
2540	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, data: 0x0034);
2541	release:
2542	hw->phy.ops.release(hw);
2543
2544	return ret_val;
2545	}
2546
2547	/**
2548	* e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2549	* @hw: pointer to the HW structure
2550	**/
2551	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2552	{
2553	u32 mac_reg;
2554	u16 i, phy_reg = 0;
2555	s32 ret_val;
2556
2557	ret_val = hw->phy.ops.acquire(hw);
2558	if (ret_val)
2559	return;
2560	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, phy_reg: &phy_reg);
2561	if (ret_val)
2562	goto release;
2563
2564	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2565	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2566	mac_reg = er32(RAL(i));
2567	hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2568	(u16)(mac_reg & 0xFFFF));
2569	hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2570	(u16)((mac_reg >> 16) & 0xFFFF));
2571
2572	mac_reg = er32(RAH(i));
2573	hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2574	(u16)(mac_reg & 0xFFFF));
2575	hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2576	(u16)((mac_reg & E1000_RAH_AV) >> 16));
2577	}
2578
2579	e1000_disable_phy_wakeup_reg_access_bm(hw, phy_reg: &phy_reg);
2580
2581	release:
2582	hw->phy.ops.release(hw);
2583	}
2584
2585	/**
2586	* e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2587	* with 82579 PHY
2588	* @hw: pointer to the HW structure
2589	* @enable: flag to enable/disable workaround when enabling/disabling jumbos
2590	**/
2591	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2592	{
2593	s32 ret_val = 0;
2594	u16 phy_reg, data;
2595	u32 mac_reg;
2596	u16 i;
2597
2598	if (hw->mac.type < e1000_pch2lan)
2599	return 0;
2600
2601	/* disable Rx path while enabling/disabling workaround */
2602	e1e_rphy(hw, PHY_REG(769, 20), data: &phy_reg);
2603	ret_val = e1e_wphy(hw, PHY_REG(769, 20), data: phy_reg | BIT(14));
2604	if (ret_val)
2605	return ret_val;
2606
2607	if (enable) {
2608	/* Write Rx addresses (rar_entry_count for RAL/H, and
2609	* SHRAL/H) and initial CRC values to the MAC
2610	*/
2611	for (i = 0; i < hw->mac.rar_entry_count; i++) {
2612	u8 mac_addr[ETH_ALEN] = { 0 };
2613	u32 addr_high, addr_low;
2614
2615	addr_high = er32(RAH(i));
2616	if (!(addr_high & E1000_RAH_AV))
2617	continue;
2618	addr_low = er32(RAL(i));
2619	mac_addr[0] = (addr_low & 0xFF);
2620	mac_addr[1] = ((addr_low >> 8) & 0xFF);
2621	mac_addr[2] = ((addr_low >> 16) & 0xFF);
2622	mac_addr[3] = ((addr_low >> 24) & 0xFF);
2623	mac_addr[4] = (addr_high & 0xFF);
2624	mac_addr[5] = ((addr_high >> 8) & 0xFF);
2625
2626	ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2627	}
2628
2629	/* Write Rx addresses to the PHY */
2630	e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2631
2632	/* Enable jumbo frame workaround in the MAC */
2633	mac_reg = er32(FFLT_DBG);
2634	mac_reg &= ~BIT(14);
2635	mac_reg |= (7 << 15);
2636	ew32(FFLT_DBG, mac_reg);
2637
2638	mac_reg = er32(RCTL);
2639	mac_reg |= E1000_RCTL_SECRC;
2640	ew32(RCTL, mac_reg);
2641
2642	ret_val = e1000e_read_kmrn_reg(hw,
2643	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2644	data: &data);
2645	if (ret_val)
2646	return ret_val;
2647	ret_val = e1000e_write_kmrn_reg(hw,
2648	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2649	data: data | BIT(0));
2650	if (ret_val)
2651	return ret_val;
2652	ret_val = e1000e_read_kmrn_reg(hw,
2653	E1000_KMRNCTRLSTA_HD_CTRL,
2654	data: &data);
2655	if (ret_val)
2656	return ret_val;
2657	data &= ~(0xF << 8);
2658	data |= (0xB << 8);
2659	ret_val = e1000e_write_kmrn_reg(hw,
2660	E1000_KMRNCTRLSTA_HD_CTRL,
2661	data);
2662	if (ret_val)
2663	return ret_val;
2664
2665	/* Enable jumbo frame workaround in the PHY */
2666	e1e_rphy(hw, PHY_REG(769, 23), data: &data);
2667	data &= ~(0x7F << 5);
2668	data |= (0x37 << 5);
2669	ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2670	if (ret_val)
2671	return ret_val;
2672	e1e_rphy(hw, PHY_REG(769, 16), data: &data);
2673	data &= ~BIT(13);
2674	ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2675	if (ret_val)
2676	return ret_val;
2677	e1e_rphy(hw, PHY_REG(776, 20), data: &data);
2678	data &= ~(0x3FF << 2);
2679	data |= (E1000_TX_PTR_GAP << 2);
2680	ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2681	if (ret_val)
2682	return ret_val;
2683	ret_val = e1e_wphy(hw, PHY_REG(776, 23), data: 0xF100);
2684	if (ret_val)
2685	return ret_val;
2686	e1e_rphy(hw, HV_PM_CTRL, data: &data);
2687	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: data | BIT(10));
2688	if (ret_val)
2689	return ret_val;
2690	} else {
2691	/* Write MAC register values back to h/w defaults */
2692	mac_reg = er32(FFLT_DBG);
2693	mac_reg &= ~(0xF << 14);
2694	ew32(FFLT_DBG, mac_reg);
2695
2696	mac_reg = er32(RCTL);
2697	mac_reg &= ~E1000_RCTL_SECRC;
2698	ew32(RCTL, mac_reg);
2699
2700	ret_val = e1000e_read_kmrn_reg(hw,
2701	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2702	data: &data);
2703	if (ret_val)
2704	return ret_val;
2705	ret_val = e1000e_write_kmrn_reg(hw,
2706	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2707	data: data & ~BIT(0));
2708	if (ret_val)
2709	return ret_val;
2710	ret_val = e1000e_read_kmrn_reg(hw,
2711	E1000_KMRNCTRLSTA_HD_CTRL,
2712	data: &data);
2713	if (ret_val)
2714	return ret_val;
2715	data &= ~(0xF << 8);
2716	data |= (0xB << 8);
2717	ret_val = e1000e_write_kmrn_reg(hw,
2718	E1000_KMRNCTRLSTA_HD_CTRL,
2719	data);
2720	if (ret_val)
2721	return ret_val;
2722
2723	/* Write PHY register values back to h/w defaults */
2724	e1e_rphy(hw, PHY_REG(769, 23), data: &data);
2725	data &= ~(0x7F << 5);
2726	ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2727	if (ret_val)
2728	return ret_val;
2729	e1e_rphy(hw, PHY_REG(769, 16), data: &data);
2730	data |= BIT(13);
2731	ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2732	if (ret_val)
2733	return ret_val;
2734	e1e_rphy(hw, PHY_REG(776, 20), data: &data);
2735	data &= ~(0x3FF << 2);
2736	data |= (0x8 << 2);
2737	ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2738	if (ret_val)
2739	return ret_val;
2740	ret_val = e1e_wphy(hw, PHY_REG(776, 23), data: 0x7E00);
2741	if (ret_val)
2742	return ret_val;
2743	e1e_rphy(hw, HV_PM_CTRL, data: &data);
2744	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: data & ~BIT(10));
2745	if (ret_val)
2746	return ret_val;
2747	}
2748
2749	/* re-enable Rx path after enabling/disabling workaround */
2750	return e1e_wphy(hw, PHY_REG(769, 20), data: phy_reg & ~BIT(14));
2751	}
2752
2753	/**
2754	* e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2755	* @hw: pointer to the HW structure
2756	*
2757	* A series of PHY workarounds to be done after every PHY reset.
2758	**/
2759	static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2760	{
2761	s32 ret_val = 0;
2762
2763	if (hw->mac.type != e1000_pch2lan)
2764	return 0;
2765
2766	/* Set MDIO slow mode before any other MDIO access */
2767	ret_val = e1000_set_mdio_slow_mode_hv(hw);
2768	if (ret_val)
2769	return ret_val;
2770
2771	ret_val = hw->phy.ops.acquire(hw);
2772	if (ret_val)
2773	return ret_val;
2774	/* set MSE higher to enable link to stay up when noise is high */
2775	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, data: 0x0034);
2776	if (ret_val)
2777	goto release;
2778	/* drop link after 5 times MSE threshold was reached */
2779	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, data: 0x0005);
2780	release:
2781	hw->phy.ops.release(hw);
2782
2783	return ret_val;
2784	}
2785
2786	/**
2787	* e1000_k1_workaround_lv - K1 Si workaround
2788	* @hw: pointer to the HW structure
2789	*
2790	* Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2791	* Disable K1 in 1000Mbps and 100Mbps
2792	**/
2793	static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2794	{
2795	s32 ret_val = 0;
2796	u16 status_reg = 0;
2797
2798	if (hw->mac.type != e1000_pch2lan)
2799	return 0;
2800
2801	/* Set K1 beacon duration based on 10Mbs speed */
2802	ret_val = e1e_rphy(hw, HV_M_STATUS, data: &status_reg);
2803	if (ret_val)
2804	return ret_val;
2805
2806	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2807	== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2808	if (status_reg &
2809	(HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2810	u16 pm_phy_reg;
2811
2812	/* LV 1G/100 Packet drop issue wa */
2813	ret_val = e1e_rphy(hw, HV_PM_CTRL, data: &pm_phy_reg);
2814	if (ret_val)
2815	return ret_val;
2816	pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2817	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: pm_phy_reg);
2818	if (ret_val)
2819	return ret_val;
2820	} else {
2821	u32 mac_reg;
2822
2823	mac_reg = er32(FEXTNVM4);
2824	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2825	mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2826	ew32(FEXTNVM4, mac_reg);
2827	}
2828	}
2829
2830	return ret_val;
2831	}
2832
2833	/**
2834	* e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2835	* @hw: pointer to the HW structure
2836	* @gate: boolean set to true to gate, false to ungate
2837	*
2838	* Gate/ungate the automatic PHY configuration via hardware; perform
2839	* the configuration via software instead.
2840	**/
2841	static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2842	{
2843	u32 extcnf_ctrl;
2844
2845	if (hw->mac.type < e1000_pch2lan)
2846	return;
2847
2848	extcnf_ctrl = er32(EXTCNF_CTRL);
2849
2850	if (gate)
2851	extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2852	else
2853	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2854
2855	ew32(EXTCNF_CTRL, extcnf_ctrl);
2856	}
2857
2858	/**
2859	* e1000_lan_init_done_ich8lan - Check for PHY config completion
2860	* @hw: pointer to the HW structure
2861	*
2862	* Check the appropriate indication the MAC has finished configuring the
2863	* PHY after a software reset.
2864	**/
2865	static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2866	{
2867	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2868
2869	/* Wait for basic configuration completes before proceeding */
2870	do {
2871	data = er32(STATUS);
2872	data &= E1000_STATUS_LAN_INIT_DONE;
2873	usleep_range(min: 100, max: 200);
2874	} while ((!data) && --loop);
2875
2876	/* If basic configuration is incomplete before the above loop
2877	* count reaches 0, loading the configuration from NVM will
2878	* leave the PHY in a bad state possibly resulting in no link.
2879	*/
2880	if (loop == 0)
2881	e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2882
2883	/* Clear the Init Done bit for the next init event */
2884	data = er32(STATUS);
2885	data &= ~E1000_STATUS_LAN_INIT_DONE;
2886	ew32(STATUS, data);
2887	}
2888
2889	/**
2890	* e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2891	* @hw: pointer to the HW structure
2892	**/
2893	static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2894	{
2895	s32 ret_val = 0;
2896	u16 reg;
2897
2898	if (hw->phy.ops.check_reset_block(hw))
2899	return 0;
2900
2901	/* Allow time for h/w to get to quiescent state after reset */
2902	usleep_range(min: 10000, max: 11000);
2903
2904	/* Perform any necessary post-reset workarounds */
2905	switch (hw->mac.type) {
2906	case e1000_pchlan:
2907	ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2908	if (ret_val)
2909	return ret_val;
2910	break;
2911	case e1000_pch2lan:
2912	ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2913	if (ret_val)
2914	return ret_val;
2915	break;
2916	default:
2917	break;
2918	}
2919
2920	/* Clear the host wakeup bit after lcd reset */
2921	if (hw->mac.type >= e1000_pchlan) {
2922	e1e_rphy(hw, BM_PORT_GEN_CFG, data: &reg);
2923	reg &= ~BM_WUC_HOST_WU_BIT;
2924	e1e_wphy(hw, BM_PORT_GEN_CFG, data: reg);
2925	}
2926
2927	/* Configure the LCD with the extended configuration region in NVM */
2928	ret_val = e1000_sw_lcd_config_ich8lan(hw);
2929	if (ret_val)
2930	return ret_val;
2931
2932	/* Configure the LCD with the OEM bits in NVM */
2933	ret_val = e1000_oem_bits_config_ich8lan(hw, d0_state: true);
2934
2935	if (hw->mac.type == e1000_pch2lan) {
2936	/* Ungate automatic PHY configuration on non-managed 82579 */
2937	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2938	usleep_range(min: 10000, max: 11000);
2939	e1000_gate_hw_phy_config_ich8lan(hw, gate: false);
2940	}
2941
2942	/* Set EEE LPI Update Timer to 200usec */
2943	ret_val = hw->phy.ops.acquire(hw);
2944	if (ret_val)
2945	return ret_val;
2946	ret_val = e1000_write_emi_reg_locked(hw,
2947	I82579_LPI_UPDATE_TIMER,
2948	data: 0x1387);
2949	hw->phy.ops.release(hw);
2950	}
2951
2952	return ret_val;
2953	}
2954
2955	/**
2956	* e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2957	* @hw: pointer to the HW structure
2958	*
2959	* Resets the PHY
2960	* This is a function pointer entry point called by drivers
2961	* or other shared routines.
2962	**/
2963	static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2964	{
2965	s32 ret_val = 0;
2966
2967	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
2968	if ((hw->mac.type == e1000_pch2lan) &&
2969	!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2970	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
2971
2972	ret_val = e1000e_phy_hw_reset_generic(hw);
2973	if (ret_val)
2974	return ret_val;
2975
2976	return e1000_post_phy_reset_ich8lan(hw);
2977	}
2978
2979	/**
2980	* e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2981	* @hw: pointer to the HW structure
2982	* @active: true to enable LPLU, false to disable
2983	*
2984	* Sets the LPLU state according to the active flag. For PCH, if OEM write
2985	* bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2986	* the phy speed. This function will manually set the LPLU bit and restart
2987	* auto-neg as hw would do. D3 and D0 LPLU will call the same function
2988	* since it configures the same bit.
2989	**/
2990	static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2991	{
2992	s32 ret_val;
2993	u16 oem_reg;
2994
2995	ret_val = e1e_rphy(hw, HV_OEM_BITS, data: &oem_reg);
2996	if (ret_val)
2997	return ret_val;
2998
2999	if (active)
3000	oem_reg |= HV_OEM_BITS_LPLU;
3001	else
3002	oem_reg &= ~HV_OEM_BITS_LPLU;
3003
3004	if (!hw->phy.ops.check_reset_block(hw))
3005	oem_reg |= HV_OEM_BITS_RESTART_AN;
3006
3007	return e1e_wphy(hw, HV_OEM_BITS, data: oem_reg);
3008	}
3009
3010	/**
3011	* e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3012	* @hw: pointer to the HW structure
3013	* @active: true to enable LPLU, false to disable
3014	*
3015	* Sets the LPLU D0 state according to the active flag. When
3016	* activating LPLU this function also disables smart speed
3017	* and vice versa. LPLU will not be activated unless the
3018	* device autonegotiation advertisement meets standards of
3019	* either 10 or 10/100 or 10/100/1000 at all duplexes.
3020	* This is a function pointer entry point only called by
3021	* PHY setup routines.
3022	**/
3023	static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3024	{
3025	struct e1000_phy_info *phy = &hw->phy;
3026	u32 phy_ctrl;
3027	s32 ret_val = 0;
3028	u16 data;
3029
3030	if (phy->type == e1000_phy_ife)
3031	return 0;
3032
3033	phy_ctrl = er32(PHY_CTRL);
3034
3035	if (active) {
3036	phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3037	ew32(PHY_CTRL, phy_ctrl);
3038
3039	if (phy->type != e1000_phy_igp_3)
3040	return 0;
3041
3042	/* Call gig speed drop workaround on LPLU before accessing
3043	* any PHY registers
3044	*/
3045	if (hw->mac.type == e1000_ich8lan)
3046	e1000e_gig_downshift_workaround_ich8lan(hw);
3047
3048	/* When LPLU is enabled, we should disable SmartSpeed */
3049	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, data: &data);
3050	if (ret_val)
3051	return ret_val;
3052	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3053	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3054	if (ret_val)
3055	return ret_val;
3056	} else {
3057	phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3058	ew32(PHY_CTRL, phy_ctrl);
3059
3060	if (phy->type != e1000_phy_igp_3)
3061	return 0;
3062
3063	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3064	* during Dx states where the power conservation is most
3065	* important. During driver activity we should enable
3066	* SmartSpeed, so performance is maintained.
3067	*/
3068	if (phy->smart_speed == e1000_smart_speed_on) {
3069	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3070	data: &data);
3071	if (ret_val)
3072	return ret_val;
3073
3074	data |= IGP01E1000_PSCFR_SMART_SPEED;
3075	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3076	data);
3077	if (ret_val)
3078	return ret_val;
3079	} else if (phy->smart_speed == e1000_smart_speed_off) {
3080	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3081	data: &data);
3082	if (ret_val)
3083	return ret_val;
3084
3085	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3086	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3087	data);
3088	if (ret_val)
3089	return ret_val;
3090	}
3091	}
3092
3093	return 0;
3094	}
3095
3096	/**
3097	* e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3098	* @hw: pointer to the HW structure
3099	* @active: true to enable LPLU, false to disable
3100	*
3101	* Sets the LPLU D3 state according to the active flag. When
3102	* activating LPLU this function also disables smart speed
3103	* and vice versa. LPLU will not be activated unless the
3104	* device autonegotiation advertisement meets standards of
3105	* either 10 or 10/100 or 10/100/1000 at all duplexes.
3106	* This is a function pointer entry point only called by
3107	* PHY setup routines.
3108	**/
3109	static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3110	{
3111	struct e1000_phy_info *phy = &hw->phy;
3112	u32 phy_ctrl;
3113	s32 ret_val = 0;
3114	u16 data;
3115
3116	phy_ctrl = er32(PHY_CTRL);
3117
3118	if (!active) {
3119	phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3120	ew32(PHY_CTRL, phy_ctrl);
3121
3122	if (phy->type != e1000_phy_igp_3)
3123	return 0;
3124
3125	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3126	* during Dx states where the power conservation is most
3127	* important. During driver activity we should enable
3128	* SmartSpeed, so performance is maintained.
3129	*/
3130	if (phy->smart_speed == e1000_smart_speed_on) {
3131	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3132	data: &data);
3133	if (ret_val)
3134	return ret_val;
3135
3136	data |= IGP01E1000_PSCFR_SMART_SPEED;
3137	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3138	data);
3139	if (ret_val)
3140	return ret_val;
3141	} else if (phy->smart_speed == e1000_smart_speed_off) {
3142	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3143	data: &data);
3144	if (ret_val)
3145	return ret_val;
3146
3147	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3148	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3149	data);
3150	if (ret_val)
3151	return ret_val;
3152	}
3153	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3154	(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3155	(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3156	phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3157	ew32(PHY_CTRL, phy_ctrl);
3158
3159	if (phy->type != e1000_phy_igp_3)
3160	return 0;
3161
3162	/* Call gig speed drop workaround on LPLU before accessing
3163	* any PHY registers
3164	*/
3165	if (hw->mac.type == e1000_ich8lan)
3166	e1000e_gig_downshift_workaround_ich8lan(hw);
3167
3168	/* When LPLU is enabled, we should disable SmartSpeed */
3169	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, data: &data);
3170	if (ret_val)
3171	return ret_val;
3172
3173	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3174	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3175	}
3176
3177	return ret_val;
3178	}
3179
3180	/**
3181	* e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3182	* @hw: pointer to the HW structure
3183	* @bank: pointer to the variable that returns the active bank
3184	*
3185	* Reads signature byte from the NVM using the flash access registers.
3186	* Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3187	**/
3188	static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3189	{
3190	u32 eecd;
3191	struct e1000_nvm_info *nvm = &hw->nvm;
3192	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3193	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3194	u32 nvm_dword = 0;
3195	u8 sig_byte = 0;
3196	s32 ret_val;
3197
3198	switch (hw->mac.type) {
3199	case e1000_pch_spt:
3200	case e1000_pch_cnp:
3201	case e1000_pch_tgp:
3202	case e1000_pch_adp:
3203	case e1000_pch_mtp:
3204	case e1000_pch_lnp:
3205	case e1000_pch_ptp:
3206	case e1000_pch_nvp:
3207	bank1_offset = nvm->flash_bank_size;
3208	act_offset = E1000_ICH_NVM_SIG_WORD;
3209
3210	/* set bank to 0 in case flash read fails */
3211	*bank = 0;
3212
3213	/* Check bank 0 */
3214	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset,
3215	data: &nvm_dword);
3216	if (ret_val)
3217	return ret_val;
3218	sig_byte = FIELD_GET(0xFF00, nvm_dword);
3219	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3220	E1000_ICH_NVM_SIG_VALUE) {
3221	*bank = 0;
3222	return 0;
3223	}
3224
3225	/* Check bank 1 */
3226	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset +
3227	bank1_offset,
3228	data: &nvm_dword);
3229	if (ret_val)
3230	return ret_val;
3231	sig_byte = FIELD_GET(0xFF00, nvm_dword);
3232	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3233	E1000_ICH_NVM_SIG_VALUE) {
3234	*bank = 1;
3235	return 0;
3236	}
3237
3238	e_dbg("ERROR: No valid NVM bank present\n");
3239	return -E1000_ERR_NVM;
3240	case e1000_ich8lan:
3241	case e1000_ich9lan:
3242	eecd = er32(EECD);
3243	if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3244	E1000_EECD_SEC1VAL_VALID_MASK) {
3245	if (eecd & E1000_EECD_SEC1VAL)
3246	*bank = 1;
3247	else
3248	*bank = 0;
3249
3250	return 0;
3251	}
3252	e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3253	fallthrough;
3254	default:
3255	/* set bank to 0 in case flash read fails */
3256	*bank = 0;
3257
3258	/* Check bank 0 */
3259	ret_val = e1000_read_flash_byte_ich8lan(hw, offset: act_offset,
3260	data: &sig_byte);
3261	if (ret_val)
3262	return ret_val;
3263	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3264	E1000_ICH_NVM_SIG_VALUE) {
3265	*bank = 0;
3266	return 0;
3267	}
3268
3269	/* Check bank 1 */
3270	ret_val = e1000_read_flash_byte_ich8lan(hw, offset: act_offset +
3271	bank1_offset,
3272	data: &sig_byte);
3273	if (ret_val)
3274	return ret_val;
3275	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3276	E1000_ICH_NVM_SIG_VALUE) {
3277	*bank = 1;
3278	return 0;
3279	}
3280
3281	e_dbg("ERROR: No valid NVM bank present\n");
3282	return -E1000_ERR_NVM;
3283	}
3284	}
3285
3286	/**
3287	* e1000_read_nvm_spt - NVM access for SPT
3288	* @hw: pointer to the HW structure
3289	* @offset: The offset (in bytes) of the word(s) to read.
3290	* @words: Size of data to read in words.
3291	* @data: pointer to the word(s) to read at offset.
3292	*
3293	* Reads a word(s) from the NVM
3294	**/
3295	static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3296	u16 *data)
3297	{
3298	struct e1000_nvm_info *nvm = &hw->nvm;
3299	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3300	u32 act_offset;
3301	s32 ret_val = 0;
3302	u32 bank = 0;
3303	u32 dword = 0;
3304	u16 offset_to_read;
3305	u16 i;
3306
3307	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3308	(words == 0)) {
3309	e_dbg("nvm parameter(s) out of bounds\n");
3310	ret_val = -E1000_ERR_NVM;
3311	goto out;
3312	}
3313
3314	nvm->ops.acquire(hw);
3315
3316	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3317	if (ret_val) {
3318	e_dbg("Could not detect valid bank, assuming bank 0\n");
3319	bank = 0;
3320	}
3321
3322	act_offset = (bank) ? nvm->flash_bank_size : 0;
3323	act_offset += offset;
3324
3325	ret_val = 0;
3326
3327	for (i = 0; i < words; i += 2) {
3328	if (words - i == 1) {
3329	if (dev_spec->shadow_ram[offset + i].modified) {
3330	data[i] =
3331	dev_spec->shadow_ram[offset + i].value;
3332	} else {
3333	offset_to_read = act_offset + i -
3334	((act_offset + i) % 2);
3335	ret_val =
3336	e1000_read_flash_dword_ich8lan(hw,
3337	offset: offset_to_read,
3338	data: &dword);
3339	if (ret_val)
3340	break;
3341	if ((act_offset + i) % 2 == 0)
3342	data[i] = (u16)(dword & 0xFFFF);
3343	else
3344	data[i] = (u16)((dword >> 16) & 0xFFFF);
3345	}
3346	} else {
3347	offset_to_read = act_offset + i;
3348	if (!(dev_spec->shadow_ram[offset + i].modified) ||
3349	!(dev_spec->shadow_ram[offset + i + 1].modified)) {
3350	ret_val =
3351	e1000_read_flash_dword_ich8lan(hw,
3352	offset: offset_to_read,
3353	data: &dword);
3354	if (ret_val)
3355	break;
3356	}
3357	if (dev_spec->shadow_ram[offset + i].modified)
3358	data[i] =
3359	dev_spec->shadow_ram[offset + i].value;
3360	else
3361	data[i] = (u16)(dword & 0xFFFF);
3362	if (dev_spec->shadow_ram[offset + i].modified)
3363	data[i + 1] =
3364	dev_spec->shadow_ram[offset + i + 1].value;
3365	else
3366	data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3367	}
3368	}
3369
3370	nvm->ops.release(hw);
3371
3372	out:
3373	if (ret_val)
3374	e_dbg("NVM read error: %d\n", ret_val);
3375
3376	return ret_val;
3377	}
3378
3379	/**
3380	* e1000_read_nvm_ich8lan - Read word(s) from the NVM
3381	* @hw: pointer to the HW structure
3382	* @offset: The offset (in bytes) of the word(s) to read.
3383	* @words: Size of data to read in words
3384	* @data: Pointer to the word(s) to read at offset.
3385	*
3386	* Reads a word(s) from the NVM using the flash access registers.
3387	**/
3388	static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3389	u16 *data)
3390	{
3391	struct e1000_nvm_info *nvm = &hw->nvm;
3392	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3393	u32 act_offset;
3394	s32 ret_val = 0;
3395	u32 bank = 0;
3396	u16 i, word;
3397
3398	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3399	(words == 0)) {
3400	e_dbg("nvm parameter(s) out of bounds\n");
3401	ret_val = -E1000_ERR_NVM;
3402	goto out;
3403	}
3404
3405	nvm->ops.acquire(hw);
3406
3407	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3408	if (ret_val) {
3409	e_dbg("Could not detect valid bank, assuming bank 0\n");
3410	bank = 0;
3411	}
3412
3413	act_offset = (bank) ? nvm->flash_bank_size : 0;
3414	act_offset += offset;
3415
3416	ret_val = 0;
3417	for (i = 0; i < words; i++) {
3418	if (dev_spec->shadow_ram[offset + i].modified) {
3419	data[i] = dev_spec->shadow_ram[offset + i].value;
3420	} else {
3421	ret_val = e1000_read_flash_word_ich8lan(hw,
3422	offset: act_offset + i,
3423	data: &word);
3424	if (ret_val)
3425	break;
3426	data[i] = word;
3427	}
3428	}
3429
3430	nvm->ops.release(hw);
3431
3432	out:
3433	if (ret_val)
3434	e_dbg("NVM read error: %d\n", ret_val);
3435
3436	return ret_val;
3437	}
3438
3439	/**
3440	* e1000_flash_cycle_init_ich8lan - Initialize flash
3441	* @hw: pointer to the HW structure
3442	*
3443	* This function does initial flash setup so that a new read/write/erase cycle
3444	* can be started.
3445	**/
3446	static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3447	{
3448	union ich8_hws_flash_status hsfsts;
3449	s32 ret_val = -E1000_ERR_NVM;
3450
3451	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3452
3453	/* Check if the flash descriptor is valid */
3454	if (!hsfsts.hsf_status.fldesvalid) {
3455	e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3456	return -E1000_ERR_NVM;
3457	}
3458
3459	/* Clear FCERR and DAEL in hw status by writing 1 */
3460	hsfsts.hsf_status.flcerr = 1;
3461	hsfsts.hsf_status.dael = 1;
3462	if (hw->mac.type >= e1000_pch_spt)
3463	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3464	else
3465	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3466
3467	/* Either we should have a hardware SPI cycle in progress
3468	* bit to check against, in order to start a new cycle or
3469	* FDONE bit should be changed in the hardware so that it
3470	* is 1 after hardware reset, which can then be used as an
3471	* indication whether a cycle is in progress or has been
3472	* completed.
3473	*/
3474
3475	if (!hsfsts.hsf_status.flcinprog) {
3476	/* There is no cycle running at present,
3477	* so we can start a cycle.
3478	* Begin by setting Flash Cycle Done.
3479	*/
3480	hsfsts.hsf_status.flcdone = 1;
3481	if (hw->mac.type >= e1000_pch_spt)
3482	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3483	else
3484	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3485	ret_val = 0;
3486	} else {
3487	s32 i;
3488
3489	/* Otherwise poll for sometime so the current
3490	* cycle has a chance to end before giving up.
3491	*/
3492	for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3493	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3494	if (!hsfsts.hsf_status.flcinprog) {
3495	ret_val = 0;
3496	break;
3497	}
3498	udelay(1);
3499	}
3500	if (!ret_val) {
3501	/* Successful in waiting for previous cycle to timeout,
3502	* now set the Flash Cycle Done.
3503	*/
3504	hsfsts.hsf_status.flcdone = 1;
3505	if (hw->mac.type >= e1000_pch_spt)
3506	ew32flash(ICH_FLASH_HSFSTS,
3507	hsfsts.regval & 0xFFFF);
3508	else
3509	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3510	} else {
3511	e_dbg("Flash controller busy, cannot get access\n");
3512	}
3513	}
3514
3515	return ret_val;
3516	}
3517
3518	/**
3519	* e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3520	* @hw: pointer to the HW structure
3521	* @timeout: maximum time to wait for completion
3522	*
3523	* This function starts a flash cycle and waits for its completion.
3524	**/
3525	static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3526	{
3527	union ich8_hws_flash_ctrl hsflctl;
3528	union ich8_hws_flash_status hsfsts;
3529	u32 i = 0;
3530
3531	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3532	if (hw->mac.type >= e1000_pch_spt)
3533	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3534	else
3535	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3536	hsflctl.hsf_ctrl.flcgo = 1;
3537
3538	if (hw->mac.type >= e1000_pch_spt)
3539	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3540	else
3541	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3542
3543	/* wait till FDONE bit is set to 1 */
3544	do {
3545	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3546	if (hsfsts.hsf_status.flcdone)
3547	break;
3548	udelay(1);
3549	} while (i++ < timeout);
3550
3551	if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3552	return 0;
3553
3554	return -E1000_ERR_NVM;
3555	}
3556
3557	/**
3558	* e1000_read_flash_dword_ich8lan - Read dword from flash
3559	* @hw: pointer to the HW structure
3560	* @offset: offset to data location
3561	* @data: pointer to the location for storing the data
3562	*
3563	* Reads the flash dword at offset into data. Offset is converted
3564	* to bytes before read.
3565	**/
3566	static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3567	u32 *data)
3568	{
3569	/* Must convert word offset into bytes. */
3570	offset <<= 1;
3571	return e1000_read_flash_data32_ich8lan(hw, offset, data);
3572	}
3573
3574	/**
3575	* e1000_read_flash_word_ich8lan - Read word from flash
3576	* @hw: pointer to the HW structure
3577	* @offset: offset to data location
3578	* @data: pointer to the location for storing the data
3579	*
3580	* Reads the flash word at offset into data. Offset is converted
3581	* to bytes before read.
3582	**/
3583	static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3584	u16 *data)
3585	{
3586	/* Must convert offset into bytes. */
3587	offset <<= 1;
3588
3589	return e1000_read_flash_data_ich8lan(hw, offset, size: 2, data);
3590	}
3591
3592	/**
3593	* e1000_read_flash_byte_ich8lan - Read byte from flash
3594	* @hw: pointer to the HW structure
3595	* @offset: The offset of the byte to read.
3596	* @data: Pointer to a byte to store the value read.
3597	*
3598	* Reads a single byte from the NVM using the flash access registers.
3599	**/
3600	static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3601	u8 *data)
3602	{
3603	s32 ret_val;
3604	u16 word = 0;
3605
3606	/* In SPT, only 32 bits access is supported,
3607	* so this function should not be called.
3608	*/
3609	if (hw->mac.type >= e1000_pch_spt)
3610	return -E1000_ERR_NVM;
3611	else
3612	ret_val = e1000_read_flash_data_ich8lan(hw, offset, size: 1, data: &word);
3613
3614	if (ret_val)
3615	return ret_val;
3616
3617	*data = (u8)word;
3618
3619	return 0;
3620	}
3621
3622	/**
3623	* e1000_read_flash_data_ich8lan - Read byte or word from NVM
3624	* @hw: pointer to the HW structure
3625	* @offset: The offset (in bytes) of the byte or word to read.
3626	* @size: Size of data to read, 1=byte 2=word
3627	* @data: Pointer to the word to store the value read.
3628	*
3629	* Reads a byte or word from the NVM using the flash access registers.
3630	**/
3631	static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3632	u8 size, u16 *data)
3633	{
3634	union ich8_hws_flash_status hsfsts;
3635	union ich8_hws_flash_ctrl hsflctl;
3636	u32 flash_linear_addr;
3637	u32 flash_data = 0;
3638	s32 ret_val = -E1000_ERR_NVM;
3639	u8 count = 0;
3640
3641	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3642	return -E1000_ERR_NVM;
3643
3644	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3645	hw->nvm.flash_base_addr);
3646
3647	do {
3648	udelay(1);
3649	/* Steps */
3650	ret_val = e1000_flash_cycle_init_ich8lan(hw);
3651	if (ret_val)
3652	break;
3653
3654	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3655	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3656	hsflctl.hsf_ctrl.fldbcount = size - 1;
3657	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3658	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3659
3660	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3661
3662	ret_val =
3663	e1000_flash_cycle_ich8lan(hw,
3664	ICH_FLASH_READ_COMMAND_TIMEOUT);
3665
3666	/* Check if FCERR is set to 1, if set to 1, clear it
3667	* and try the whole sequence a few more times, else
3668	* read in (shift in) the Flash Data0, the order is
3669	* least significant byte first msb to lsb
3670	*/
3671	if (!ret_val) {
3672	flash_data = er32flash(ICH_FLASH_FDATA0);
3673	if (size == 1)
3674	*data = (u8)(flash_data & 0x000000FF);
3675	else if (size == 2)
3676	*data = (u16)(flash_data & 0x0000FFFF);
3677	break;
3678	} else {
3679	/* If we've gotten here, then things are probably
3680	* completely hosed, but if the error condition is
3681	* detected, it won't hurt to give it another try...
3682	* ICH_FLASH_CYCLE_REPEAT_COUNT times.
3683	*/
3684	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3685	if (hsfsts.hsf_status.flcerr) {
3686	/* Repeat for some time before giving up. */
3687	continue;
3688	} else if (!hsfsts.hsf_status.flcdone) {
3689	e_dbg("Timeout error - flash cycle did not complete.\n");
3690	break;
3691	}
3692	}
3693	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3694
3695	return ret_val;
3696	}
3697
3698	/**
3699	* e1000_read_flash_data32_ich8lan - Read dword from NVM
3700	* @hw: pointer to the HW structure
3701	* @offset: The offset (in bytes) of the dword to read.
3702	* @data: Pointer to the dword to store the value read.
3703	*
3704	* Reads a byte or word from the NVM using the flash access registers.
3705	**/
3706
3707	static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3708	u32 *data)
3709	{
3710	union ich8_hws_flash_status hsfsts;
3711	union ich8_hws_flash_ctrl hsflctl;
3712	u32 flash_linear_addr;
3713	s32 ret_val = -E1000_ERR_NVM;
3714	u8 count = 0;
3715
3716	if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3717	return -E1000_ERR_NVM;
3718	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3719	hw->nvm.flash_base_addr);
3720
3721	do {
3722	udelay(1);
3723	/* Steps */
3724	ret_val = e1000_flash_cycle_init_ich8lan(hw);
3725	if (ret_val)
3726	break;
3727	/* In SPT, This register is in Lan memory space, not flash.
3728	* Therefore, only 32 bit access is supported
3729	*/
3730	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3731
3732	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3733	hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3734	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3735	/* In SPT, This register is in Lan memory space, not flash.
3736	* Therefore, only 32 bit access is supported
3737	*/
3738	ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3739	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3740
3741	ret_val =
3742	e1000_flash_cycle_ich8lan(hw,
3743	ICH_FLASH_READ_COMMAND_TIMEOUT);
3744
3745	/* Check if FCERR is set to 1, if set to 1, clear it
3746	* and try the whole sequence a few more times, else
3747	* read in (shift in) the Flash Data0, the order is
3748	* least significant byte first msb to lsb
3749	*/
3750	if (!ret_val) {
3751	*data = er32flash(ICH_FLASH_FDATA0);
3752	break;
3753	} else {
3754	/* If we've gotten here, then things are probably
3755	* completely hosed, but if the error condition is
3756	* detected, it won't hurt to give it another try...
3757	* ICH_FLASH_CYCLE_REPEAT_COUNT times.
3758	*/
3759	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3760	if (hsfsts.hsf_status.flcerr) {
3761	/* Repeat for some time before giving up. */
3762	continue;
3763	} else if (!hsfsts.hsf_status.flcdone) {
3764	e_dbg("Timeout error - flash cycle did not complete.\n");
3765	break;
3766	}
3767	}
3768	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3769
3770	return ret_val;
3771	}
3772
3773	/**
3774	* e1000_write_nvm_ich8lan - Write word(s) to the NVM
3775	* @hw: pointer to the HW structure
3776	* @offset: The offset (in bytes) of the word(s) to write.
3777	* @words: Size of data to write in words
3778	* @data: Pointer to the word(s) to write at offset.
3779	*
3780	* Writes a byte or word to the NVM using the flash access registers.
3781	**/
3782	static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3783	u16 *data)
3784	{
3785	struct e1000_nvm_info *nvm = &hw->nvm;
3786	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3787	u16 i;
3788
3789	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3790	(words == 0)) {
3791	e_dbg("nvm parameter(s) out of bounds\n");
3792	return -E1000_ERR_NVM;
3793	}
3794
3795	nvm->ops.acquire(hw);
3796
3797	for (i = 0; i < words; i++) {
3798	dev_spec->shadow_ram[offset + i].modified = true;
3799	dev_spec->shadow_ram[offset + i].value = data[i];
3800	}
3801
3802	nvm->ops.release(hw);
3803
3804	return 0;
3805	}
3806
3807	/**
3808	* e1000_update_nvm_checksum_spt - Update the checksum for NVM
3809	* @hw: pointer to the HW structure
3810	*
3811	* The NVM checksum is updated by calling the generic update_nvm_checksum,
3812	* which writes the checksum to the shadow ram. The changes in the shadow
3813	* ram are then committed to the EEPROM by processing each bank at a time
3814	* checking for the modified bit and writing only the pending changes.
3815	* After a successful commit, the shadow ram is cleared and is ready for
3816	* future writes.
3817	**/
3818	static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3819	{
3820	struct e1000_nvm_info *nvm = &hw->nvm;
3821	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3822	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3823	s32 ret_val;
3824	u32 dword = 0;
3825
3826	ret_val = e1000e_update_nvm_checksum_generic(hw);
3827	if (ret_val)
3828	goto out;
3829
3830	if (nvm->type != e1000_nvm_flash_sw)
3831	goto out;
3832
3833	nvm->ops.acquire(hw);
3834
3835	/* We're writing to the opposite bank so if we're on bank 1,
3836	* write to bank 0 etc. We also need to erase the segment that
3837	* is going to be written
3838	*/
3839	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3840	if (ret_val) {
3841	e_dbg("Could not detect valid bank, assuming bank 0\n");
3842	bank = 0;
3843	}
3844
3845	if (bank == 0) {
3846	new_bank_offset = nvm->flash_bank_size;
3847	old_bank_offset = 0;
3848	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 1);
3849	if (ret_val)
3850	goto release;
3851	} else {
3852	old_bank_offset = nvm->flash_bank_size;
3853	new_bank_offset = 0;
3854	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 0);
3855	if (ret_val)
3856	goto release;
3857	}
3858	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3859	/* Determine whether to write the value stored
3860	* in the other NVM bank or a modified value stored
3861	* in the shadow RAM
3862	*/
3863	ret_val = e1000_read_flash_dword_ich8lan(hw,
3864	offset: i + old_bank_offset,
3865	data: &dword);
3866
3867	if (dev_spec->shadow_ram[i].modified) {
3868	dword &= 0xffff0000;
3869	dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3870	}
3871	if (dev_spec->shadow_ram[i + 1].modified) {
3872	dword &= 0x0000ffff;
3873	dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3874	<< 16);
3875	}
3876	if (ret_val)
3877	break;
3878
3879	/* If the word is 0x13, then make sure the signature bits
3880	* (15:14) are 11b until the commit has completed.
3881	* This will allow us to write 10b which indicates the
3882	* signature is valid. We want to do this after the write
3883	* has completed so that we don't mark the segment valid
3884	* while the write is still in progress
3885	*/
3886	if (i == E1000_ICH_NVM_SIG_WORD - 1)
3887	dword |= E1000_ICH_NVM_SIG_MASK << 16;
3888
3889	/* Convert offset to bytes. */
3890	act_offset = (i + new_bank_offset) << 1;
3891
3892	usleep_range(min: 100, max: 200);
3893
3894	/* Write the data to the new bank. Offset in words */
3895	act_offset = i + new_bank_offset;
3896	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset,
3897	dword);
3898	if (ret_val)
3899	break;
3900	}
3901
3902	/* Don't bother writing the segment valid bits if sector
3903	* programming failed.
3904	*/
3905	if (ret_val) {
3906	/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3907	e_dbg("Flash commit failed.\n");
3908	goto release;
3909	}
3910
3911	/* Finally validate the new segment by setting bit 15:14
3912	* to 10b in word 0x13 , this can be done without an
3913	* erase as well since these bits are 11 to start with
3914	* and we need to change bit 14 to 0b
3915	*/
3916	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3917
3918	/*offset in words but we read dword */
3919	--act_offset;
3920	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset, data: &dword);
3921
3922	if (ret_val)
3923	goto release;
3924
3925	dword &= 0xBFFFFFFF;
3926	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset, dword);
3927
3928	if (ret_val)
3929	goto release;
3930
3931	/* offset in words but we read dword */
3932	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3933	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset, data: &dword);
3934
3935	if (ret_val)
3936	goto release;
3937
3938	dword &= 0x00FFFFFF;
3939	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset, dword);
3940
3941	if (ret_val)
3942	goto release;
3943
3944	/* Great! Everything worked, we can now clear the cached entries. */
3945	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3946	dev_spec->shadow_ram[i].modified = false;
3947	dev_spec->shadow_ram[i].value = 0xFFFF;
3948	}
3949
3950	release:
3951	nvm->ops.release(hw);
3952
3953	/* Reload the EEPROM, or else modifications will not appear
3954	* until after the next adapter reset.
3955	*/
3956	if (!ret_val) {
3957	nvm->ops.reload(hw);
3958	usleep_range(min: 10000, max: 11000);
3959	}
3960
3961	out:
3962	if (ret_val)
3963	e_dbg("NVM update error: %d\n", ret_val);
3964
3965	return ret_val;
3966	}
3967
3968	/**
3969	* e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3970	* @hw: pointer to the HW structure
3971	*
3972	* The NVM checksum is updated by calling the generic update_nvm_checksum,
3973	* which writes the checksum to the shadow ram. The changes in the shadow
3974	* ram are then committed to the EEPROM by processing each bank at a time
3975	* checking for the modified bit and writing only the pending changes.
3976	* After a successful commit, the shadow ram is cleared and is ready for
3977	* future writes.
3978	**/
3979	static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3980	{
3981	struct e1000_nvm_info *nvm = &hw->nvm;
3982	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3983	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3984	s32 ret_val;
3985	u16 data = 0;
3986
3987	ret_val = e1000e_update_nvm_checksum_generic(hw);
3988	if (ret_val)
3989	goto out;
3990
3991	if (nvm->type != e1000_nvm_flash_sw)
3992	goto out;
3993
3994	nvm->ops.acquire(hw);
3995
3996	/* We're writing to the opposite bank so if we're on bank 1,
3997	* write to bank 0 etc. We also need to erase the segment that
3998	* is going to be written
3999	*/
4000	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
4001	if (ret_val) {
4002	e_dbg("Could not detect valid bank, assuming bank 0\n");
4003	bank = 0;
4004	}
4005
4006	if (bank == 0) {
4007	new_bank_offset = nvm->flash_bank_size;
4008	old_bank_offset = 0;
4009	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 1);
4010	if (ret_val)
4011	goto release;
4012	} else {
4013	old_bank_offset = nvm->flash_bank_size;
4014	new_bank_offset = 0;
4015	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 0);
4016	if (ret_val)
4017	goto release;
4018	}
4019	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4020	if (dev_spec->shadow_ram[i].modified) {
4021	data = dev_spec->shadow_ram[i].value;
4022	} else {
4023	ret_val = e1000_read_flash_word_ich8lan(hw, offset: i +
4024	old_bank_offset,
4025	data: &data);
4026	if (ret_val)
4027	break;
4028	}
4029
4030	/* If the word is 0x13, then make sure the signature bits
4031	* (15:14) are 11b until the commit has completed.
4032	* This will allow us to write 10b which indicates the
4033	* signature is valid. We want to do this after the write
4034	* has completed so that we don't mark the segment valid
4035	* while the write is still in progress
4036	*/
4037	if (i == E1000_ICH_NVM_SIG_WORD)
4038	data |= E1000_ICH_NVM_SIG_MASK;
4039
4040	/* Convert offset to bytes. */
4041	act_offset = (i + new_bank_offset) << 1;
4042
4043	usleep_range(min: 100, max: 200);
4044	/* Write the bytes to the new bank. */
4045	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4046	offset: act_offset,
4047	byte: (u8)data);
4048	if (ret_val)
4049	break;
4050
4051	usleep_range(min: 100, max: 200);
4052	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4053	offset: act_offset + 1,
4054	byte: (u8)(data >> 8));
4055	if (ret_val)
4056	break;
4057	}
4058
4059	/* Don't bother writing the segment valid bits if sector
4060	* programming failed.
4061	*/
4062	if (ret_val) {
4063	/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4064	e_dbg("Flash commit failed.\n");
4065	goto release;
4066	}
4067
4068	/* Finally validate the new segment by setting bit 15:14
4069	* to 10b in word 0x13 , this can be done without an
4070	* erase as well since these bits are 11 to start with
4071	* and we need to change bit 14 to 0b
4072	*/
4073	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4074	ret_val = e1000_read_flash_word_ich8lan(hw, offset: act_offset, data: &data);
4075	if (ret_val)
4076	goto release;
4077
4078	data &= 0xBFFF;
4079	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4080	offset: act_offset * 2 + 1,
4081	byte: (u8)(data >> 8));
4082	if (ret_val)
4083	goto release;
4084
4085	/* And invalidate the previously valid segment by setting
4086	* its signature word (0x13) high_byte to 0b. This can be
4087	* done without an erase because flash erase sets all bits
4088	* to 1's. We can write 1's to 0's without an erase
4089	*/
4090	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4091	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, offset: act_offset, byte: 0);
4092	if (ret_val)
4093	goto release;
4094
4095	/* Great! Everything worked, we can now clear the cached entries. */
4096	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4097	dev_spec->shadow_ram[i].modified = false;
4098	dev_spec->shadow_ram[i].value = 0xFFFF;
4099	}
4100
4101	release:
4102	nvm->ops.release(hw);
4103
4104	/* Reload the EEPROM, or else modifications will not appear
4105	* until after the next adapter reset.
4106	*/
4107	if (!ret_val) {
4108	nvm->ops.reload(hw);
4109	usleep_range(min: 10000, max: 11000);
4110	}
4111
4112	out:
4113	if (ret_val)
4114	e_dbg("NVM update error: %d\n", ret_val);
4115
4116	return ret_val;
4117	}
4118
4119	/**
4120	* e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4121	* @hw: pointer to the HW structure
4122	*
4123	* Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4124	* If the bit is 0, that the EEPROM had been modified, but the checksum was not
4125	* calculated, in which case we need to calculate the checksum and set bit 6.
4126	**/
4127	static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4128	{
4129	s32 ret_val;
4130	u16 data;
4131	u16 word;
4132	u16 valid_csum_mask;
4133
4134	/* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4135	* the checksum needs to be fixed. This bit is an indication that
4136	* the NVM was prepared by OEM software and did not calculate
4137	* the checksum...a likely scenario.
4138	*/
4139	switch (hw->mac.type) {
4140	case e1000_pch_lpt:
4141	case e1000_pch_spt:
4142	case e1000_pch_cnp:
4143	case e1000_pch_tgp:
4144	case e1000_pch_adp:
4145	case e1000_pch_mtp:
4146	case e1000_pch_lnp:
4147	case e1000_pch_ptp:
4148	case e1000_pch_nvp:
4149	word = NVM_COMPAT;
4150	valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4151	break;
4152	default:
4153	word = NVM_FUTURE_INIT_WORD1;
4154	valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4155	break;
4156	}
4157
4158	ret_val = e1000_read_nvm(hw, offset: word, words: 1, data: &data);
4159	if (ret_val)
4160	return ret_val;
4161
4162	if (!(data & valid_csum_mask)) {
4163	e_dbg("NVM Checksum valid bit not set\n");
4164
4165	if (hw->mac.type < e1000_pch_tgp) {
4166	data |= valid_csum_mask;
4167	ret_val = e1000_write_nvm(hw, offset: word, words: 1, data: &data);
4168	if (ret_val)
4169	return ret_val;
4170	ret_val = e1000e_update_nvm_checksum(hw);
4171	if (ret_val)
4172	return ret_val;
4173	}
4174	}
4175
4176	return e1000e_validate_nvm_checksum_generic(hw);
4177	}
4178
4179	/**
4180	* e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4181	* @hw: pointer to the HW structure
4182	*
4183	* To prevent malicious write/erase of the NVM, set it to be read-only
4184	* so that the hardware ignores all write/erase cycles of the NVM via
4185	* the flash control registers. The shadow-ram copy of the NVM will
4186	* still be updated, however any updates to this copy will not stick
4187	* across driver reloads.
4188	**/
4189	void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4190	{
4191	struct e1000_nvm_info *nvm = &hw->nvm;
4192	union ich8_flash_protected_range pr0;
4193	union ich8_hws_flash_status hsfsts;
4194	u32 gfpreg;
4195
4196	nvm->ops.acquire(hw);
4197
4198	gfpreg = er32flash(ICH_FLASH_GFPREG);
4199
4200	/* Write-protect GbE Sector of NVM */
4201	pr0.regval = er32flash(ICH_FLASH_PR0);
4202	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4203	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4204	pr0.range.wpe = true;
4205	ew32flash(ICH_FLASH_PR0, pr0.regval);
4206
4207	/* Lock down a subset of GbE Flash Control Registers, e.g.
4208	* PR0 to prevent the write-protection from being lifted.
4209	* Once FLOCKDN is set, the registers protected by it cannot
4210	* be written until FLOCKDN is cleared by a hardware reset.
4211	*/
4212	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4213	hsfsts.hsf_status.flockdn = true;
4214	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4215
4216	nvm->ops.release(hw);
4217	}
4218
4219	/**
4220	* e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4221	* @hw: pointer to the HW structure
4222	* @offset: The offset (in bytes) of the byte/word to read.
4223	* @size: Size of data to read, 1=byte 2=word
4224	* @data: The byte(s) to write to the NVM.
4225	*
4226	* Writes one/two bytes to the NVM using the flash access registers.
4227	**/
4228	static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4229	u8 size, u16 data)
4230	{
4231	union ich8_hws_flash_status hsfsts;
4232	union ich8_hws_flash_ctrl hsflctl;
4233	u32 flash_linear_addr;
4234	u32 flash_data = 0;
4235	s32 ret_val;
4236	u8 count = 0;
4237
4238	if (hw->mac.type >= e1000_pch_spt) {
4239	if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4240	return -E1000_ERR_NVM;
4241	} else {
4242	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4243	return -E1000_ERR_NVM;
4244	}
4245
4246	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4247	hw->nvm.flash_base_addr);
4248
4249	do {
4250	udelay(1);
4251	/* Steps */
4252	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4253	if (ret_val)
4254	break;
4255	/* In SPT, This register is in Lan memory space, not
4256	* flash. Therefore, only 32 bit access is supported
4257	*/
4258	if (hw->mac.type >= e1000_pch_spt)
4259	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4260	else
4261	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4262
4263	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4264	hsflctl.hsf_ctrl.fldbcount = size - 1;
4265	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4266	/* In SPT, This register is in Lan memory space,
4267	* not flash. Therefore, only 32 bit access is
4268	* supported
4269	*/
4270	if (hw->mac.type >= e1000_pch_spt)
4271	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4272	else
4273	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4274
4275	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4276
4277	if (size == 1)
4278	flash_data = (u32)data & 0x00FF;
4279	else
4280	flash_data = (u32)data;
4281
4282	ew32flash(ICH_FLASH_FDATA0, flash_data);
4283
4284	/* check if FCERR is set to 1 , if set to 1, clear it
4285	* and try the whole sequence a few more times else done
4286	*/
4287	ret_val =
4288	e1000_flash_cycle_ich8lan(hw,
4289	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4290	if (!ret_val)
4291	break;
4292
4293	/* If we're here, then things are most likely
4294	* completely hosed, but if the error condition
4295	* is detected, it won't hurt to give it another
4296	* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4297	*/
4298	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4299	if (hsfsts.hsf_status.flcerr)
4300	/* Repeat for some time before giving up. */
4301	continue;
4302	if (!hsfsts.hsf_status.flcdone) {
4303	e_dbg("Timeout error - flash cycle did not complete.\n");
4304	break;
4305	}
4306	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4307
4308	return ret_val;
4309	}
4310
4311	/**
4312	* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4313	* @hw: pointer to the HW structure
4314	* @offset: The offset (in bytes) of the dwords to read.
4315	* @data: The 4 bytes to write to the NVM.
4316	*
4317	* Writes one/two/four bytes to the NVM using the flash access registers.
4318	**/
4319	static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4320	u32 data)
4321	{
4322	union ich8_hws_flash_status hsfsts;
4323	union ich8_hws_flash_ctrl hsflctl;
4324	u32 flash_linear_addr;
4325	s32 ret_val;
4326	u8 count = 0;
4327
4328	if (hw->mac.type >= e1000_pch_spt) {
4329	if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4330	return -E1000_ERR_NVM;
4331	}
4332	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4333	hw->nvm.flash_base_addr);
4334	do {
4335	udelay(1);
4336	/* Steps */
4337	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4338	if (ret_val)
4339	break;
4340
4341	/* In SPT, This register is in Lan memory space, not
4342	* flash. Therefore, only 32 bit access is supported
4343	*/
4344	if (hw->mac.type >= e1000_pch_spt)
4345	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4346	>> 16;
4347	else
4348	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4349
4350	hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4351	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4352
4353	/* In SPT, This register is in Lan memory space,
4354	* not flash. Therefore, only 32 bit access is
4355	* supported
4356	*/
4357	if (hw->mac.type >= e1000_pch_spt)
4358	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4359	else
4360	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4361
4362	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4363
4364	ew32flash(ICH_FLASH_FDATA0, data);
4365
4366	/* check if FCERR is set to 1 , if set to 1, clear it
4367	* and try the whole sequence a few more times else done
4368	*/
4369	ret_val =
4370	e1000_flash_cycle_ich8lan(hw,
4371	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4372
4373	if (!ret_val)
4374	break;
4375
4376	/* If we're here, then things are most likely
4377	* completely hosed, but if the error condition
4378	* is detected, it won't hurt to give it another
4379	* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4380	*/
4381	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4382
4383	if (hsfsts.hsf_status.flcerr)
4384	/* Repeat for some time before giving up. */
4385	continue;
4386	if (!hsfsts.hsf_status.flcdone) {
4387	e_dbg("Timeout error - flash cycle did not complete.\n");
4388	break;
4389	}
4390	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4391
4392	return ret_val;
4393	}
4394
4395	/**
4396	* e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4397	* @hw: pointer to the HW structure
4398	* @offset: The index of the byte to read.
4399	* @data: The byte to write to the NVM.
4400	*
4401	* Writes a single byte to the NVM using the flash access registers.
4402	**/
4403	static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4404	u8 data)
4405	{
4406	u16 word = (u16)data;
4407
4408	return e1000_write_flash_data_ich8lan(hw, offset, size: 1, data: word);
4409	}
4410
4411	/**
4412	* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4413	* @hw: pointer to the HW structure
4414	* @offset: The offset of the word to write.
4415	* @dword: The dword to write to the NVM.
4416	*
4417	* Writes a single dword to the NVM using the flash access registers.
4418	* Goes through a retry algorithm before giving up.
4419	**/
4420	static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4421	u32 offset, u32 dword)
4422	{
4423	s32 ret_val;
4424	u16 program_retries;
4425
4426	/* Must convert word offset into bytes. */
4427	offset <<= 1;
4428	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, data: dword);
4429
4430	if (!ret_val)
4431	return ret_val;
4432	for (program_retries = 0; program_retries < 100; program_retries++) {
4433	e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4434	usleep_range(min: 100, max: 200);
4435	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, data: dword);
4436	if (!ret_val)
4437	break;
4438	}
4439	if (program_retries == 100)
4440	return -E1000_ERR_NVM;
4441
4442	return 0;
4443	}
4444
4445	/**
4446	* e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4447	* @hw: pointer to the HW structure
4448	* @offset: The offset of the byte to write.
4449	* @byte: The byte to write to the NVM.
4450	*
4451	* Writes a single byte to the NVM using the flash access registers.
4452	* Goes through a retry algorithm before giving up.
4453	**/
4454	static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4455	u32 offset, u8 byte)
4456	{
4457	s32 ret_val;
4458	u16 program_retries;
4459
4460	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, data: byte);
4461	if (!ret_val)
4462	return ret_val;
4463
4464	for (program_retries = 0; program_retries < 100; program_retries++) {
4465	e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4466	usleep_range(min: 100, max: 200);
4467	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, data: byte);
4468	if (!ret_val)
4469	break;
4470	}
4471	if (program_retries == 100)
4472	return -E1000_ERR_NVM;
4473
4474	return 0;
4475	}
4476
4477	/**
4478	* e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4479	* @hw: pointer to the HW structure
4480	* @bank: 0 for first bank, 1 for second bank, etc.
4481	*
4482	* Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4483	* bank N is 4096 * N + flash_reg_addr.
4484	**/
4485	static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4486	{
4487	struct e1000_nvm_info *nvm = &hw->nvm;
4488	union ich8_hws_flash_status hsfsts;
4489	union ich8_hws_flash_ctrl hsflctl;
4490	u32 flash_linear_addr;
4491	/* bank size is in 16bit words - adjust to bytes */
4492	u32 flash_bank_size = nvm->flash_bank_size * 2;
4493	s32 ret_val;
4494	s32 count = 0;
4495	s32 j, iteration, sector_size;
4496
4497	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4498
4499	/* Determine HW Sector size: Read BERASE bits of hw flash status
4500	* register
4501	* 00: The Hw sector is 256 bytes, hence we need to erase 16
4502	* consecutive sectors. The start index for the nth Hw sector
4503	* can be calculated as = bank * 4096 + n * 256
4504	* 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4505	* The start index for the nth Hw sector can be calculated
4506	* as = bank * 4096
4507	* 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4508	* (ich9 only, otherwise error condition)
4509	* 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4510	*/
4511	switch (hsfsts.hsf_status.berasesz) {
4512	case 0:
4513	/* Hw sector size 256 */
4514	sector_size = ICH_FLASH_SEG_SIZE_256;
4515	iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4516	break;
4517	case 1:
4518	sector_size = ICH_FLASH_SEG_SIZE_4K;
4519	iteration = 1;
4520	break;
4521	case 2:
4522	sector_size = ICH_FLASH_SEG_SIZE_8K;
4523	iteration = 1;
4524	break;
4525	case 3:
4526	sector_size = ICH_FLASH_SEG_SIZE_64K;
4527	iteration = 1;
4528	break;
4529	default:
4530	return -E1000_ERR_NVM;
4531	}
4532
4533	/* Start with the base address, then add the sector offset. */
4534	flash_linear_addr = hw->nvm.flash_base_addr;
4535	flash_linear_addr += (bank) ? flash_bank_size : 0;
4536
4537	for (j = 0; j < iteration; j++) {
4538	do {
4539	u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4540
4541	/* Steps */
4542	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4543	if (ret_val)
4544	return ret_val;
4545
4546	/* Write a value 11 (block Erase) in Flash
4547	* Cycle field in hw flash control
4548	*/
4549	if (hw->mac.type >= e1000_pch_spt)
4550	hsflctl.regval =
4551	er32flash(ICH_FLASH_HSFSTS) >> 16;
4552	else
4553	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4554
4555	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4556	if (hw->mac.type >= e1000_pch_spt)
4557	ew32flash(ICH_FLASH_HSFSTS,
4558	hsflctl.regval << 16);
4559	else
4560	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4561
4562	/* Write the last 24 bits of an index within the
4563	* block into Flash Linear address field in Flash
4564	* Address.
4565	*/
4566	flash_linear_addr += (j * sector_size);
4567	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4568
4569	ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4570	if (!ret_val)
4571	break;
4572
4573	/* Check if FCERR is set to 1. If 1,
4574	* clear it and try the whole sequence
4575	* a few more times else Done
4576	*/
4577	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4578	if (hsfsts.hsf_status.flcerr)
4579	/* repeat for some time before giving up */
4580	continue;
4581	else if (!hsfsts.hsf_status.flcdone)
4582	return ret_val;
4583	} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4584	}
4585
4586	return 0;
4587	}
4588
4589	/**
4590	* e1000_valid_led_default_ich8lan - Set the default LED settings
4591	* @hw: pointer to the HW structure
4592	* @data: Pointer to the LED settings
4593	*
4594	* Reads the LED default settings from the NVM to data. If the NVM LED
4595	* settings is all 0's or F's, set the LED default to a valid LED default
4596	* setting.
4597	**/
4598	static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4599	{
4600	s32 ret_val;
4601
4602	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, words: 1, data);
4603	if (ret_val) {
4604	e_dbg("NVM Read Error\n");
4605	return ret_val;
4606	}
4607
4608	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4609	*data = ID_LED_DEFAULT_ICH8LAN;
4610
4611	return 0;
4612	}
4613
4614	/**
4615	* e1000_id_led_init_pchlan - store LED configurations
4616	* @hw: pointer to the HW structure
4617	*
4618	* PCH does not control LEDs via the LEDCTL register, rather it uses
4619	* the PHY LED configuration register.
4620	*
4621	* PCH also does not have an "always on" or "always off" mode which
4622	* complicates the ID feature. Instead of using the "on" mode to indicate
4623	* in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4624	* use "link_up" mode. The LEDs will still ID on request if there is no
4625	* link based on logic in e1000_led_[on|off]_pchlan().
4626	**/
4627	static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4628	{
4629	struct e1000_mac_info *mac = &hw->mac;
4630	s32 ret_val;
4631	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4632	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4633	u16 data, i, temp, shift;
4634
4635	/* Get default ID LED modes */
4636	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4637	if (ret_val)
4638	return ret_val;
4639
4640	mac->ledctl_default = er32(LEDCTL);
4641	mac->ledctl_mode1 = mac->ledctl_default;
4642	mac->ledctl_mode2 = mac->ledctl_default;
4643
4644	for (i = 0; i < 4; i++) {
4645	temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4646	shift = (i * 5);
4647	switch (temp) {
4648	case ID_LED_ON1_DEF2:
4649	case ID_LED_ON1_ON2:
4650	case ID_LED_ON1_OFF2:
4651	mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4652	mac->ledctl_mode1 |= (ledctl_on << shift);
4653	break;
4654	case ID_LED_OFF1_DEF2:
4655	case ID_LED_OFF1_ON2:
4656	case ID_LED_OFF1_OFF2:
4657	mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4658	mac->ledctl_mode1 |= (ledctl_off << shift);
4659	break;
4660	default:
4661	/* Do nothing */
4662	break;
4663	}
4664	switch (temp) {
4665	case ID_LED_DEF1_ON2:
4666	case ID_LED_ON1_ON2:
4667	case ID_LED_OFF1_ON2:
4668	mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4669	mac->ledctl_mode2 |= (ledctl_on << shift);
4670	break;
4671	case ID_LED_DEF1_OFF2:
4672	case ID_LED_ON1_OFF2:
4673	case ID_LED_OFF1_OFF2:
4674	mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4675	mac->ledctl_mode2 |= (ledctl_off << shift);
4676	break;
4677	default:
4678	/* Do nothing */
4679	break;
4680	}
4681	}
4682
4683	return 0;
4684	}
4685
4686	/**
4687	* e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4688	* @hw: pointer to the HW structure
4689	*
4690	* ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4691	* register, so the bus width is hard coded.
4692	**/
4693	static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4694	{
4695	struct e1000_bus_info *bus = &hw->bus;
4696	s32 ret_val;
4697
4698	ret_val = e1000e_get_bus_info_pcie(hw);
4699
4700	/* ICH devices are "PCI Express"-ish. They have
4701	* a configuration space, but do not contain
4702	* PCI Express Capability registers, so bus width
4703	* must be hardcoded.
4704	*/
4705	if (bus->width == e1000_bus_width_unknown)
4706	bus->width = e1000_bus_width_pcie_x1;
4707
4708	return ret_val;
4709	}
4710
4711	/**
4712	* e1000_reset_hw_ich8lan - Reset the hardware
4713	* @hw: pointer to the HW structure
4714	*
4715	* Does a full reset of the hardware which includes a reset of the PHY and
4716	* MAC.
4717	**/
4718	static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4719	{
4720	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4721	u16 kum_cfg;
4722	u32 ctrl, reg;
4723	s32 ret_val;
4724
4725	/* Prevent the PCI-E bus from sticking if there is no TLP connection
4726	* on the last TLP read/write transaction when MAC is reset.
4727	*/
4728	ret_val = e1000e_disable_pcie_master(hw);
4729	if (ret_val)
4730	e_dbg("PCI-E Master disable polling has failed.\n");
4731
4732	e_dbg("Masking off all interrupts\n");
4733	ew32(IMC, 0xffffffff);
4734
4735	/* Disable the Transmit and Receive units. Then delay to allow
4736	* any pending transactions to complete before we hit the MAC
4737	* with the global reset.
4738	*/
4739	ew32(RCTL, 0);
4740	ew32(TCTL, E1000_TCTL_PSP);
4741	e1e_flush();
4742
4743	usleep_range(min: 10000, max: 11000);
4744
4745	/* Workaround for ICH8 bit corruption issue in FIFO memory */
4746	if (hw->mac.type == e1000_ich8lan) {
4747	/* Set Tx and Rx buffer allocation to 8k apiece. */
4748	ew32(PBA, E1000_PBA_8K);
4749	/* Set Packet Buffer Size to 16k. */
4750	ew32(PBS, E1000_PBS_16K);
4751	}
4752
4753	if (hw->mac.type == e1000_pchlan) {
4754	/* Save the NVM K1 bit setting */
4755	ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, words: 1, data: &kum_cfg);
4756	if (ret_val)
4757	return ret_val;
4758
4759	if (kum_cfg & E1000_NVM_K1_ENABLE)
4760	dev_spec->nvm_k1_enabled = true;
4761	else
4762	dev_spec->nvm_k1_enabled = false;
4763	}
4764
4765	ctrl = er32(CTRL);
4766
4767	if (!hw->phy.ops.check_reset_block(hw)) {
4768	/* Full-chip reset requires MAC and PHY reset at the same
4769	* time to make sure the interface between MAC and the
4770	* external PHY is reset.
4771	*/
4772	ctrl |= E1000_CTRL_PHY_RST;
4773
4774	/* Gate automatic PHY configuration by hardware on
4775	* non-managed 82579
4776	*/
4777	if ((hw->mac.type == e1000_pch2lan) &&
4778	!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4779	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
4780	}
4781	ret_val = e1000_acquire_swflag_ich8lan(hw);
4782	e_dbg("Issuing a global reset to ich8lan\n");
4783	ew32(CTRL, (ctrl | E1000_CTRL_RST));
4784	/* cannot issue a flush here because it hangs the hardware */
4785	msleep(msecs: 20);
4786
4787	/* Set Phy Config Counter to 50msec */
4788	if (hw->mac.type == e1000_pch2lan) {
4789	reg = er32(FEXTNVM3);
4790	reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4791	reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4792	ew32(FEXTNVM3, reg);
4793	}
4794
4795	if (!ret_val)
4796	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
4797
4798	if (ctrl & E1000_CTRL_PHY_RST) {
4799	ret_val = hw->phy.ops.get_cfg_done(hw);
4800	if (ret_val)
4801	return ret_val;
4802
4803	ret_val = e1000_post_phy_reset_ich8lan(hw);
4804	if (ret_val)
4805	return ret_val;
4806	}
4807
4808	/* For PCH, this write will make sure that any noise
4809	* will be detected as a CRC error and be dropped rather than show up
4810	* as a bad packet to the DMA engine.
4811	*/
4812	if (hw->mac.type == e1000_pchlan)
4813	ew32(CRC_OFFSET, 0x65656565);
4814
4815	ew32(IMC, 0xffffffff);
4816	er32(ICR);
4817
4818	reg = er32(KABGTXD);
4819	reg |= E1000_KABGTXD_BGSQLBIAS;
4820	ew32(KABGTXD, reg);
4821
4822	return 0;
4823	}
4824
4825	/**
4826	* e1000_init_hw_ich8lan - Initialize the hardware
4827	* @hw: pointer to the HW structure
4828	*
4829	* Prepares the hardware for transmit and receive by doing the following:
4830	* - initialize hardware bits
4831	* - initialize LED identification
4832	* - setup receive address registers
4833	* - setup flow control
4834	* - setup transmit descriptors
4835	* - clear statistics
4836	**/
4837	static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4838	{
4839	struct e1000_mac_info *mac = &hw->mac;
4840	u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4841	s32 ret_val;
4842	u16 i;
4843
4844	e1000_initialize_hw_bits_ich8lan(hw);
4845
4846	/* Initialize identification LED */
4847	ret_val = mac->ops.id_led_init(hw);
4848	/* An error is not fatal and we should not stop init due to this */
4849	if (ret_val)
4850	e_dbg("Error initializing identification LED\n");
4851
4852	/* Setup the receive address. */
4853	e1000e_init_rx_addrs(hw, rar_count: mac->rar_entry_count);
4854
4855	/* Zero out the Multicast HASH table */
4856	e_dbg("Zeroing the MTA\n");
4857	for (i = 0; i < mac->mta_reg_count; i++)
4858	E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4859
4860	/* The 82578 Rx buffer will stall if wakeup is enabled in host and
4861	* the ME. Disable wakeup by clearing the host wakeup bit.
4862	* Reset the phy after disabling host wakeup to reset the Rx buffer.
4863	*/
4864	if (hw->phy.type == e1000_phy_82578) {
4865	e1e_rphy(hw, BM_PORT_GEN_CFG, data: &i);
4866	i &= ~BM_WUC_HOST_WU_BIT;
4867	e1e_wphy(hw, BM_PORT_GEN_CFG, data: i);
4868	ret_val = e1000_phy_hw_reset_ich8lan(hw);
4869	if (ret_val)
4870	return ret_val;
4871	}
4872
4873	/* Setup link and flow control */
4874	ret_val = mac->ops.setup_link(hw);
4875
4876	/* Set the transmit descriptor write-back policy for both queues */
4877	txdctl = er32(TXDCTL(0));
4878	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4879	E1000_TXDCTL_FULL_TX_DESC_WB);
4880	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4881	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4882	ew32(TXDCTL(0), txdctl);
4883	txdctl = er32(TXDCTL(1));
4884	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4885	E1000_TXDCTL_FULL_TX_DESC_WB);
4886	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4887	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4888	ew32(TXDCTL(1), txdctl);
4889
4890	/* ICH8 has opposite polarity of no_snoop bits.
4891	* By default, we should use snoop behavior.
4892	*/
4893	if (mac->type == e1000_ich8lan)
4894	snoop = PCIE_ICH8_SNOOP_ALL;
4895	else
4896	snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4897	e1000e_set_pcie_no_snoop(hw, no_snoop: snoop);
4898
4899	/* Enable workaround for packet loss issue on TGP PCH
4900	* Do not gate DMA clock from the modPHY block
4901	*/
4902	if (mac->type >= e1000_pch_tgp) {
4903	fflt_dbg = er32(FFLT_DBG);
4904	fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4905	ew32(FFLT_DBG, fflt_dbg);
4906	}
4907
4908	ctrl_ext = er32(CTRL_EXT);
4909	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4910	ew32(CTRL_EXT, ctrl_ext);
4911
4912	/* Clear all of the statistics registers (clear on read). It is
4913	* important that we do this after we have tried to establish link
4914	* because the symbol error count will increment wildly if there
4915	* is no link.
4916	*/
4917	e1000_clear_hw_cntrs_ich8lan(hw);
4918
4919	return ret_val;
4920	}
4921
4922	/**
4923	* e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4924	* @hw: pointer to the HW structure
4925	*
4926	* Sets/Clears required hardware bits necessary for correctly setting up the
4927	* hardware for transmit and receive.
4928	**/
4929	static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4930	{
4931	u32 reg;
4932
4933	/* Extended Device Control */
4934	reg = er32(CTRL_EXT);
4935	reg |= BIT(22);
4936	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
4937	if (hw->mac.type >= e1000_pchlan)
4938	reg |= E1000_CTRL_EXT_PHYPDEN;
4939	ew32(CTRL_EXT, reg);
4940
4941	/* Transmit Descriptor Control 0 */
4942	reg = er32(TXDCTL(0));
4943	reg |= BIT(22);
4944	ew32(TXDCTL(0), reg);
4945
4946	/* Transmit Descriptor Control 1 */
4947	reg = er32(TXDCTL(1));
4948	reg |= BIT(22);
4949	ew32(TXDCTL(1), reg);
4950
4951	/* Transmit Arbitration Control 0 */
4952	reg = er32(TARC(0));
4953	if (hw->mac.type == e1000_ich8lan)
4954	reg |= BIT(28) | BIT(29);
4955	reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4956	ew32(TARC(0), reg);
4957
4958	/* Transmit Arbitration Control 1 */
4959	reg = er32(TARC(1));
4960	if (er32(TCTL) & E1000_TCTL_MULR)
4961	reg &= ~BIT(28);
4962	else
4963	reg |= BIT(28);
4964	reg |= BIT(24) | BIT(26) | BIT(30);
4965	ew32(TARC(1), reg);
4966
4967	/* Device Status */
4968	if (hw->mac.type == e1000_ich8lan) {
4969	reg = er32(STATUS);
4970	reg &= ~BIT(31);
4971	ew32(STATUS, reg);
4972	}
4973
4974	/* work-around descriptor data corruption issue during nfs v2 udp
4975	* traffic, just disable the nfs filtering capability
4976	*/
4977	reg = er32(RFCTL);
4978	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4979
4980	/* Disable IPv6 extension header parsing because some malformed
4981	* IPv6 headers can hang the Rx.
4982	*/
4983	if (hw->mac.type == e1000_ich8lan)
4984	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4985	ew32(RFCTL, reg);
4986
4987	/* Enable ECC on Lynxpoint */
4988	if (hw->mac.type >= e1000_pch_lpt) {
4989	reg = er32(PBECCSTS);
4990	reg |= E1000_PBECCSTS_ECC_ENABLE;
4991	ew32(PBECCSTS, reg);
4992
4993	reg = er32(CTRL);
4994	reg |= E1000_CTRL_MEHE;
4995	ew32(CTRL, reg);
4996	}
4997	}
4998
4999	/**
5000	* e1000_setup_link_ich8lan - Setup flow control and link settings
5001	* @hw: pointer to the HW structure
5002	*
5003	* Determines which flow control settings to use, then configures flow
5004	* control. Calls the appropriate media-specific link configuration
5005	* function. Assuming the adapter has a valid link partner, a valid link
5006	* should be established. Assumes the hardware has previously been reset
5007	* and the transmitter and receiver are not enabled.
5008	**/
5009	static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5010	{
5011	s32 ret_val;
5012
5013	if (hw->phy.ops.check_reset_block(hw))
5014	return 0;
5015
5016	/* ICH parts do not have a word in the NVM to determine
5017	* the default flow control setting, so we explicitly
5018	* set it to full.
5019	*/
5020	if (hw->fc.requested_mode == e1000_fc_default) {
5021	/* Workaround h/w hang when Tx flow control enabled */
5022	if (hw->mac.type == e1000_pchlan)
5023	hw->fc.requested_mode = e1000_fc_rx_pause;
5024	else
5025	hw->fc.requested_mode = e1000_fc_full;
5026	}
5027
5028	/* Save off the requested flow control mode for use later. Depending
5029	* on the link partner's capabilities, we may or may not use this mode.
5030	*/
5031	hw->fc.current_mode = hw->fc.requested_mode;
5032
5033	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5034
5035	/* Continue to configure the copper link. */
5036	ret_val = hw->mac.ops.setup_physical_interface(hw);
5037	if (ret_val)
5038	return ret_val;
5039
5040	ew32(FCTTV, hw->fc.pause_time);
5041	if ((hw->phy.type == e1000_phy_82578) ||
5042	(hw->phy.type == e1000_phy_82579) ||
5043	(hw->phy.type == e1000_phy_i217) ||
5044	(hw->phy.type == e1000_phy_82577)) {
5045	ew32(FCRTV_PCH, hw->fc.refresh_time);
5046
5047	ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5048	data: hw->fc.pause_time);
5049	if (ret_val)
5050	return ret_val;
5051	}
5052
5053	return e1000e_set_fc_watermarks(hw);
5054	}
5055
5056	/**
5057	* e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5058	* @hw: pointer to the HW structure
5059	*
5060	* Configures the kumeran interface to the PHY to wait the appropriate time
5061	* when polling the PHY, then call the generic setup_copper_link to finish
5062	* configuring the copper link.
5063	**/
5064	static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5065	{
5066	u32 ctrl;
5067	s32 ret_val;
5068	u16 reg_data;
5069
5070	ctrl = er32(CTRL);
5071	ctrl |= E1000_CTRL_SLU;
5072	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5073	ew32(CTRL, ctrl);
5074
5075	/* Set the mac to wait the maximum time between each iteration
5076	* and increase the max iterations when polling the phy;
5077	* this fixes erroneous timeouts at 10Mbps.
5078	*/
5079	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, data: 0xFFFF);
5080	if (ret_val)
5081	return ret_val;
5082	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5083	data: &reg_data);
5084	if (ret_val)
5085	return ret_val;
5086	reg_data |= 0x3F;
5087	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5088	data: reg_data);
5089	if (ret_val)
5090	return ret_val;
5091
5092	switch (hw->phy.type) {
5093	case e1000_phy_igp_3:
5094	ret_val = e1000e_copper_link_setup_igp(hw);
5095	if (ret_val)
5096	return ret_val;
5097	break;
5098	case e1000_phy_bm:
5099	case e1000_phy_82578:
5100	ret_val = e1000e_copper_link_setup_m88(hw);
5101	if (ret_val)
5102	return ret_val;
5103	break;
5104	case e1000_phy_82577:
5105	case e1000_phy_82579:
5106	ret_val = e1000_copper_link_setup_82577(hw);
5107	if (ret_val)
5108	return ret_val;
5109	break;
5110	case e1000_phy_ife:
5111	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, data: &reg_data);
5112	if (ret_val)
5113	return ret_val;
5114
5115	reg_data &= ~IFE_PMC_AUTO_MDIX;
5116
5117	switch (hw->phy.mdix) {
5118	case 1:
5119	reg_data &= ~IFE_PMC_FORCE_MDIX;
5120	break;
5121	case 2:
5122	reg_data |= IFE_PMC_FORCE_MDIX;
5123	break;
5124	case 0:
5125	default:
5126	reg_data |= IFE_PMC_AUTO_MDIX;
5127	break;
5128	}
5129	ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data: reg_data);
5130	if (ret_val)
5131	return ret_val;
5132	break;
5133	default:
5134	break;
5135	}
5136
5137	return e1000e_setup_copper_link(hw);
5138	}
5139
5140	/**
5141	* e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5142	* @hw: pointer to the HW structure
5143	*
5144	* Calls the PHY specific link setup function and then calls the
5145	* generic setup_copper_link to finish configuring the link for
5146	* Lynxpoint PCH devices
5147	**/
5148	static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5149	{
5150	u32 ctrl;
5151	s32 ret_val;
5152
5153	ctrl = er32(CTRL);
5154	ctrl |= E1000_CTRL_SLU;
5155	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5156	ew32(CTRL, ctrl);
5157
5158	ret_val = e1000_copper_link_setup_82577(hw);
5159	if (ret_val)
5160	return ret_val;
5161
5162	return e1000e_setup_copper_link(hw);
5163	}
5164
5165	/**
5166	* e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5167	* @hw: pointer to the HW structure
5168	* @speed: pointer to store current link speed
5169	* @duplex: pointer to store the current link duplex
5170	*
5171	* Calls the generic get_speed_and_duplex to retrieve the current link
5172	* information and then calls the Kumeran lock loss workaround for links at
5173	* gigabit speeds.
5174	**/
5175	static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5176	u16 *duplex)
5177	{
5178	s32 ret_val;
5179
5180	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5181	if (ret_val)
5182	return ret_val;
5183
5184	if ((hw->mac.type == e1000_ich8lan) &&
5185	(hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5186	ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5187	}
5188
5189	return ret_val;
5190	}
5191
5192	/**
5193	* e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5194	* @hw: pointer to the HW structure
5195	*
5196	* Work-around for 82566 Kumeran PCS lock loss:
5197	* On link status change (i.e. PCI reset, speed change) and link is up and
5198	* speed is gigabit-
5199	* 0) if workaround is optionally disabled do nothing
5200	* 1) wait 1ms for Kumeran link to come up
5201	* 2) check Kumeran Diagnostic register PCS lock loss bit
5202	* 3) if not set the link is locked (all is good), otherwise...
5203	* 4) reset the PHY
5204	* 5) repeat up to 10 times
5205	* Note: this is only called for IGP3 copper when speed is 1gb.
5206	**/
5207	static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5208	{
5209	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5210	u32 phy_ctrl;
5211	s32 ret_val;
5212	u16 i, data;
5213	bool link;
5214
5215	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5216	return 0;
5217
5218	/* Make sure link is up before proceeding. If not just return.
5219	* Attempting this while link is negotiating fouled up link
5220	* stability
5221	*/
5222	ret_val = e1000e_phy_has_link_generic(hw, iterations: 1, usec_interval: 0, success: &link);
5223	if (!link)
5224	return 0;
5225
5226	for (i = 0; i < 10; i++) {
5227	/* read once to clear */
5228	ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, data: &data);
5229	if (ret_val)
5230	return ret_val;
5231	/* and again to get new status */
5232	ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, data: &data);
5233	if (ret_val)
5234	return ret_val;
5235
5236	/* check for PCS lock */
5237	if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5238	return 0;
5239
5240	/* Issue PHY reset */
5241	e1000_phy_hw_reset(hw);
5242	mdelay(5);
5243	}
5244	/* Disable GigE link negotiation */
5245	phy_ctrl = er32(PHY_CTRL);
5246	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5247	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5248	ew32(PHY_CTRL, phy_ctrl);
5249
5250	/* Call gig speed drop workaround on Gig disable before accessing
5251	* any PHY registers
5252	*/
5253	e1000e_gig_downshift_workaround_ich8lan(hw);
5254
5255	/* unable to acquire PCS lock */
5256	return -E1000_ERR_PHY;
5257	}
5258
5259	/**
5260	* e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5261	* @hw: pointer to the HW structure
5262	* @state: boolean value used to set the current Kumeran workaround state
5263	*
5264	* If ICH8, set the current Kumeran workaround state (enabled - true
5265	* /disabled - false).
5266	**/
5267	void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5268	bool state)
5269	{
5270	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5271
5272	if (hw->mac.type != e1000_ich8lan) {
5273	e_dbg("Workaround applies to ICH8 only.\n");
5274	return;
5275	}
5276
5277	dev_spec->kmrn_lock_loss_workaround_enabled = state;
5278	}
5279
5280	/**
5281	* e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5282	* @hw: pointer to the HW structure
5283	*
5284	* Workaround for 82566 power-down on D3 entry:
5285	* 1) disable gigabit link
5286	* 2) write VR power-down enable
5287	* 3) read it back
5288	* Continue if successful, else issue LCD reset and repeat
5289	**/
5290	void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5291	{
5292	u32 reg;
5293	u16 data;
5294	u8 retry = 0;
5295
5296	if (hw->phy.type != e1000_phy_igp_3)
5297	return;
5298
5299	/* Try the workaround twice (if needed) */
5300	do {
5301	/* Disable link */
5302	reg = er32(PHY_CTRL);
5303	reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5304	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5305	ew32(PHY_CTRL, reg);
5306
5307	/* Call gig speed drop workaround on Gig disable before
5308	* accessing any PHY registers
5309	*/
5310	if (hw->mac.type == e1000_ich8lan)
5311	e1000e_gig_downshift_workaround_ich8lan(hw);
5312
5313	/* Write VR power-down enable */
5314	e1e_rphy(hw, IGP3_VR_CTRL, data: &data);
5315	data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5316	e1e_wphy(hw, IGP3_VR_CTRL, data: data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5317
5318	/* Read it back and test */
5319	e1e_rphy(hw, IGP3_VR_CTRL, data: &data);
5320	data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5321	if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5322	break;
5323
5324	/* Issue PHY reset and repeat at most one more time */
5325	reg = er32(CTRL);
5326	ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5327	retry++;
5328	} while (retry);
5329	}
5330
5331	/**
5332	* e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5333	* @hw: pointer to the HW structure
5334	*
5335	* Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5336	* LPLU, Gig disable, MDIC PHY reset):
5337	* 1) Set Kumeran Near-end loopback
5338	* 2) Clear Kumeran Near-end loopback
5339	* Should only be called for ICH8[m] devices with any 1G Phy.
5340	**/
5341	void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5342	{
5343	s32 ret_val;
5344	u16 reg_data;
5345
5346	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5347	return;
5348
5349	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5350	data: &reg_data);
5351	if (ret_val)
5352	return;
5353	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5354	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5355	data: reg_data);
5356	if (ret_val)
5357	return;
5358	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5359	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, data: reg_data);
5360	}
5361
5362	/**
5363	* e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5364	* @hw: pointer to the HW structure
5365	*
5366	* During S0 to Sx transition, it is possible the link remains at gig
5367	* instead of negotiating to a lower speed. Before going to Sx, set
5368	* 'Gig Disable' to force link speed negotiation to a lower speed based on
5369	* the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5370	* the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5371	* needs to be written.
5372	* Parts that support (and are linked to a partner which support) EEE in
5373	* 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5374	* than 10Mbps w/o EEE.
5375	**/
5376	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5377	{
5378	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5379	u32 phy_ctrl;
5380	s32 ret_val;
5381
5382	phy_ctrl = er32(PHY_CTRL);
5383	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5384
5385	if (hw->phy.type == e1000_phy_i217) {
5386	u16 phy_reg, device_id = hw->adapter->pdev->device;
5387
5388	if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5389	(device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5390	(device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5391	(device_id == E1000_DEV_ID_PCH_I218_V3) ||
5392	(hw->mac.type >= e1000_pch_spt)) {
5393	u32 fextnvm6 = er32(FEXTNVM6);
5394
5395	ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5396	}
5397
5398	ret_val = hw->phy.ops.acquire(hw);
5399	if (ret_val)
5400	goto out;
5401
5402	if (!dev_spec->eee_disable) {
5403	u16 eee_advert;
5404
5405	ret_val =
5406	e1000_read_emi_reg_locked(hw,
5407	I217_EEE_ADVERTISEMENT,
5408	data: &eee_advert);
5409	if (ret_val)
5410	goto release;
5411
5412	/* Disable LPLU if both link partners support 100BaseT
5413	* EEE and 100Full is advertised on both ends of the
5414	* link, and enable Auto Enable LPI since there will
5415	* be no driver to enable LPI while in Sx.
5416	*/
5417	if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5418	(dev_spec->eee_lp_ability &
5419	I82579_EEE_100_SUPPORTED) &&
5420	(hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5421	phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5422	E1000_PHY_CTRL_NOND0A_LPLU);
5423
5424	/* Set Auto Enable LPI after link up */
5425	e1e_rphy_locked(hw,
5426	I217_LPI_GPIO_CTRL, data: &phy_reg);
5427	phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5428	e1e_wphy_locked(hw,
5429	I217_LPI_GPIO_CTRL, data: phy_reg);
5430	}
5431	}
5432
5433	/* For i217 Intel Rapid Start Technology support,
5434	* when the system is going into Sx and no manageability engine
5435	* is present, the driver must configure proxy to reset only on
5436	* power good. LPI (Low Power Idle) state must also reset only
5437	* on power good, as well as the MTA (Multicast table array).
5438	* The SMBus release must also be disabled on LCD reset.
5439	*/
5440	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5441	/* Enable proxy to reset only on power good. */
5442	e1e_rphy_locked(hw, I217_PROXY_CTRL, data: &phy_reg);
5443	phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5444	e1e_wphy_locked(hw, I217_PROXY_CTRL, data: phy_reg);
5445
5446	/* Set bit enable LPI (EEE) to reset only on
5447	* power good.
5448	*/
5449	e1e_rphy_locked(hw, I217_SxCTRL, data: &phy_reg);
5450	phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5451	e1e_wphy_locked(hw, I217_SxCTRL, data: phy_reg);
5452
5453	/* Disable the SMB release on LCD reset. */
5454	e1e_rphy_locked(hw, I217_MEMPWR, data: &phy_reg);
5455	phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5456	e1e_wphy_locked(hw, I217_MEMPWR, data: phy_reg);
5457	}
5458
5459	/* Enable MTA to reset for Intel Rapid Start Technology
5460	* Support
5461	*/
5462	e1e_rphy_locked(hw, I217_CGFREG, data: &phy_reg);
5463	phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5464	e1e_wphy_locked(hw, I217_CGFREG, data: phy_reg);
5465
5466	release:
5467	hw->phy.ops.release(hw);
5468	}
5469	out:
5470	ew32(PHY_CTRL, phy_ctrl);
5471
5472	if (hw->mac.type == e1000_ich8lan)
5473	e1000e_gig_downshift_workaround_ich8lan(hw);
5474
5475	if (hw->mac.type >= e1000_pchlan) {
5476	e1000_oem_bits_config_ich8lan(hw, d0_state: false);
5477
5478	/* Reset PHY to activate OEM bits on 82577/8 */
5479	if (hw->mac.type == e1000_pchlan)
5480	e1000e_phy_hw_reset_generic(hw);
5481
5482	ret_val = hw->phy.ops.acquire(hw);
5483	if (ret_val)
5484	return;
5485	e1000_write_smbus_addr(hw);
5486	hw->phy.ops.release(hw);
5487	}
5488	}
5489
5490	/**
5491	* e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5492	* @hw: pointer to the HW structure
5493	*
5494	* During Sx to S0 transitions on non-managed devices or managed devices
5495	* on which PHY resets are not blocked, if the PHY registers cannot be
5496	* accessed properly by the s/w toggle the LANPHYPC value to power cycle
5497	* the PHY.
5498	* On i217, setup Intel Rapid Start Technology.
5499	**/
5500	void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5501	{
5502	s32 ret_val;
5503
5504	if (hw->mac.type < e1000_pch2lan)
5505	return;
5506
5507	ret_val = e1000_init_phy_workarounds_pchlan(hw);
5508	if (ret_val) {
5509	e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5510	return;
5511	}
5512
5513	/* For i217 Intel Rapid Start Technology support when the system
5514	* is transitioning from Sx and no manageability engine is present
5515	* configure SMBus to restore on reset, disable proxy, and enable
5516	* the reset on MTA (Multicast table array).
5517	*/
5518	if (hw->phy.type == e1000_phy_i217) {
5519	u16 phy_reg;
5520
5521	ret_val = hw->phy.ops.acquire(hw);
5522	if (ret_val) {
5523	e_dbg("Failed to setup iRST\n");
5524	return;
5525	}
5526
5527	/* Clear Auto Enable LPI after link up */
5528	e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, data: &phy_reg);
5529	phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5530	e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, data: phy_reg);
5531
5532	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5533	/* Restore clear on SMB if no manageability engine
5534	* is present
5535	*/
5536	ret_val = e1e_rphy_locked(hw, I217_MEMPWR, data: &phy_reg);
5537	if (ret_val)
5538	goto release;
5539	phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5540	e1e_wphy_locked(hw, I217_MEMPWR, data: phy_reg);
5541
5542	/* Disable Proxy */
5543	e1e_wphy_locked(hw, I217_PROXY_CTRL, data: 0);
5544	}
5545	/* Enable reset on MTA */
5546	ret_val = e1e_rphy_locked(hw, I217_CGFREG, data: &phy_reg);
5547	if (ret_val)
5548	goto release;
5549	phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5550	e1e_wphy_locked(hw, I217_CGFREG, data: phy_reg);
5551	release:
5552	if (ret_val)
5553	e_dbg("Error %d in resume workarounds\n", ret_val);
5554	hw->phy.ops.release(hw);
5555	}
5556	}
5557
5558	/**
5559	* e1000_cleanup_led_ich8lan - Restore the default LED operation
5560	* @hw: pointer to the HW structure
5561	*
5562	* Return the LED back to the default configuration.
5563	**/
5564	static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5565	{
5566	if (hw->phy.type == e1000_phy_ife)
5567	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, data: 0);
5568
5569	ew32(LEDCTL, hw->mac.ledctl_default);
5570	return 0;
5571	}
5572
5573	/**
5574	* e1000_led_on_ich8lan - Turn LEDs on
5575	* @hw: pointer to the HW structure
5576	*
5577	* Turn on the LEDs.
5578	**/
5579	static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5580	{
5581	if (hw->phy.type == e1000_phy_ife)
5582	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5583	data: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5584
5585	ew32(LEDCTL, hw->mac.ledctl_mode2);
5586	return 0;
5587	}
5588
5589	/**
5590	* e1000_led_off_ich8lan - Turn LEDs off
5591	* @hw: pointer to the HW structure
5592	*
5593	* Turn off the LEDs.
5594	**/
5595	static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5596	{
5597	if (hw->phy.type == e1000_phy_ife)
5598	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5599	data: (IFE_PSCL_PROBE_MODE |
5600	IFE_PSCL_PROBE_LEDS_OFF));
5601
5602	ew32(LEDCTL, hw->mac.ledctl_mode1);
5603	return 0;
5604	}
5605
5606	/**
5607	* e1000_setup_led_pchlan - Configures SW controllable LED
5608	* @hw: pointer to the HW structure
5609	*
5610	* This prepares the SW controllable LED for use.
5611	**/
5612	static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5613	{
5614	return e1e_wphy(hw, HV_LED_CONFIG, data: (u16)hw->mac.ledctl_mode1);
5615	}
5616
5617	/**
5618	* e1000_cleanup_led_pchlan - Restore the default LED operation
5619	* @hw: pointer to the HW structure
5620	*
5621	* Return the LED back to the default configuration.
5622	**/
5623	static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5624	{
5625	return e1e_wphy(hw, HV_LED_CONFIG, data: (u16)hw->mac.ledctl_default);
5626	}
5627
5628	/**
5629	* e1000_led_on_pchlan - Turn LEDs on
5630	* @hw: pointer to the HW structure
5631	*
5632	* Turn on the LEDs.
5633	**/
5634	static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5635	{
5636	u16 data = (u16)hw->mac.ledctl_mode2;
5637	u32 i, led;
5638
5639	/* If no link, then turn LED on by setting the invert bit
5640	* for each LED that's mode is "link_up" in ledctl_mode2.
5641	*/
5642	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5643	for (i = 0; i < 3; i++) {
5644	led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5645	if ((led & E1000_PHY_LED0_MODE_MASK) !=
5646	E1000_LEDCTL_MODE_LINK_UP)
5647	continue;
5648	if (led & E1000_PHY_LED0_IVRT)
5649	data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5650	else
5651	data |= (E1000_PHY_LED0_IVRT << (i * 5));
5652	}
5653	}
5654
5655	return e1e_wphy(hw, HV_LED_CONFIG, data);
5656	}
5657
5658	/**
5659	* e1000_led_off_pchlan - Turn LEDs off
5660	* @hw: pointer to the HW structure
5661	*
5662	* Turn off the LEDs.
5663	**/
5664	static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5665	{
5666	u16 data = (u16)hw->mac.ledctl_mode1;
5667	u32 i, led;
5668
5669	/* If no link, then turn LED off by clearing the invert bit
5670	* for each LED that's mode is "link_up" in ledctl_mode1.
5671	*/
5672	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5673	for (i = 0; i < 3; i++) {
5674	led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5675	if ((led & E1000_PHY_LED0_MODE_MASK) !=
5676	E1000_LEDCTL_MODE_LINK_UP)
5677	continue;
5678	if (led & E1000_PHY_LED0_IVRT)
5679	data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5680	else
5681	data |= (E1000_PHY_LED0_IVRT << (i * 5));
5682	}
5683	}
5684
5685	return e1e_wphy(hw, HV_LED_CONFIG, data);
5686	}
5687
5688	/**
5689	* e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5690	* @hw: pointer to the HW structure
5691	*
5692	* Read appropriate register for the config done bit for completion status
5693	* and configure the PHY through s/w for EEPROM-less parts.
5694	*
5695	* NOTE: some silicon which is EEPROM-less will fail trying to read the
5696	* config done bit, so only an error is logged and continues. If we were
5697	* to return with error, EEPROM-less silicon would not be able to be reset
5698	* or change link.
5699	**/
5700	static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5701	{
5702	s32 ret_val = 0;
5703	u32 bank = 0;
5704	u32 status;
5705
5706	e1000e_get_cfg_done_generic(hw);
5707
5708	/* Wait for indication from h/w that it has completed basic config */
5709	if (hw->mac.type >= e1000_ich10lan) {
5710	e1000_lan_init_done_ich8lan(hw);
5711	} else {
5712	ret_val = e1000e_get_auto_rd_done(hw);
5713	if (ret_val) {
5714	/* When auto config read does not complete, do not
5715	* return with an error. This can happen in situations
5716	* where there is no eeprom and prevents getting link.
5717	*/
5718	e_dbg("Auto Read Done did not complete\n");
5719	ret_val = 0;
5720	}
5721	}
5722
5723	/* Clear PHY Reset Asserted bit */
5724	status = er32(STATUS);
5725	if (status & E1000_STATUS_PHYRA)
5726	ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5727	else
5728	e_dbg("PHY Reset Asserted not set - needs delay\n");
5729
5730	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
5731	if (hw->mac.type <= e1000_ich9lan) {
5732	if (!(er32(EECD) & E1000_EECD_PRES) &&
5733	(hw->phy.type == e1000_phy_igp_3)) {
5734	e1000e_phy_init_script_igp3(hw);
5735	}
5736	} else {
5737	if (e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank)) {
5738	/* Maybe we should do a basic PHY config */
5739	e_dbg("EEPROM not present\n");
5740	ret_val = -E1000_ERR_CONFIG;
5741	}
5742	}
5743
5744	return ret_val;
5745	}
5746
5747	/**
5748	* e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5749	* @hw: pointer to the HW structure
5750	*
5751	* In the case of a PHY power down to save power, or to turn off link during a
5752	* driver unload, or wake on lan is not enabled, remove the link.
5753	**/
5754	static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5755	{
5756	/* If the management interface is not enabled, then power down */
5757	if (!(hw->mac.ops.check_mng_mode(hw) ||
5758	hw->phy.ops.check_reset_block(hw)))
5759	e1000_power_down_phy_copper(hw);
5760	}
5761
5762	/**
5763	* e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5764	* @hw: pointer to the HW structure
5765	*
5766	* Clears hardware counters specific to the silicon family and calls
5767	* clear_hw_cntrs_generic to clear all general purpose counters.
5768	**/
5769	static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5770	{
5771	u16 phy_data;
5772	s32 ret_val;
5773
5774	e1000e_clear_hw_cntrs_base(hw);
5775
5776	er32(ALGNERRC);
5777	er32(RXERRC);
5778	er32(TNCRS);
5779	er32(CEXTERR);
5780	er32(TSCTC);
5781	er32(TSCTFC);
5782
5783	er32(MGTPRC);
5784	er32(MGTPDC);
5785	er32(MGTPTC);
5786
5787	er32(IAC);
5788	er32(ICRXOC);
5789
5790	/* Clear PHY statistics registers */
5791	if ((hw->phy.type == e1000_phy_82578) ||
5792	(hw->phy.type == e1000_phy_82579) ||
5793	(hw->phy.type == e1000_phy_i217) ||
5794	(hw->phy.type == e1000_phy_82577)) {
5795	ret_val = hw->phy.ops.acquire(hw);
5796	if (ret_val)
5797	return;
5798	ret_val = hw->phy.ops.set_page(hw,
5799	HV_STATS_PAGE << IGP_PAGE_SHIFT);
5800	if (ret_val)
5801	goto release;
5802	hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5803	hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5804	hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5805	hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5806	hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5807	hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5808	hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5809	hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5810	hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5811	hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5812	hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5813	hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5814	hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5815	hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5816	release:
5817	hw->phy.ops.release(hw);
5818	}
5819	}
5820
5821	static const struct e1000_mac_operations ich8_mac_ops = {
5822	/* check_mng_mode dependent on mac type */
5823	.check_for_link = e1000_check_for_copper_link_ich8lan,
5824	/* cleanup_led dependent on mac type */
5825	.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5826	.get_bus_info = e1000_get_bus_info_ich8lan,
5827	.set_lan_id = e1000_set_lan_id_single_port,
5828	.get_link_up_info = e1000_get_link_up_info_ich8lan,
5829	/* led_on dependent on mac type */
5830	/* led_off dependent on mac type */
5831	.update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5832	.reset_hw = e1000_reset_hw_ich8lan,
5833	.init_hw = e1000_init_hw_ich8lan,
5834	.setup_link = e1000_setup_link_ich8lan,
5835	.setup_physical_interface = e1000_setup_copper_link_ich8lan,
5836	/* id_led_init dependent on mac type */
5837	.config_collision_dist = e1000e_config_collision_dist_generic,
5838	.rar_set = e1000e_rar_set_generic,
5839	.rar_get_count = e1000e_rar_get_count_generic,
5840	};
5841
5842	static const struct e1000_phy_operations ich8_phy_ops = {
5843	.acquire = e1000_acquire_swflag_ich8lan,
5844	.check_reset_block = e1000_check_reset_block_ich8lan,
5845	.commit = NULL,
5846	.get_cfg_done = e1000_get_cfg_done_ich8lan,
5847	.get_cable_length = e1000e_get_cable_length_igp_2,
5848	.read_reg = e1000e_read_phy_reg_igp,
5849	.release = e1000_release_swflag_ich8lan,
5850	.reset = e1000_phy_hw_reset_ich8lan,
5851	.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5852	.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5853	.write_reg = e1000e_write_phy_reg_igp,
5854	};
5855
5856	static const struct e1000_nvm_operations ich8_nvm_ops = {
5857	.acquire = e1000_acquire_nvm_ich8lan,
5858	.read = e1000_read_nvm_ich8lan,
5859	.release = e1000_release_nvm_ich8lan,
5860	.reload = e1000e_reload_nvm_generic,
5861	.update = e1000_update_nvm_checksum_ich8lan,
5862	.valid_led_default = e1000_valid_led_default_ich8lan,
5863	.validate = e1000_validate_nvm_checksum_ich8lan,
5864	.write = e1000_write_nvm_ich8lan,
5865	};
5866
5867	static const struct e1000_nvm_operations spt_nvm_ops = {
5868	.acquire = e1000_acquire_nvm_ich8lan,
5869	.release = e1000_release_nvm_ich8lan,
5870	.read = e1000_read_nvm_spt,
5871	.update = e1000_update_nvm_checksum_spt,
5872	.reload = e1000e_reload_nvm_generic,
5873	.valid_led_default = e1000_valid_led_default_ich8lan,
5874	.validate = e1000_validate_nvm_checksum_ich8lan,
5875	.write = e1000_write_nvm_ich8lan,
5876	};
5877
5878	const struct e1000_info e1000_ich8_info = {
5879	.mac = e1000_ich8lan,
5880	.flags = FLAG_HAS_WOL
5881	| FLAG_IS_ICH
5882	| FLAG_HAS_CTRLEXT_ON_LOAD
5883	| FLAG_HAS_AMT
5884	| FLAG_HAS_FLASH
5885	| FLAG_APME_IN_WUC,
5886	.pba = 8,
5887	.max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5888	.get_variants = e1000_get_variants_ich8lan,
5889	.mac_ops = &ich8_mac_ops,
5890	.phy_ops = &ich8_phy_ops,
5891	.nvm_ops = &ich8_nvm_ops,
5892	};
5893
5894	const struct e1000_info e1000_ich9_info = {
5895	.mac = e1000_ich9lan,
5896	.flags = FLAG_HAS_JUMBO_FRAMES
5897	| FLAG_IS_ICH
5898	| FLAG_HAS_WOL
5899	| FLAG_HAS_CTRLEXT_ON_LOAD
5900	| FLAG_HAS_AMT
5901	| FLAG_HAS_FLASH
5902	| FLAG_APME_IN_WUC,
5903	.pba = 18,
5904	.max_hw_frame_size = DEFAULT_JUMBO,
5905	.get_variants = e1000_get_variants_ich8lan,
5906	.mac_ops = &ich8_mac_ops,
5907	.phy_ops = &ich8_phy_ops,
5908	.nvm_ops = &ich8_nvm_ops,
5909	};
5910
5911	const struct e1000_info e1000_ich10_info = {
5912	.mac = e1000_ich10lan,
5913	.flags = FLAG_HAS_JUMBO_FRAMES
5914	| FLAG_IS_ICH
5915	| FLAG_HAS_WOL
5916	| FLAG_HAS_CTRLEXT_ON_LOAD
5917	| FLAG_HAS_AMT
5918	| FLAG_HAS_FLASH
5919	| FLAG_APME_IN_WUC,
5920	.pba = 18,
5921	.max_hw_frame_size = DEFAULT_JUMBO,
5922	.get_variants = e1000_get_variants_ich8lan,
5923	.mac_ops = &ich8_mac_ops,
5924	.phy_ops = &ich8_phy_ops,
5925	.nvm_ops = &ich8_nvm_ops,
5926	};
5927
5928	const struct e1000_info e1000_pch_info = {
5929	.mac = e1000_pchlan,
5930	.flags = FLAG_IS_ICH
5931	| FLAG_HAS_WOL
5932	| FLAG_HAS_CTRLEXT_ON_LOAD
5933	| FLAG_HAS_AMT
5934	| FLAG_HAS_FLASH
5935	| FLAG_HAS_JUMBO_FRAMES
5936	| FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5937	| FLAG_APME_IN_WUC,
5938	.flags2 = FLAG2_HAS_PHY_STATS,
5939	.pba = 26,
5940	.max_hw_frame_size = 4096,
5941	.get_variants = e1000_get_variants_ich8lan,
5942	.mac_ops = &ich8_mac_ops,
5943	.phy_ops = &ich8_phy_ops,
5944	.nvm_ops = &ich8_nvm_ops,
5945	};
5946
5947	const struct e1000_info e1000_pch2_info = {
5948	.mac = e1000_pch2lan,
5949	.flags = FLAG_IS_ICH
5950	| FLAG_HAS_WOL
5951	| FLAG_HAS_HW_TIMESTAMP
5952	| FLAG_HAS_CTRLEXT_ON_LOAD
5953	| FLAG_HAS_AMT
5954	| FLAG_HAS_FLASH
5955	| FLAG_HAS_JUMBO_FRAMES
5956	| FLAG_APME_IN_WUC,
5957	.flags2 = FLAG2_HAS_PHY_STATS
5958	| FLAG2_HAS_EEE
5959	| FLAG2_CHECK_SYSTIM_OVERFLOW,
5960	.pba = 26,
5961	.max_hw_frame_size = 9022,
5962	.get_variants = e1000_get_variants_ich8lan,
5963	.mac_ops = &ich8_mac_ops,
5964	.phy_ops = &ich8_phy_ops,
5965	.nvm_ops = &ich8_nvm_ops,
5966	};
5967
5968	const struct e1000_info e1000_pch_lpt_info = {
5969	.mac = e1000_pch_lpt,
5970	.flags = FLAG_IS_ICH
5971	| FLAG_HAS_WOL
5972	| FLAG_HAS_HW_TIMESTAMP
5973	| FLAG_HAS_CTRLEXT_ON_LOAD
5974	| FLAG_HAS_AMT
5975	| FLAG_HAS_FLASH
5976	| FLAG_HAS_JUMBO_FRAMES
5977	| FLAG_APME_IN_WUC,
5978	.flags2 = FLAG2_HAS_PHY_STATS
5979	| FLAG2_HAS_EEE
5980	| FLAG2_CHECK_SYSTIM_OVERFLOW,
5981	.pba = 26,
5982	.max_hw_frame_size = 9022,
5983	.get_variants = e1000_get_variants_ich8lan,
5984	.mac_ops = &ich8_mac_ops,
5985	.phy_ops = &ich8_phy_ops,
5986	.nvm_ops = &ich8_nvm_ops,
5987	};
5988
5989	const struct e1000_info e1000_pch_spt_info = {
5990	.mac = e1000_pch_spt,
5991	.flags = FLAG_IS_ICH
5992	| FLAG_HAS_WOL
5993	| FLAG_HAS_HW_TIMESTAMP
5994	| FLAG_HAS_CTRLEXT_ON_LOAD
5995	| FLAG_HAS_AMT
5996	| FLAG_HAS_FLASH
5997	| FLAG_HAS_JUMBO_FRAMES
5998	| FLAG_APME_IN_WUC,
5999	.flags2 = FLAG2_HAS_PHY_STATS
6000	| FLAG2_HAS_EEE,
6001	.pba = 26,
6002	.max_hw_frame_size = 9022,
6003	.get_variants = e1000_get_variants_ich8lan,
6004	.mac_ops = &ich8_mac_ops,
6005	.phy_ops = &ich8_phy_ops,
6006	.nvm_ops = &spt_nvm_ops,
6007	};
6008
6009	const struct e1000_info e1000_pch_cnp_info = {
6010	.mac = e1000_pch_cnp,
6011	.flags = FLAG_IS_ICH
6012	| FLAG_HAS_WOL
6013	| FLAG_HAS_HW_TIMESTAMP
6014	| FLAG_HAS_CTRLEXT_ON_LOAD
6015	| FLAG_HAS_AMT
6016	| FLAG_HAS_FLASH
6017	| FLAG_HAS_JUMBO_FRAMES
6018	| FLAG_APME_IN_WUC,
6019	.flags2 = FLAG2_HAS_PHY_STATS
6020	| FLAG2_HAS_EEE,
6021	.pba = 26,
6022	.max_hw_frame_size = 9022,
6023	.get_variants = e1000_get_variants_ich8lan,
6024	.mac_ops = &ich8_mac_ops,
6025	.phy_ops = &ich8_phy_ops,
6026	.nvm_ops = &spt_nvm_ops,
6027	};
6028
6029	const struct e1000_info e1000_pch_tgp_info = {
6030	.mac = e1000_pch_tgp,
6031	.flags = FLAG_IS_ICH
6032	| FLAG_HAS_WOL
6033	| FLAG_HAS_HW_TIMESTAMP
6034	| FLAG_HAS_CTRLEXT_ON_LOAD
6035	| FLAG_HAS_AMT
6036	| FLAG_HAS_FLASH
6037	| FLAG_HAS_JUMBO_FRAMES
6038	| FLAG_APME_IN_WUC,
6039	.flags2 = FLAG2_HAS_PHY_STATS
6040	| FLAG2_HAS_EEE,
6041	.pba = 26,
6042	.max_hw_frame_size = 9022,
6043	.get_variants = e1000_get_variants_ich8lan,
6044	.mac_ops = &ich8_mac_ops,
6045	.phy_ops = &ich8_phy_ops,
6046	.nvm_ops = &spt_nvm_ops,
6047	};
6048
6049	const struct e1000_info e1000_pch_adp_info = {
6050	.mac = e1000_pch_adp,
6051	.flags = FLAG_IS_ICH
6052	| FLAG_HAS_WOL
6053	| FLAG_HAS_HW_TIMESTAMP
6054	| FLAG_HAS_CTRLEXT_ON_LOAD
6055	| FLAG_HAS_AMT
6056	| FLAG_HAS_FLASH
6057	| FLAG_HAS_JUMBO_FRAMES
6058	| FLAG_APME_IN_WUC,
6059	.flags2 = FLAG2_HAS_PHY_STATS
6060	| FLAG2_HAS_EEE,
6061	.pba = 26,
6062	.max_hw_frame_size = 9022,
6063	.get_variants = e1000_get_variants_ich8lan,
6064	.mac_ops = &ich8_mac_ops,
6065	.phy_ops = &ich8_phy_ops,
6066	.nvm_ops = &spt_nvm_ops,
6067	};
6068
6069	const struct e1000_info e1000_pch_mtp_info = {
6070	.mac = e1000_pch_mtp,
6071	.flags = FLAG_IS_ICH
6072	| FLAG_HAS_WOL
6073	| FLAG_HAS_HW_TIMESTAMP
6074	| FLAG_HAS_CTRLEXT_ON_LOAD
6075	| FLAG_HAS_AMT
6076	| FLAG_HAS_FLASH
6077	| FLAG_HAS_JUMBO_FRAMES
6078	| FLAG_APME_IN_WUC,
6079	.flags2 = FLAG2_HAS_PHY_STATS
6080	| FLAG2_HAS_EEE,
6081	.pba = 26,
6082	.max_hw_frame_size = 9022,
6083	.get_variants = e1000_get_variants_ich8lan,
6084	.mac_ops = &ich8_mac_ops,
6085	.phy_ops = &ich8_phy_ops,
6086	.nvm_ops = &spt_nvm_ops,
6087	};
6088