1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4	#include <linux/bitfield.h>
5
6	#include "e1000.h"
7
8	/**
9	* e1000e_get_bus_info_pcie - Get PCIe bus information
10	* @hw: pointer to the HW structure
11	*
12	* Determines and stores the system bus information for a particular
13	* network interface. The following bus information is determined and stored:
14	* bus speed, bus width, type (PCIe), and PCIe function.
15	**/
16	s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
17	{
18	struct pci_dev *pdev = hw->adapter->pdev;
19	struct e1000_mac_info *mac = &hw->mac;
20	struct e1000_bus_info *bus = &hw->bus;
21	u16 pcie_link_status;
22
23	if (!pci_pcie_cap(dev: pdev)) {
24	bus->width = e1000_bus_width_unknown;
25	} else {
26	pcie_capability_read_word(dev: pdev, PCI_EXP_LNKSTA, val: &pcie_link_status);
27	bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,
28	pcie_link_status);
29	}
30
31	mac->ops.set_lan_id(hw);
32
33	return 0;
34	}
35
36	/**
37	* e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
38	*
39	* @hw: pointer to the HW structure
40	*
41	* Determines the LAN function id by reading memory-mapped registers
42	* and swaps the port value if requested.
43	**/
44	void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
45	{
46	struct e1000_bus_info *bus = &hw->bus;
47	u32 reg;
48
49	/* The status register reports the correct function number
50	* for the device regardless of function swap state.
51	*/
52	reg = er32(STATUS);
53	bus->func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg);
54	}
55
56	/**
57	* e1000_set_lan_id_single_port - Set LAN id for a single port device
58	* @hw: pointer to the HW structure
59	*
60	* Sets the LAN function id to zero for a single port device.
61	**/
62	void e1000_set_lan_id_single_port(struct e1000_hw *hw)
63	{
64	struct e1000_bus_info *bus = &hw->bus;
65
66	bus->func = 0;
67	}
68
69	/**
70	* e1000_clear_vfta_generic - Clear VLAN filter table
71	* @hw: pointer to the HW structure
72	*
73	* Clears the register array which contains the VLAN filter table by
74	* setting all the values to 0.
75	**/
76	void e1000_clear_vfta_generic(struct e1000_hw *hw)
77	{
78	u32 offset;
79
80	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
81	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
82	e1e_flush();
83	}
84	}
85
86	/**
87	* e1000_write_vfta_generic - Write value to VLAN filter table
88	* @hw: pointer to the HW structure
89	* @offset: register offset in VLAN filter table
90	* @value: register value written to VLAN filter table
91	*
92	* Writes value at the given offset in the register array which stores
93	* the VLAN filter table.
94	**/
95	void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
96	{
97	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
98	e1e_flush();
99	}
100
101	/**
102	* e1000e_init_rx_addrs - Initialize receive address's
103	* @hw: pointer to the HW structure
104	* @rar_count: receive address registers
105	*
106	* Setup the receive address registers by setting the base receive address
107	* register to the devices MAC address and clearing all the other receive
108	* address registers to 0.
109	**/
110	void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
111	{
112	u32 i;
113	u8 mac_addr[ETH_ALEN] = { 0 };
114
115	/* Setup the receive address */
116	e_dbg("Programming MAC Address into RAR[0]\n");
117
118	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
119
120	/* Zero out the other (rar_entry_count - 1) receive addresses */
121	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
122	for (i = 1; i < rar_count; i++)
123	hw->mac.ops.rar_set(hw, mac_addr, i);
124	}
125
126	/**
127	* e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
128	* @hw: pointer to the HW structure
129	*
130	* Checks the nvm for an alternate MAC address. An alternate MAC address
131	* can be setup by pre-boot software and must be treated like a permanent
132	* address and must override the actual permanent MAC address. If an
133	* alternate MAC address is found it is programmed into RAR0, replacing
134	* the permanent address that was installed into RAR0 by the Si on reset.
135	* This function will return SUCCESS unless it encounters an error while
136	* reading the EEPROM.
137	**/
138	s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
139	{
140	u32 i;
141	s32 ret_val;
142	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
143	u8 alt_mac_addr[ETH_ALEN];
144
145	ret_val = e1000_read_nvm(hw, NVM_COMPAT, words: 1, data: &nvm_data);
146	if (ret_val)
147	return ret_val;
148
149	/* not supported on 82573 */
150	if (hw->mac.type == e1000_82573)
151	return 0;
152
153	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, words: 1,
154	data: &nvm_alt_mac_addr_offset);
155	if (ret_val) {
156	e_dbg("NVM Read Error\n");
157	return ret_val;
158	}
159
160	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
161	(nvm_alt_mac_addr_offset == 0x0000))
162	/* There is no Alternate MAC Address */
163	return 0;
164
165	if (hw->bus.func == E1000_FUNC_1)
166	nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
167	for (i = 0; i < ETH_ALEN; i += 2) {
168	offset = nvm_alt_mac_addr_offset + (i >> 1);
169	ret_val = e1000_read_nvm(hw, offset, words: 1, data: &nvm_data);
170	if (ret_val) {
171	e_dbg("NVM Read Error\n");
172	return ret_val;
173	}
174
175	alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
176	alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
177	}
178
179	/* if multicast bit is set, the alternate address will not be used */
180	if (is_multicast_ether_addr(addr: alt_mac_addr)) {
181	e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
182	return 0;
183	}
184
185	/* We have a valid alternate MAC address, and we want to treat it the
186	* same as the normal permanent MAC address stored by the HW into the
187	* RAR. Do this by mapping this address into RAR0.
188	*/
189	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
190
191	return 0;
192	}
193
194	u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)
195	{
196	return hw->mac.rar_entry_count;
197	}
198
199	/**
200	* e1000e_rar_set_generic - Set receive address register
201	* @hw: pointer to the HW structure
202	* @addr: pointer to the receive address
203	* @index: receive address array register
204	*
205	* Sets the receive address array register at index to the address passed
206	* in by addr.
207	**/
208	int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
209	{
210	u32 rar_low, rar_high;
211
212	/* HW expects these in little endian so we reverse the byte order
213	* from network order (big endian) to little endian
214	*/
215	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
216	((u32)addr[2] << 16) | ((u32)addr[3] << 24));
217
218	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
219
220	/* If MAC address zero, no need to set the AV bit */
221	if (rar_low || rar_high)
222	rar_high |= E1000_RAH_AV;
223
224	/* Some bridges will combine consecutive 32-bit writes into
225	* a single burst write, which will malfunction on some parts.
226	* The flushes avoid this.
227	*/
228	ew32(RAL(index), rar_low);
229	e1e_flush();
230	ew32(RAH(index), rar_high);
231	e1e_flush();
232
233	return 0;
234	}
235
236	/**
237	* e1000_hash_mc_addr - Generate a multicast hash value
238	* @hw: pointer to the HW structure
239	* @mc_addr: pointer to a multicast address
240	*
241	* Generates a multicast address hash value which is used to determine
242	* the multicast filter table array address and new table value.
243	**/
244	static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
245	{
246	u32 hash_value, hash_mask;
247	u8 bit_shift = 0;
248
249	/* Register count multiplied by bits per register */
250	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
251
252	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
253	* where 0xFF would still fall within the hash mask.
254	*/
255	while (hash_mask >> bit_shift != 0xFF)
256	bit_shift++;
257
258	/* The portion of the address that is used for the hash table
259	* is determined by the mc_filter_type setting.
260	* The algorithm is such that there is a total of 8 bits of shifting.
261	* The bit_shift for a mc_filter_type of 0 represents the number of
262	* left-shifts where the MSB of mc_addr[5] would still fall within
263	* the hash_mask. Case 0 does this exactly. Since there are a total
264	* of 8 bits of shifting, then mc_addr[4] will shift right the
265	* remaining number of bits. Thus 8 - bit_shift. The rest of the
266	* cases are a variation of this algorithm...essentially raising the
267	* number of bits to shift mc_addr[5] left, while still keeping the
268	* 8-bit shifting total.
269	*
270	* For example, given the following Destination MAC Address and an
271	* mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
272	* we can see that the bit_shift for case 0 is 4. These are the hash
273	* values resulting from each mc_filter_type...
274	* [0] [1] [2] [3] [4] [5]
275	* 01 AA 00 12 34 56
276	* LSB MSB
277	*
278	* case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
279	* case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
280	* case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
281	* case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
282	*/
283	switch (hw->mac.mc_filter_type) {
284	default:
285	case 0:
286	break;
287	case 1:
288	bit_shift += 1;
289	break;
290	case 2:
291	bit_shift += 2;
292	break;
293	case 3:
294	bit_shift += 4;
295	break;
296	}
297
298	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
299	(((u16)mc_addr[5]) << bit_shift)));
300
301	return hash_value;
302	}
303
304	/**
305	* e1000e_update_mc_addr_list_generic - Update Multicast addresses
306	* @hw: pointer to the HW structure
307	* @mc_addr_list: array of multicast addresses to program
308	* @mc_addr_count: number of multicast addresses to program
309	*
310	* Updates entire Multicast Table Array.
311	* The caller must have a packed mc_addr_list of multicast addresses.
312	**/
313	void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
314	u8 *mc_addr_list, u32 mc_addr_count)
315	{
316	u32 hash_value, hash_bit, hash_reg;
317	int i;
318
319	/* clear mta_shadow */
320	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
321
322	/* update mta_shadow from mc_addr_list */
323	for (i = 0; (u32)i < mc_addr_count; i++) {
324	hash_value = e1000_hash_mc_addr(hw, mc_addr: mc_addr_list);
325
326	hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
327	hash_bit = hash_value & 0x1F;
328
329	hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
330	mc_addr_list += (ETH_ALEN);
331	}
332
333	/* replace the entire MTA table */
334	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
335	E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
336	e1e_flush();
337	}
338
339	/**
340	* e1000e_clear_hw_cntrs_base - Clear base hardware counters
341	* @hw: pointer to the HW structure
342	*
343	* Clears the base hardware counters by reading the counter registers.
344	**/
345	void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
346	{
347	er32(CRCERRS);
348	er32(SYMERRS);
349	er32(MPC);
350	er32(SCC);
351	er32(ECOL);
352	er32(MCC);
353	er32(LATECOL);
354	er32(COLC);
355	er32(DC);
356	er32(SEC);
357	er32(RLEC);
358	er32(XONRXC);
359	er32(XONTXC);
360	er32(XOFFRXC);
361	er32(XOFFTXC);
362	er32(FCRUC);
363	er32(GPRC);
364	er32(BPRC);
365	er32(MPRC);
366	er32(GPTC);
367	er32(GORCL);
368	er32(GORCH);
369	er32(GOTCL);
370	er32(GOTCH);
371	er32(RNBC);
372	er32(RUC);
373	er32(RFC);
374	er32(ROC);
375	er32(RJC);
376	er32(TORL);
377	er32(TORH);
378	er32(TOTL);
379	er32(TOTH);
380	er32(TPR);
381	er32(TPT);
382	er32(MPTC);
383	er32(BPTC);
384	}
385
386	/**
387	* e1000e_check_for_copper_link - Check for link (Copper)
388	* @hw: pointer to the HW structure
389	*
390	* Checks to see of the link status of the hardware has changed. If a
391	* change in link status has been detected, then we read the PHY registers
392	* to get the current speed/duplex if link exists.
393	**/
394	s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
395	{
396	struct e1000_mac_info *mac = &hw->mac;
397	s32 ret_val;
398	bool link;
399
400	/* We only want to go out to the PHY registers to see if Auto-Neg
401	* has completed and/or if our link status has changed. The
402	* get_link_status flag is set upon receiving a Link Status
403	* Change or Rx Sequence Error interrupt.
404	*/
405	if (!mac->get_link_status)
406	return 0;
407	mac->get_link_status = false;
408
409	/* First we want to see if the MII Status Register reports
410	* link. If so, then we want to get the current speed/duplex
411	* of the PHY.
412	*/
413	ret_val = e1000e_phy_has_link_generic(hw, iterations: 1, usec_interval: 0, success: &link);
414	if (ret_val || !link)
415	goto out;
416
417	/* Check if there was DownShift, must be checked
418	* immediately after link-up
419	*/
420	e1000e_check_downshift(hw);
421
422	/* If we are forcing speed/duplex, then we simply return since
423	* we have already determined whether we have link or not.
424	*/
425	if (!mac->autoneg)
426	return -E1000_ERR_CONFIG;
427
428	/* Auto-Neg is enabled. Auto Speed Detection takes care
429	* of MAC speed/duplex configuration. So we only need to
430	* configure Collision Distance in the MAC.
431	*/
432	mac->ops.config_collision_dist(hw);
433
434	/* Configure Flow Control now that Auto-Neg has completed.
435	* First, we need to restore the desired flow control
436	* settings because we may have had to re-autoneg with a
437	* different link partner.
438	*/
439	ret_val = e1000e_config_fc_after_link_up(hw);
440	if (ret_val)
441	e_dbg("Error configuring flow control\n");
442
443	return ret_val;
444
445	out:
446	mac->get_link_status = true;
447	return ret_val;
448	}
449
450	/**
451	* e1000e_check_for_fiber_link - Check for link (Fiber)
452	* @hw: pointer to the HW structure
453	*
454	* Checks for link up on the hardware. If link is not up and we have
455	* a signal, then we need to force link up.
456	**/
457	s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
458	{
459	struct e1000_mac_info *mac = &hw->mac;
460	u32 rxcw;
461	u32 ctrl;
462	u32 status;
463	s32 ret_val;
464
465	ctrl = er32(CTRL);
466	status = er32(STATUS);
467	rxcw = er32(RXCW);
468
469	/* If we don't have link (auto-negotiation failed or link partner
470	* cannot auto-negotiate), the cable is plugged in (we have signal),
471	* and our link partner is not trying to auto-negotiate with us (we
472	* are receiving idles or data), we need to force link up. We also
473	* need to give auto-negotiation time to complete, in case the cable
474	* was just plugged in. The autoneg_failed flag does this.
475	*/
476	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
477	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
478	!(rxcw & E1000_RXCW_C)) {
479	if (!mac->autoneg_failed) {
480	mac->autoneg_failed = true;
481	return 0;
482	}
483	e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
484
485	/* Disable auto-negotiation in the TXCW register */
486	ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
487
488	/* Force link-up and also force full-duplex. */
489	ctrl = er32(CTRL);
490	ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
491	ew32(CTRL, ctrl);
492
493	/* Configure Flow Control after forcing link up. */
494	ret_val = e1000e_config_fc_after_link_up(hw);
495	if (ret_val) {
496	e_dbg("Error configuring flow control\n");
497	return ret_val;
498	}
499	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
500	/* If we are forcing link and we are receiving /C/ ordered
501	* sets, re-enable auto-negotiation in the TXCW register
502	* and disable forced link in the Device Control register
503	* in an attempt to auto-negotiate with our link partner.
504	*/
505	e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
506	ew32(TXCW, mac->txcw);
507	ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
508
509	mac->serdes_has_link = true;
510	}
511
512	return 0;
513	}
514
515	/**
516	* e1000e_check_for_serdes_link - Check for link (Serdes)
517	* @hw: pointer to the HW structure
518	*
519	* Checks for link up on the hardware. If link is not up and we have
520	* a signal, then we need to force link up.
521	**/
522	s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
523	{
524	struct e1000_mac_info *mac = &hw->mac;
525	u32 rxcw;
526	u32 ctrl;
527	u32 status;
528	s32 ret_val;
529
530	ctrl = er32(CTRL);
531	status = er32(STATUS);
532	rxcw = er32(RXCW);
533
534	/* If we don't have link (auto-negotiation failed or link partner
535	* cannot auto-negotiate), and our link partner is not trying to
536	* auto-negotiate with us (we are receiving idles or data),
537	* we need to force link up. We also need to give auto-negotiation
538	* time to complete.
539	*/
540	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
541	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
542	if (!mac->autoneg_failed) {
543	mac->autoneg_failed = true;
544	return 0;
545	}
546	e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
547
548	/* Disable auto-negotiation in the TXCW register */
549	ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
550
551	/* Force link-up and also force full-duplex. */
552	ctrl = er32(CTRL);
553	ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
554	ew32(CTRL, ctrl);
555
556	/* Configure Flow Control after forcing link up. */
557	ret_val = e1000e_config_fc_after_link_up(hw);
558	if (ret_val) {
559	e_dbg("Error configuring flow control\n");
560	return ret_val;
561	}
562	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
563	/* If we are forcing link and we are receiving /C/ ordered
564	* sets, re-enable auto-negotiation in the TXCW register
565	* and disable forced link in the Device Control register
566	* in an attempt to auto-negotiate with our link partner.
567	*/
568	e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
569	ew32(TXCW, mac->txcw);
570	ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
571
572	mac->serdes_has_link = true;
573	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
574	/* If we force link for non-auto-negotiation switch, check
575	* link status based on MAC synchronization for internal
576	* serdes media type.
577	*/
578	/* SYNCH bit and IV bit are sticky. */
579	usleep_range(min: 10, max: 20);
580	rxcw = er32(RXCW);
581	if (rxcw & E1000_RXCW_SYNCH) {
582	if (!(rxcw & E1000_RXCW_IV)) {
583	mac->serdes_has_link = true;
584	e_dbg("SERDES: Link up - forced.\n");
585	}
586	} else {
587	mac->serdes_has_link = false;
588	e_dbg("SERDES: Link down - force failed.\n");
589	}
590	}
591
592	if (E1000_TXCW_ANE & er32(TXCW)) {
593	status = er32(STATUS);
594	if (status & E1000_STATUS_LU) {
595	/* SYNCH bit and IV bit are sticky, so reread rxcw. */
596	usleep_range(min: 10, max: 20);
597	rxcw = er32(RXCW);
598	if (rxcw & E1000_RXCW_SYNCH) {
599	if (!(rxcw & E1000_RXCW_IV)) {
600	mac->serdes_has_link = true;
601	e_dbg("SERDES: Link up - autoneg completed successfully.\n");
602	} else {
603	mac->serdes_has_link = false;
604	e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
605	}
606	} else {
607	mac->serdes_has_link = false;
608	e_dbg("SERDES: Link down - no sync.\n");
609	}
610	} else {
611	mac->serdes_has_link = false;
612	e_dbg("SERDES: Link down - autoneg failed\n");
613	}
614	}
615
616	return 0;
617	}
618
619	/**
620	* e1000_set_default_fc_generic - Set flow control default values
621	* @hw: pointer to the HW structure
622	*
623	* Read the EEPROM for the default values for flow control and store the
624	* values.
625	**/
626	static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
627	{
628	s32 ret_val;
629	u16 nvm_data;
630
631	/* Read and store word 0x0F of the EEPROM. This word contains bits
632	* that determine the hardware's default PAUSE (flow control) mode,
633	* a bit that determines whether the HW defaults to enabling or
634	* disabling auto-negotiation, and the direction of the
635	* SW defined pins. If there is no SW over-ride of the flow
636	* control setting, then the variable hw->fc will
637	* be initialized based on a value in the EEPROM.
638	*/
639	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, words: 1, data: &nvm_data);
640
641	if (ret_val) {
642	e_dbg("NVM Read Error\n");
643	return ret_val;
644	}
645
646	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
647	hw->fc.requested_mode = e1000_fc_none;
648	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
649	hw->fc.requested_mode = e1000_fc_tx_pause;
650	else
651	hw->fc.requested_mode = e1000_fc_full;
652
653	return 0;
654	}
655
656	/**
657	* e1000e_setup_link_generic - Setup flow control and link settings
658	* @hw: pointer to the HW structure
659	*
660	* Determines which flow control settings to use, then configures flow
661	* control. Calls the appropriate media-specific link configuration
662	* function. Assuming the adapter has a valid link partner, a valid link
663	* should be established. Assumes the hardware has previously been reset
664	* and the transmitter and receiver are not enabled.
665	**/
666	s32 e1000e_setup_link_generic(struct e1000_hw *hw)
667	{
668	s32 ret_val;
669
670	/* In the case of the phy reset being blocked, we already have a link.
671	* We do not need to set it up again.
672	*/
673	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
674	return 0;
675
676	/* If requested flow control is set to default, set flow control
677	* based on the EEPROM flow control settings.
678	*/
679	if (hw->fc.requested_mode == e1000_fc_default) {
680	ret_val = e1000_set_default_fc_generic(hw);
681	if (ret_val)
682	return ret_val;
683	}
684
685	/* Save off the requested flow control mode for use later. Depending
686	* on the link partner's capabilities, we may or may not use this mode.
687	*/
688	hw->fc.current_mode = hw->fc.requested_mode;
689
690	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
691
692	/* Call the necessary media_type subroutine to configure the link. */
693	ret_val = hw->mac.ops.setup_physical_interface(hw);
694	if (ret_val)
695	return ret_val;
696
697	/* Initialize the flow control address, type, and PAUSE timer
698	* registers to their default values. This is done even if flow
699	* control is disabled, because it does not hurt anything to
700	* initialize these registers.
701	*/
702	e_dbg("Initializing the Flow Control address, type and timer regs\n");
703	ew32(FCT, FLOW_CONTROL_TYPE);
704	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
705	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
706
707	ew32(FCTTV, hw->fc.pause_time);
708
709	return e1000e_set_fc_watermarks(hw);
710	}
711
712	/**
713	* e1000_commit_fc_settings_generic - Configure flow control
714	* @hw: pointer to the HW structure
715	*
716	* Write the flow control settings to the Transmit Config Word Register (TXCW)
717	* base on the flow control settings in e1000_mac_info.
718	**/
719	static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
720	{
721	struct e1000_mac_info *mac = &hw->mac;
722	u32 txcw;
723
724	/* Check for a software override of the flow control settings, and
725	* setup the device accordingly. If auto-negotiation is enabled, then
726	* software will have to set the "PAUSE" bits to the correct value in
727	* the Transmit Config Word Register (TXCW) and re-start auto-
728	* negotiation. However, if auto-negotiation is disabled, then
729	* software will have to manually configure the two flow control enable
730	* bits in the CTRL register.
731	*
732	* The possible values of the "fc" parameter are:
733	* 0: Flow control is completely disabled
734	* 1: Rx flow control is enabled (we can receive pause frames,
735	* but not send pause frames).
736	* 2: Tx flow control is enabled (we can send pause frames but we
737	* do not support receiving pause frames).
738	* 3: Both Rx and Tx flow control (symmetric) are enabled.
739	*/
740	switch (hw->fc.current_mode) {
741	case e1000_fc_none:
742	/* Flow control completely disabled by a software over-ride. */
743	txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
744	break;
745	case e1000_fc_rx_pause:
746	/* Rx Flow control is enabled and Tx Flow control is disabled
747	* by a software over-ride. Since there really isn't a way to
748	* advertise that we are capable of Rx Pause ONLY, we will
749	* advertise that we support both symmetric and asymmetric Rx
750	* PAUSE. Later, we will disable the adapter's ability to send
751	* PAUSE frames.
752	*/
753	txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
754	break;
755	case e1000_fc_tx_pause:
756	/* Tx Flow control is enabled, and Rx Flow control is disabled,
757	* by a software over-ride.
758	*/
759	txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
760	break;
761	case e1000_fc_full:
762	/* Flow control (both Rx and Tx) is enabled by a software
763	* over-ride.
764	*/
765	txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
766	break;
767	default:
768	e_dbg("Flow control param set incorrectly\n");
769	return -E1000_ERR_CONFIG;
770	}
771
772	ew32(TXCW, txcw);
773	mac->txcw = txcw;
774
775	return 0;
776	}
777
778	/**
779	* e1000_poll_fiber_serdes_link_generic - Poll for link up
780	* @hw: pointer to the HW structure
781	*
782	* Polls for link up by reading the status register, if link fails to come
783	* up with auto-negotiation, then the link is forced if a signal is detected.
784	**/
785	static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
786	{
787	struct e1000_mac_info *mac = &hw->mac;
788	u32 i, status;
789	s32 ret_val;
790
791	/* If we have a signal (the cable is plugged in, or assumed true for
792	* serdes media) then poll for a "Link-Up" indication in the Device
793	* Status Register. Time-out if a link isn't seen in 500 milliseconds
794	* seconds (Auto-negotiation should complete in less than 500
795	* milliseconds even if the other end is doing it in SW).
796	*/
797	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
798	usleep_range(min: 10000, max: 11000);
799	status = er32(STATUS);
800	if (status & E1000_STATUS_LU)
801	break;
802	}
803	if (i == FIBER_LINK_UP_LIMIT) {
804	e_dbg("Never got a valid link from auto-neg!!!\n");
805	mac->autoneg_failed = true;
806	/* AutoNeg failed to achieve a link, so we'll call
807	* mac->check_for_link. This routine will force the
808	* link up if we detect a signal. This will allow us to
809	* communicate with non-autonegotiating link partners.
810	*/
811	ret_val = mac->ops.check_for_link(hw);
812	if (ret_val) {
813	e_dbg("Error while checking for link\n");
814	return ret_val;
815	}
816	mac->autoneg_failed = false;
817	} else {
818	mac->autoneg_failed = false;
819	e_dbg("Valid Link Found\n");
820	}
821
822	return 0;
823	}
824
825	/**
826	* e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
827	* @hw: pointer to the HW structure
828	*
829	* Configures collision distance and flow control for fiber and serdes
830	* links. Upon successful setup, poll for link.
831	**/
832	s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
833	{
834	u32 ctrl;
835	s32 ret_val;
836
837	ctrl = er32(CTRL);
838
839	/* Take the link out of reset */
840	ctrl &= ~E1000_CTRL_LRST;
841
842	hw->mac.ops.config_collision_dist(hw);
843
844	ret_val = e1000_commit_fc_settings_generic(hw);
845	if (ret_val)
846	return ret_val;
847
848	/* Since auto-negotiation is enabled, take the link out of reset (the
849	* link will be in reset, because we previously reset the chip). This
850	* will restart auto-negotiation. If auto-negotiation is successful
851	* then the link-up status bit will be set and the flow control enable
852	* bits (RFCE and TFCE) will be set according to their negotiated value.
853	*/
854	e_dbg("Auto-negotiation enabled\n");
855
856	ew32(CTRL, ctrl);
857	e1e_flush();
858	usleep_range(min: 1000, max: 2000);
859
860	/* For these adapters, the SW definable pin 1 is set when the optics
861	* detect a signal. If we have a signal, then poll for a "Link-Up"
862	* indication.
863	*/
864	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
865	(er32(CTRL) & E1000_CTRL_SWDPIN1)) {
866	ret_val = e1000_poll_fiber_serdes_link_generic(hw);
867	} else {
868	e_dbg("No signal detected\n");
869	}
870
871	return ret_val;
872	}
873
874	/**
875	* e1000e_config_collision_dist_generic - Configure collision distance
876	* @hw: pointer to the HW structure
877	*
878	* Configures the collision distance to the default value and is used
879	* during link setup.
880	**/
881	void e1000e_config_collision_dist_generic(struct e1000_hw *hw)
882	{
883	u32 tctl;
884
885	tctl = er32(TCTL);
886
887	tctl &= ~E1000_TCTL_COLD;
888	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
889
890	ew32(TCTL, tctl);
891	e1e_flush();
892	}
893
894	/**
895	* e1000e_set_fc_watermarks - Set flow control high/low watermarks
896	* @hw: pointer to the HW structure
897	*
898	* Sets the flow control high/low threshold (watermark) registers. If
899	* flow control XON frame transmission is enabled, then set XON frame
900	* transmission as well.
901	**/
902	s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
903	{
904	u32 fcrtl = 0, fcrth = 0;
905
906	/* Set the flow control receive threshold registers. Normally,
907	* these registers will be set to a default threshold that may be
908	* adjusted later by the driver's runtime code. However, if the
909	* ability to transmit pause frames is not enabled, then these
910	* registers will be set to 0.
911	*/
912	if (hw->fc.current_mode & e1000_fc_tx_pause) {
913	/* We need to set up the Receive Threshold high and low water
914	* marks as well as (optionally) enabling the transmission of
915	* XON frames.
916	*/
917	fcrtl = hw->fc.low_water;
918	if (hw->fc.send_xon)
919	fcrtl |= E1000_FCRTL_XONE;
920
921	fcrth = hw->fc.high_water;
922	}
923	ew32(FCRTL, fcrtl);
924	ew32(FCRTH, fcrth);
925
926	return 0;
927	}
928
929	/**
930	* e1000e_force_mac_fc - Force the MAC's flow control settings
931	* @hw: pointer to the HW structure
932	*
933	* Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
934	* device control register to reflect the adapter settings. TFCE and RFCE
935	* need to be explicitly set by software when a copper PHY is used because
936	* autonegotiation is managed by the PHY rather than the MAC. Software must
937	* also configure these bits when link is forced on a fiber connection.
938	**/
939	s32 e1000e_force_mac_fc(struct e1000_hw *hw)
940	{
941	u32 ctrl;
942
943	ctrl = er32(CTRL);
944
945	/* Because we didn't get link via the internal auto-negotiation
946	* mechanism (we either forced link or we got link via PHY
947	* auto-neg), we have to manually enable/disable transmit an
948	* receive flow control.
949	*
950	* The "Case" statement below enables/disable flow control
951	* according to the "hw->fc.current_mode" parameter.
952	*
953	* The possible values of the "fc" parameter are:
954	* 0: Flow control is completely disabled
955	* 1: Rx flow control is enabled (we can receive pause
956	* frames but not send pause frames).
957	* 2: Tx flow control is enabled (we can send pause frames
958	* but we do not receive pause frames).
959	* 3: Both Rx and Tx flow control (symmetric) is enabled.
960	* other: No other values should be possible at this point.
961	*/
962	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
963
964	switch (hw->fc.current_mode) {
965	case e1000_fc_none:
966	ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
967	break;
968	case e1000_fc_rx_pause:
969	ctrl &= (~E1000_CTRL_TFCE);
970	ctrl |= E1000_CTRL_RFCE;
971	break;
972	case e1000_fc_tx_pause:
973	ctrl &= (~E1000_CTRL_RFCE);
974	ctrl |= E1000_CTRL_TFCE;
975	break;
976	case e1000_fc_full:
977	ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
978	break;
979	default:
980	e_dbg("Flow control param set incorrectly\n");
981	return -E1000_ERR_CONFIG;
982	}
983
984	ew32(CTRL, ctrl);
985
986	return 0;
987	}
988
989	/**
990	* e1000e_config_fc_after_link_up - Configures flow control after link
991	* @hw: pointer to the HW structure
992	*
993	* Checks the status of auto-negotiation after link up to ensure that the
994	* speed and duplex were not forced. If the link needed to be forced, then
995	* flow control needs to be forced also. If auto-negotiation is enabled
996	* and did not fail, then we configure flow control based on our link
997	* partner.
998	**/
999	s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1000	{
1001	struct e1000_mac_info *mac = &hw->mac;
1002	s32 ret_val = 0;
1003	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1004	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1005	u16 speed, duplex;
1006
1007	/* Check for the case where we have fiber media and auto-neg failed
1008	* so we had to force link. In this case, we need to force the
1009	* configuration of the MAC to match the "fc" parameter.
1010	*/
1011	if (mac->autoneg_failed) {
1012	if (hw->phy.media_type == e1000_media_type_fiber ||
1013	hw->phy.media_type == e1000_media_type_internal_serdes)
1014	ret_val = e1000e_force_mac_fc(hw);
1015	} else {
1016	if (hw->phy.media_type == e1000_media_type_copper)
1017	ret_val = e1000e_force_mac_fc(hw);
1018	}
1019
1020	if (ret_val) {
1021	e_dbg("Error forcing flow control settings\n");
1022	return ret_val;
1023	}
1024
1025	/* Check for the case where we have copper media and auto-neg is
1026	* enabled. In this case, we need to check and see if Auto-Neg
1027	* has completed, and if so, how the PHY and link partner has
1028	* flow control configured.
1029	*/
1030	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1031	/* Read the MII Status Register and check to see if AutoNeg
1032	* has completed. We read this twice because this reg has
1033	* some "sticky" (latched) bits.
1034	*/
1035	ret_val = e1e_rphy(hw, MII_BMSR, data: &mii_status_reg);
1036	if (ret_val)
1037	return ret_val;
1038	ret_val = e1e_rphy(hw, MII_BMSR, data: &mii_status_reg);
1039	if (ret_val)
1040	return ret_val;
1041
1042	if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) {
1043	e_dbg("Copper PHY and Auto Neg has not completed.\n");
1044	return ret_val;
1045	}
1046
1047	/* The AutoNeg process has completed, so we now need to
1048	* read both the Auto Negotiation Advertisement
1049	* Register (Address 4) and the Auto_Negotiation Base
1050	* Page Ability Register (Address 5) to determine how
1051	* flow control was negotiated.
1052	*/
1053	ret_val = e1e_rphy(hw, MII_ADVERTISE, data: &mii_nway_adv_reg);
1054	if (ret_val)
1055	return ret_val;
1056	ret_val = e1e_rphy(hw, MII_LPA, data: &mii_nway_lp_ability_reg);
1057	if (ret_val)
1058	return ret_val;
1059
1060	/* Two bits in the Auto Negotiation Advertisement Register
1061	* (Address 4) and two bits in the Auto Negotiation Base
1062	* Page Ability Register (Address 5) determine flow control
1063	* for both the PHY and the link partner. The following
1064	* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1065	* 1999, describes these PAUSE resolution bits and how flow
1066	* control is determined based upon these settings.
1067	* NOTE: DC = Don't Care
1068	*
1069	* LOCAL DEVICE | LINK PARTNER
1070	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1071	*-------|---------|-------|---------|--------------------
1072	* 0 | 0 | DC | DC | e1000_fc_none
1073	* 0 | 1 | 0 | DC | e1000_fc_none
1074	* 0 | 1 | 1 | 0 | e1000_fc_none
1075	* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1076	* 1 | 0 | 0 | DC | e1000_fc_none
1077	* 1 | DC | 1 | DC | e1000_fc_full
1078	* 1 | 1 | 0 | 0 | e1000_fc_none
1079	* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1080	*
1081	* Are both PAUSE bits set to 1? If so, this implies
1082	* Symmetric Flow Control is enabled at both ends. The
1083	* ASM_DIR bits are irrelevant per the spec.
1084	*
1085	* For Symmetric Flow Control:
1086	*
1087	* LOCAL DEVICE | LINK PARTNER
1088	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1089	*-------|---------|-------|---------|--------------------
1090	* 1 | DC | 1 | DC | E1000_fc_full
1091	*
1092	*/
1093	if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1094	(mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) {
1095	/* Now we need to check if the user selected Rx ONLY
1096	* of pause frames. In this case, we had to advertise
1097	* FULL flow control because we could not advertise Rx
1098	* ONLY. Hence, we must now check to see if we need to
1099	* turn OFF the TRANSMISSION of PAUSE frames.
1100	*/
1101	if (hw->fc.requested_mode == e1000_fc_full) {
1102	hw->fc.current_mode = e1000_fc_full;
1103	e_dbg("Flow Control = FULL.\n");
1104	} else {
1105	hw->fc.current_mode = e1000_fc_rx_pause;
1106	e_dbg("Flow Control = Rx PAUSE frames only.\n");
1107	}
1108	}
1109	/* For receiving PAUSE frames ONLY.
1110	*
1111	* LOCAL DEVICE | LINK PARTNER
1112	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1113	*-------|---------|-------|---------|--------------------
1114	* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1115	*/
1116	else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1117	(mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1118	(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1119	(mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1120	hw->fc.current_mode = e1000_fc_tx_pause;
1121	e_dbg("Flow Control = Tx PAUSE frames only.\n");
1122	}
1123	/* For transmitting PAUSE frames ONLY.
1124	*
1125	* LOCAL DEVICE | LINK PARTNER
1126	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1127	*-------|---------|-------|---------|--------------------
1128	* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1129	*/
1130	else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1131	(mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1132	!(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1133	(mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1134	hw->fc.current_mode = e1000_fc_rx_pause;
1135	e_dbg("Flow Control = Rx PAUSE frames only.\n");
1136	} else {
1137	/* Per the IEEE spec, at this point flow control
1138	* should be disabled.
1139	*/
1140	hw->fc.current_mode = e1000_fc_none;
1141	e_dbg("Flow Control = NONE.\n");
1142	}
1143
1144	/* Now we need to do one last check... If we auto-
1145	* negotiated to HALF DUPLEX, flow control should not be
1146	* enabled per IEEE 802.3 spec.
1147	*/
1148	ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1149	if (ret_val) {
1150	e_dbg("Error getting link speed and duplex\n");
1151	return ret_val;
1152	}
1153
1154	if (duplex == HALF_DUPLEX)
1155	hw->fc.current_mode = e1000_fc_none;
1156
1157	/* Now we call a subroutine to actually force the MAC
1158	* controller to use the correct flow control settings.
1159	*/
1160	ret_val = e1000e_force_mac_fc(hw);
1161	if (ret_val) {
1162	e_dbg("Error forcing flow control settings\n");
1163	return ret_val;
1164	}
1165	}
1166
1167	/* Check for the case where we have SerDes media and auto-neg is
1168	* enabled. In this case, we need to check and see if Auto-Neg
1169	* has completed, and if so, how the PHY and link partner has
1170	* flow control configured.
1171	*/
1172	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1173	mac->autoneg) {
1174	/* Read the PCS_LSTS and check to see if AutoNeg
1175	* has completed.
1176	*/
1177	pcs_status_reg = er32(PCS_LSTAT);
1178
1179	if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1180	e_dbg("PCS Auto Neg has not completed.\n");
1181	return ret_val;
1182	}
1183
1184	/* The AutoNeg process has completed, so we now need to
1185	* read both the Auto Negotiation Advertisement
1186	* Register (PCS_ANADV) and the Auto_Negotiation Base
1187	* Page Ability Register (PCS_LPAB) to determine how
1188	* flow control was negotiated.
1189	*/
1190	pcs_adv_reg = er32(PCS_ANADV);
1191	pcs_lp_ability_reg = er32(PCS_LPAB);
1192
1193	/* Two bits in the Auto Negotiation Advertisement Register
1194	* (PCS_ANADV) and two bits in the Auto Negotiation Base
1195	* Page Ability Register (PCS_LPAB) determine flow control
1196	* for both the PHY and the link partner. The following
1197	* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1198	* 1999, describes these PAUSE resolution bits and how flow
1199	* control is determined based upon these settings.
1200	* NOTE: DC = Don't Care
1201	*
1202	* LOCAL DEVICE | LINK PARTNER
1203	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1204	*-------|---------|-------|---------|--------------------
1205	* 0 | 0 | DC | DC | e1000_fc_none
1206	* 0 | 1 | 0 | DC | e1000_fc_none
1207	* 0 | 1 | 1 | 0 | e1000_fc_none
1208	* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1209	* 1 | 0 | 0 | DC | e1000_fc_none
1210	* 1 | DC | 1 | DC | e1000_fc_full
1211	* 1 | 1 | 0 | 0 | e1000_fc_none
1212	* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1213	*
1214	* Are both PAUSE bits set to 1? If so, this implies
1215	* Symmetric Flow Control is enabled at both ends. The
1216	* ASM_DIR bits are irrelevant per the spec.
1217	*
1218	* For Symmetric Flow Control:
1219	*
1220	* LOCAL DEVICE | LINK PARTNER
1221	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1222	*-------|---------|-------|---------|--------------------
1223	* 1 | DC | 1 | DC | e1000_fc_full
1224	*
1225	*/
1226	if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1227	(pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1228	/* Now we need to check if the user selected Rx ONLY
1229	* of pause frames. In this case, we had to advertise
1230	* FULL flow control because we could not advertise Rx
1231	* ONLY. Hence, we must now check to see if we need to
1232	* turn OFF the TRANSMISSION of PAUSE frames.
1233	*/
1234	if (hw->fc.requested_mode == e1000_fc_full) {
1235	hw->fc.current_mode = e1000_fc_full;
1236	e_dbg("Flow Control = FULL.\n");
1237	} else {
1238	hw->fc.current_mode = e1000_fc_rx_pause;
1239	e_dbg("Flow Control = Rx PAUSE frames only.\n");
1240	}
1241	}
1242	/* For receiving PAUSE frames ONLY.
1243	*
1244	* LOCAL DEVICE | LINK PARTNER
1245	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1246	*-------|---------|-------|---------|--------------------
1247	* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1248	*/
1249	else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1250	(pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1251	(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1252	(pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1253	hw->fc.current_mode = e1000_fc_tx_pause;
1254	e_dbg("Flow Control = Tx PAUSE frames only.\n");
1255	}
1256	/* For transmitting PAUSE frames ONLY.
1257	*
1258	* LOCAL DEVICE | LINK PARTNER
1259	* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1260	*-------|---------|-------|---------|--------------------
1261	* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1262	*/
1263	else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1264	(pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1265	!(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1266	(pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1267	hw->fc.current_mode = e1000_fc_rx_pause;
1268	e_dbg("Flow Control = Rx PAUSE frames only.\n");
1269	} else {
1270	/* Per the IEEE spec, at this point flow control
1271	* should be disabled.
1272	*/
1273	hw->fc.current_mode = e1000_fc_none;
1274	e_dbg("Flow Control = NONE.\n");
1275	}
1276
1277	/* Now we call a subroutine to actually force the MAC
1278	* controller to use the correct flow control settings.
1279	*/
1280	pcs_ctrl_reg = er32(PCS_LCTL);
1281	pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1282	ew32(PCS_LCTL, pcs_ctrl_reg);
1283
1284	ret_val = e1000e_force_mac_fc(hw);
1285	if (ret_val) {
1286	e_dbg("Error forcing flow control settings\n");
1287	return ret_val;
1288	}
1289	}
1290
1291	return 0;
1292	}
1293
1294	/**
1295	* e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1296	* @hw: pointer to the HW structure
1297	* @speed: stores the current speed
1298	* @duplex: stores the current duplex
1299	*
1300	* Read the status register for the current speed/duplex and store the current
1301	* speed and duplex for copper connections.
1302	**/
1303	s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1304	u16 *duplex)
1305	{
1306	u32 status;
1307
1308	status = er32(STATUS);
1309	if (status & E1000_STATUS_SPEED_1000)
1310	*speed = SPEED_1000;
1311	else if (status & E1000_STATUS_SPEED_100)
1312	*speed = SPEED_100;
1313	else
1314	*speed = SPEED_10;
1315
1316	if (status & E1000_STATUS_FD)
1317	*duplex = FULL_DUPLEX;
1318	else
1319	*duplex = HALF_DUPLEX;
1320
1321	e_dbg("%u Mbps, %s Duplex\n",
1322	*speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1323	*duplex == FULL_DUPLEX ? "Full" : "Half");
1324
1325	return 0;
1326	}
1327
1328	/**
1329	* e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1330	* @hw: pointer to the HW structure
1331	* @speed: stores the current speed
1332	* @duplex: stores the current duplex
1333	*
1334	* Sets the speed and duplex to gigabit full duplex (the only possible option)
1335	* for fiber/serdes links.
1336	**/
1337	s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused
1338	*hw, u16 *speed, u16 *duplex)
1339	{
1340	*speed = SPEED_1000;
1341	*duplex = FULL_DUPLEX;
1342
1343	return 0;
1344	}
1345
1346	/**
1347	* e1000e_get_hw_semaphore - Acquire hardware semaphore
1348	* @hw: pointer to the HW structure
1349	*
1350	* Acquire the HW semaphore to access the PHY or NVM
1351	**/
1352	s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1353	{
1354	u32 swsm;
1355	s32 timeout = hw->nvm.word_size + 1;
1356	s32 i = 0;
1357
1358	/* Get the SW semaphore */
1359	while (i < timeout) {
1360	swsm = er32(SWSM);
1361	if (!(swsm & E1000_SWSM_SMBI))
1362	break;
1363
1364	udelay(100);
1365	i++;
1366	}
1367
1368	if (i == timeout) {
1369	e_dbg("Driver can't access device - SMBI bit is set.\n");
1370	return -E1000_ERR_NVM;
1371	}
1372
1373	/* Get the FW semaphore. */
1374	for (i = 0; i < timeout; i++) {
1375	swsm = er32(SWSM);
1376	ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1377
1378	/* Semaphore acquired if bit latched */
1379	if (er32(SWSM) & E1000_SWSM_SWESMBI)
1380	break;
1381
1382	udelay(100);
1383	}
1384
1385	if (i == timeout) {
1386	/* Release semaphores */
1387	e1000e_put_hw_semaphore(hw);
1388	e_dbg("Driver can't access the NVM\n");
1389	return -E1000_ERR_NVM;
1390	}
1391
1392	return 0;
1393	}
1394
1395	/**
1396	* e1000e_put_hw_semaphore - Release hardware semaphore
1397	* @hw: pointer to the HW structure
1398	*
1399	* Release hardware semaphore used to access the PHY or NVM
1400	**/
1401	void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1402	{
1403	u32 swsm;
1404
1405	swsm = er32(SWSM);
1406	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1407	ew32(SWSM, swsm);
1408	}
1409
1410	/**
1411	* e1000e_get_auto_rd_done - Check for auto read completion
1412	* @hw: pointer to the HW structure
1413	*
1414	* Check EEPROM for Auto Read done bit.
1415	**/
1416	s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1417	{
1418	s32 i = 0;
1419
1420	while (i < AUTO_READ_DONE_TIMEOUT) {
1421	if (er32(EECD) & E1000_EECD_AUTO_RD)
1422	break;
1423	usleep_range(min: 1000, max: 2000);
1424	i++;
1425	}
1426
1427	if (i == AUTO_READ_DONE_TIMEOUT) {
1428	e_dbg("Auto read by HW from NVM has not completed.\n");
1429	return -E1000_ERR_RESET;
1430	}
1431
1432	return 0;
1433	}
1434
1435	/**
1436	* e1000e_valid_led_default - Verify a valid default LED config
1437	* @hw: pointer to the HW structure
1438	* @data: pointer to the NVM (EEPROM)
1439	*
1440	* Read the EEPROM for the current default LED configuration. If the
1441	* LED configuration is not valid, set to a valid LED configuration.
1442	**/
1443	s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1444	{
1445	s32 ret_val;
1446
1447	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, words: 1, data);
1448	if (ret_val) {
1449	e_dbg("NVM Read Error\n");
1450	return ret_val;
1451	}
1452
1453	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1454	*data = ID_LED_DEFAULT;
1455
1456	return 0;
1457	}
1458
1459	/**
1460	* e1000e_id_led_init_generic -
1461	* @hw: pointer to the HW structure
1462	*
1463	**/
1464	s32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1465	{
1466	struct e1000_mac_info *mac = &hw->mac;
1467	s32 ret_val;
1468	const u32 ledctl_mask = 0x000000FF;
1469	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1470	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1471	u16 data, i, temp;
1472	const u16 led_mask = 0x0F;
1473
1474	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1475	if (ret_val)
1476	return ret_val;
1477
1478	mac->ledctl_default = er32(LEDCTL);
1479	mac->ledctl_mode1 = mac->ledctl_default;
1480	mac->ledctl_mode2 = mac->ledctl_default;
1481
1482	for (i = 0; i < 4; i++) {
1483	temp = (data >> (i << 2)) & led_mask;
1484	switch (temp) {
1485	case ID_LED_ON1_DEF2:
1486	case ID_LED_ON1_ON2:
1487	case ID_LED_ON1_OFF2:
1488	mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1489	mac->ledctl_mode1 |= ledctl_on << (i << 3);
1490	break;
1491	case ID_LED_OFF1_DEF2:
1492	case ID_LED_OFF1_ON2:
1493	case ID_LED_OFF1_OFF2:
1494	mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1495	mac->ledctl_mode1 |= ledctl_off << (i << 3);
1496	break;
1497	default:
1498	/* Do nothing */
1499	break;
1500	}
1501	switch (temp) {
1502	case ID_LED_DEF1_ON2:
1503	case ID_LED_ON1_ON2:
1504	case ID_LED_OFF1_ON2:
1505	mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1506	mac->ledctl_mode2 |= ledctl_on << (i << 3);
1507	break;
1508	case ID_LED_DEF1_OFF2:
1509	case ID_LED_ON1_OFF2:
1510	case ID_LED_OFF1_OFF2:
1511	mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1512	mac->ledctl_mode2 |= ledctl_off << (i << 3);
1513	break;
1514	default:
1515	/* Do nothing */
1516	break;
1517	}
1518	}
1519
1520	return 0;
1521	}
1522
1523	/**
1524	* e1000e_setup_led_generic - Configures SW controllable LED
1525	* @hw: pointer to the HW structure
1526	*
1527	* This prepares the SW controllable LED for use and saves the current state
1528	* of the LED so it can be later restored.
1529	**/
1530	s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1531	{
1532	u32 ledctl;
1533
1534	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1535	return -E1000_ERR_CONFIG;
1536
1537	if (hw->phy.media_type == e1000_media_type_fiber) {
1538	ledctl = er32(LEDCTL);
1539	hw->mac.ledctl_default = ledctl;
1540	/* Turn off LED0 */
1541	ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1542	E1000_LEDCTL_LED0_MODE_MASK);
1543	ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1544	E1000_LEDCTL_LED0_MODE_SHIFT);
1545	ew32(LEDCTL, ledctl);
1546	} else if (hw->phy.media_type == e1000_media_type_copper) {
1547	ew32(LEDCTL, hw->mac.ledctl_mode1);
1548	}
1549
1550	return 0;
1551	}
1552
1553	/**
1554	* e1000e_cleanup_led_generic - Set LED config to default operation
1555	* @hw: pointer to the HW structure
1556	*
1557	* Remove the current LED configuration and set the LED configuration
1558	* to the default value, saved from the EEPROM.
1559	**/
1560	s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1561	{
1562	ew32(LEDCTL, hw->mac.ledctl_default);
1563	return 0;
1564	}
1565
1566	/**
1567	* e1000e_blink_led_generic - Blink LED
1568	* @hw: pointer to the HW structure
1569	*
1570	* Blink the LEDs which are set to be on.
1571	**/
1572	s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1573	{
1574	u32 ledctl_blink = 0;
1575	u32 i;
1576
1577	if (hw->phy.media_type == e1000_media_type_fiber) {
1578	/* always blink LED0 for PCI-E fiber */
1579	ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1580	(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1581	} else {
1582	/* Set the blink bit for each LED that's "on" (0x0E)
1583	* (or "off" if inverted) in ledctl_mode2. The blink
1584	* logic in hardware only works when mode is set to "on"
1585	* so it must be changed accordingly when the mode is
1586	* "off" and inverted.
1587	*/
1588	ledctl_blink = hw->mac.ledctl_mode2;
1589	for (i = 0; i < 32; i += 8) {
1590	u32 mode = (hw->mac.ledctl_mode2 >> i) &
1591	E1000_LEDCTL_LED0_MODE_MASK;
1592	u32 led_default = hw->mac.ledctl_default >> i;
1593
1594	if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1595	(mode == E1000_LEDCTL_MODE_LED_ON)) ||
1596	((led_default & E1000_LEDCTL_LED0_IVRT) &&
1597	(mode == E1000_LEDCTL_MODE_LED_OFF))) {
1598	ledctl_blink &=
1599	~(E1000_LEDCTL_LED0_MODE_MASK << i);
1600	ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1601	E1000_LEDCTL_MODE_LED_ON) << i;
1602	}
1603	}
1604	}
1605
1606	ew32(LEDCTL, ledctl_blink);
1607
1608	return 0;
1609	}
1610
1611	/**
1612	* e1000e_led_on_generic - Turn LED on
1613	* @hw: pointer to the HW structure
1614	*
1615	* Turn LED on.
1616	**/
1617	s32 e1000e_led_on_generic(struct e1000_hw *hw)
1618	{
1619	u32 ctrl;
1620
1621	switch (hw->phy.media_type) {
1622	case e1000_media_type_fiber:
1623	ctrl = er32(CTRL);
1624	ctrl &= ~E1000_CTRL_SWDPIN0;
1625	ctrl |= E1000_CTRL_SWDPIO0;
1626	ew32(CTRL, ctrl);
1627	break;
1628	case e1000_media_type_copper:
1629	ew32(LEDCTL, hw->mac.ledctl_mode2);
1630	break;
1631	default:
1632	break;
1633	}
1634
1635	return 0;
1636	}
1637
1638	/**
1639	* e1000e_led_off_generic - Turn LED off
1640	* @hw: pointer to the HW structure
1641	*
1642	* Turn LED off.
1643	**/
1644	s32 e1000e_led_off_generic(struct e1000_hw *hw)
1645	{
1646	u32 ctrl;
1647
1648	switch (hw->phy.media_type) {
1649	case e1000_media_type_fiber:
1650	ctrl = er32(CTRL);
1651	ctrl |= E1000_CTRL_SWDPIN0;
1652	ctrl |= E1000_CTRL_SWDPIO0;
1653	ew32(CTRL, ctrl);
1654	break;
1655	case e1000_media_type_copper:
1656	ew32(LEDCTL, hw->mac.ledctl_mode1);
1657	break;
1658	default:
1659	break;
1660	}
1661
1662	return 0;
1663	}
1664
1665	/**
1666	* e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1667	* @hw: pointer to the HW structure
1668	* @no_snoop: bitmap of snoop events
1669	*
1670	* Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1671	**/
1672	void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1673	{
1674	u32 gcr;
1675
1676	if (no_snoop) {
1677	gcr = er32(GCR);
1678	gcr &= ~(PCIE_NO_SNOOP_ALL);
1679	gcr |= no_snoop;
1680	ew32(GCR, gcr);
1681	}
1682	}
1683
1684	/**
1685	* e1000e_disable_pcie_master - Disables PCI-express master access
1686	* @hw: pointer to the HW structure
1687	*
1688	* Returns 0 if successful, else returns -10
1689	* (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1690	* the master requests to be disabled.
1691	*
1692	* Disables PCI-Express master access and verifies there are no pending
1693	* requests.
1694	**/
1695	s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1696	{
1697	u32 ctrl;
1698	s32 timeout = MASTER_DISABLE_TIMEOUT;
1699
1700	ctrl = er32(CTRL);
1701	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1702	ew32(CTRL, ctrl);
1703
1704	while (timeout) {
1705	if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1706	break;
1707	usleep_range(min: 100, max: 200);
1708	timeout--;
1709	}
1710
1711	if (!timeout) {
1712	e_dbg("Master requests are pending.\n");
1713	return -E1000_ERR_MASTER_REQUESTS_PENDING;
1714	}
1715
1716	return 0;
1717	}
1718
1719	/**
1720	* e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1721	* @hw: pointer to the HW structure
1722	*
1723	* Reset the Adaptive Interframe Spacing throttle to default values.
1724	**/
1725	void e1000e_reset_adaptive(struct e1000_hw *hw)
1726	{
1727	struct e1000_mac_info *mac = &hw->mac;
1728
1729	if (!mac->adaptive_ifs) {
1730	e_dbg("Not in Adaptive IFS mode!\n");
1731	return;
1732	}
1733
1734	mac->current_ifs_val = 0;
1735	mac->ifs_min_val = IFS_MIN;
1736	mac->ifs_max_val = IFS_MAX;
1737	mac->ifs_step_size = IFS_STEP;
1738	mac->ifs_ratio = IFS_RATIO;
1739
1740	mac->in_ifs_mode = false;
1741	ew32(AIT, 0);
1742	}
1743
1744	/**
1745	* e1000e_update_adaptive - Update Adaptive Interframe Spacing
1746	* @hw: pointer to the HW structure
1747	*
1748	* Update the Adaptive Interframe Spacing Throttle value based on the
1749	* time between transmitted packets and time between collisions.
1750	**/
1751	void e1000e_update_adaptive(struct e1000_hw *hw)
1752	{
1753	struct e1000_mac_info *mac = &hw->mac;
1754
1755	if (!mac->adaptive_ifs) {
1756	e_dbg("Not in Adaptive IFS mode!\n");
1757	return;
1758	}
1759
1760	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1761	if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1762	mac->in_ifs_mode = true;
1763	if (mac->current_ifs_val < mac->ifs_max_val) {
1764	if (!mac->current_ifs_val)
1765	mac->current_ifs_val = mac->ifs_min_val;
1766	else
1767	mac->current_ifs_val +=
1768	mac->ifs_step_size;
1769	ew32(AIT, mac->current_ifs_val);
1770	}
1771	}
1772	} else {
1773	if (mac->in_ifs_mode &&
1774	(mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1775	mac->current_ifs_val = 0;
1776	mac->in_ifs_mode = false;
1777	ew32(AIT, 0);
1778	}
1779	}
1780	}
1781