| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Marvell RVU Ethernet driver |
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| 3 | * |
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| 4 | * Copyright (C) 2020 Marvell. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef OTX2_REG_H |
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| 9 | #define OTX2_REG_H |
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| 10 | |
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| 11 | #include <rvu_struct.h> |
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| 12 | |
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| 13 | /* RVU PF registers */ |
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| 14 | #define RVU_PF_VFX_PFVF_MBOX0 (0x00000) |
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| 15 | #define RVU_PF_VFX_PFVF_MBOX1 (0x00008) |
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| 16 | #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) |
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| 17 | #define RVU_PF_VF_BAR4_ADDR (0x10) |
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| 18 | #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) |
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| 19 | #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) |
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| 20 | #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) |
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| 21 | #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) |
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| 22 | #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) |
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| 23 | #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) |
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| 24 | #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) |
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| 25 | #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) |
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| 26 | #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) |
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| 27 | #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) |
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| 28 | #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) |
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| 29 | #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) |
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| 30 | #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) |
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| 31 | #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) |
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| 32 | #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) |
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| 33 | #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) |
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| 34 | #define RVU_PF_PFAF_MBOX0 (0xC00) |
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| 35 | #define RVU_PF_PFAF_MBOX1 (0xC08) |
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| 36 | #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) |
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| 37 | #define RVU_PF_INT (0xc20) |
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| 38 | #define RVU_PF_INT_W1S (0xc28) |
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| 39 | #define RVU_PF_INT_ENA_W1S (0xc30) |
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| 40 | #define RVU_PF_INT_ENA_W1C (0xc38) |
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| 41 | #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) |
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| 42 | #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) |
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| 43 | #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) |
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| 44 | #define RVU_PF_VF_MBOX_ADDR (0xC40) |
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| 45 | #define RVU_PF_LMTLINE_ADDR (0xC48) |
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| 46 | |
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| 47 | /* RVU VF registers */ |
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| 48 | #define RVU_VF_VFPF_MBOX0 (0x00000) |
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| 49 | #define RVU_VF_VFPF_MBOX1 (0x00008) |
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| 50 | #define RVU_VF_VFPF_MBOXX(a) (0x00 | (a) << 3) |
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| 51 | #define RVU_VF_INT (0x20) |
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| 52 | #define RVU_VF_INT_W1S (0x28) |
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| 53 | #define RVU_VF_INT_ENA_W1S (0x30) |
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| 54 | #define RVU_VF_INT_ENA_W1C (0x38) |
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| 55 | #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) |
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| 56 | #define RVU_VF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) |
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| 57 | #define RVU_VF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) |
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| 58 | #define RVU_VF_MSIX_PBAX(a) (0xF0000 | (a) << 3) |
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| 59 | #define RVU_VF_MBOX_REGION (0xC0000) |
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| 60 | |
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| 61 | #define RVU_FUNC_BLKADDR_SHIFT 20 |
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| 62 | #define RVU_FUNC_BLKADDR_MASK 0x1FULL |
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| 63 | |
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| 64 | /* NPA LF registers */ |
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| 65 | #define NPA_LFBASE (BLKTYPE_NPA << RVU_FUNC_BLKADDR_SHIFT) |
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| 66 | #define NPA_LF_AURA_OP_ALLOCX(a) (NPA_LFBASE | 0x10 | (a) << 3) |
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| 67 | #define NPA_LF_AURA_OP_FREE0 (NPA_LFBASE | 0x20) |
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| 68 | #define NPA_LF_AURA_OP_FREE1 (NPA_LFBASE | 0x28) |
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| 69 | #define NPA_LF_AURA_OP_CNT (NPA_LFBASE | 0x30) |
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| 70 | #define NPA_LF_AURA_OP_LIMIT (NPA_LFBASE | 0x50) |
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| 71 | #define NPA_LF_AURA_OP_INT (NPA_LFBASE | 0x60) |
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| 72 | #define NPA_LF_AURA_OP_THRESH (NPA_LFBASE | 0x70) |
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| 73 | #define NPA_LF_POOL_OP_PC (NPA_LFBASE | 0x100) |
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| 74 | #define NPA_LF_POOL_OP_AVAILABLE (NPA_LFBASE | 0x110) |
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| 75 | #define NPA_LF_POOL_OP_PTR_START0 (NPA_LFBASE | 0x120) |
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| 76 | #define NPA_LF_POOL_OP_PTR_START1 (NPA_LFBASE | 0x128) |
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| 77 | #define NPA_LF_POOL_OP_PTR_END0 (NPA_LFBASE | 0x130) |
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| 78 | #define NPA_LF_POOL_OP_PTR_END1 (NPA_LFBASE | 0x138) |
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| 79 | #define NPA_LF_POOL_OP_INT (NPA_LFBASE | 0x160) |
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| 80 | #define NPA_LF_POOL_OP_THRESH (NPA_LFBASE | 0x170) |
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| 81 | #define NPA_LF_ERR_INT (NPA_LFBASE | 0x200) |
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| 82 | #define NPA_LF_ERR_INT_W1S (NPA_LFBASE | 0x208) |
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| 83 | #define NPA_LF_ERR_INT_ENA_W1C (NPA_LFBASE | 0x210) |
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| 84 | #define NPA_LF_ERR_INT_ENA_W1S (NPA_LFBASE | 0x218) |
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| 85 | #define NPA_LF_RAS (NPA_LFBASE | 0x220) |
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| 86 | #define NPA_LF_RAS_W1S (NPA_LFBASE | 0x228) |
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| 87 | #define NPA_LF_RAS_ENA_W1C (NPA_LFBASE | 0x230) |
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| 88 | #define NPA_LF_RAS_ENA_W1S (NPA_LFBASE | 0x238) |
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| 89 | #define NPA_LF_QINTX_CNT(a) (NPA_LFBASE | 0x300 | (a) << 12) |
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| 90 | #define NPA_LF_QINTX_INT(a) (NPA_LFBASE | 0x310 | (a) << 12) |
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| 91 | #define NPA_LF_QINTX_INT_W1S(a) (NPA_LFBASE | 0x318 | (a) << 12) |
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| 92 | #define NPA_LF_QINTX_ENA_W1S(a) (NPA_LFBASE | 0x320 | (a) << 12) |
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| 93 | #define NPA_LF_QINTX_ENA_W1C(a) (NPA_LFBASE | 0x330 | (a) << 12) |
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| 94 | #define NPA_LF_AURA_BATCH_FREE0 (NPA_LFBASE | 0x400) |
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| 95 | |
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| 96 | /* NIX LF registers */ |
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| 97 | #define NIX_LFBASE (BLKTYPE_NIX << RVU_FUNC_BLKADDR_SHIFT) |
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| 98 | #define NIX_LF_RX_SECRETX(a) (NIX_LFBASE | 0x0 | (a) << 3) |
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| 99 | #define NIX_LF_CFG (NIX_LFBASE | 0x100) |
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| 100 | #define NIX_LF_GINT (NIX_LFBASE | 0x200) |
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| 101 | #define NIX_LF_GINT_W1S (NIX_LFBASE | 0x208) |
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| 102 | #define NIX_LF_GINT_ENA_W1C (NIX_LFBASE | 0x210) |
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| 103 | #define NIX_LF_GINT_ENA_W1S (NIX_LFBASE | 0x218) |
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| 104 | #define NIX_LF_ERR_INT (NIX_LFBASE | 0x220) |
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| 105 | #define NIX_LF_ERR_INT_W1S (NIX_LFBASE | 0x228) |
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| 106 | #define NIX_LF_ERR_INT_ENA_W1C (NIX_LFBASE | 0x230) |
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| 107 | #define NIX_LF_ERR_INT_ENA_W1S (NIX_LFBASE | 0x238) |
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| 108 | #define NIX_LF_RAS (NIX_LFBASE | 0x240) |
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| 109 | #define NIX_LF_RAS_W1S (NIX_LFBASE | 0x248) |
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| 110 | #define NIX_LF_RAS_ENA_W1C (NIX_LFBASE | 0x250) |
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| 111 | #define NIX_LF_RAS_ENA_W1S (NIX_LFBASE | 0x258) |
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| 112 | #define NIX_LF_SQ_OP_ERR_DBG (NIX_LFBASE | 0x260) |
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| 113 | #define NIX_LF_MNQ_ERR_DBG (NIX_LFBASE | 0x270) |
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| 114 | #define NIX_LF_SEND_ERR_DBG (NIX_LFBASE | 0x280) |
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| 115 | #define NIX_LF_TX_STATX(a) (NIX_LFBASE | 0x300 | (a) << 3) |
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| 116 | #define NIX_LF_RX_STATX(a) (NIX_LFBASE | 0x400 | (a) << 3) |
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| 117 | #define NIX_LF_OP_SENDX(a) (NIX_LFBASE | 0x800 | (a) << 3) |
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| 118 | #define NIX_LF_RQ_OP_INT (NIX_LFBASE | 0x900) |
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| 119 | #define NIX_LF_RQ_OP_OCTS (NIX_LFBASE | 0x910) |
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| 120 | #define NIX_LF_RQ_OP_PKTS (NIX_LFBASE | 0x920) |
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| 121 | #define NIX_LF_OP_IPSEC_DYNO_CN (NIX_LFBASE | 0x980) |
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| 122 | #define NIX_LF_SQ_OP_INT (NIX_LFBASE | 0xa00) |
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| 123 | #define NIX_LF_SQ_OP_OCTS (NIX_LFBASE | 0xa10) |
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| 124 | #define NIX_LF_SQ_OP_PKTS (NIX_LFBASE | 0xa20) |
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| 125 | #define NIX_LF_SQ_OP_STATUS (NIX_LFBASE | 0xa30) |
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| 126 | #define NIX_LF_CQ_OP_INT (NIX_LFBASE | 0xb00) |
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| 127 | #define NIX_LF_CQ_OP_DOOR (NIX_LFBASE | 0xb30) |
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| 128 | #define NIX_LF_CQ_OP_STATUS (NIX_LFBASE | 0xb40) |
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| 129 | #define NIX_LF_QINTX_CNT(a) (NIX_LFBASE | 0xC00 | (a) << 12) |
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| 130 | #define NIX_LF_QINTX_INT(a) (NIX_LFBASE | 0xC10 | (a) << 12) |
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| 131 | #define NIX_LF_QINTX_INT_W1S(a) (NIX_LFBASE | 0xC18 | (a) << 12) |
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| 132 | #define NIX_LF_QINTX_ENA_W1S(a) (NIX_LFBASE | 0xC20 | (a) << 12) |
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| 133 | #define NIX_LF_QINTX_ENA_W1C(a) (NIX_LFBASE | 0xC30 | (a) << 12) |
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| 134 | #define NIX_LF_CINTX_CNT(a) (NIX_LFBASE | 0xD00 | (a) << 12) |
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| 135 | #define NIX_LF_CINTX_WAIT(a) (NIX_LFBASE | 0xD10 | (a) << 12) |
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| 136 | #define NIX_LF_CINTX_INT(a) (NIX_LFBASE | 0xD20 | (a) << 12) |
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| 137 | #define NIX_LF_CINTX_INT_W1S(a) (NIX_LFBASE | 0xD30 | (a) << 12) |
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| 138 | #define NIX_LF_CINTX_ENA_W1S(a) (NIX_LFBASE | 0xD40 | (a) << 12) |
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| 139 | #define NIX_LF_CINTX_ENA_W1C(a) (NIX_LFBASE | 0xD50 | (a) << 12) |
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| 140 | |
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| 141 | /* NIX AF transmit scheduler registers */ |
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| 142 | #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) |
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| 143 | #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) |
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| 144 | #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) |
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| 145 | #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) |
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| 146 | #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) |
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| 147 | #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) |
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| 148 | #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16) |
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| 149 | #define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16) |
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| 150 | #define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16) |
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| 151 | #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) |
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| 152 | #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) |
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| 153 | #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16) |
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| 154 | #define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16) |
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| 155 | #define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16) |
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| 156 | #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16) |
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| 157 | #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) |
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| 158 | #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) |
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| 159 | #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16) |
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| 160 | #define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16) |
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| 161 | #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) |
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| 162 | #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16) |
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| 163 | #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) |
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| 164 | #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16) |
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| 165 | #define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16) |
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| 166 | #define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16) |
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| 167 | #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) |
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| 168 | #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) |
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| 169 | |
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| 170 | /* LMT LF registers */ |
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| 171 | #define LMT_LFBASE BIT_ULL(RVU_FUNC_BLKADDR_SHIFT) |
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| 172 | #define LMT_LF_LMTLINEX(a) (LMT_LFBASE | 0x000 | (a) << 12) |
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| 173 | #define LMT_LF_LMTCANCEL (LMT_LFBASE | 0x400) |
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| 174 | |
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| 175 | #endif /* OTX2_REG_H */ |
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| 176 | |
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