1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
2 | /* QLogic qed NIC Driver |
3 | * Copyright (c) 2019-2021 Marvell International Ltd. |
4 | */ |
5 | #ifndef _QED_DBG_HSI_H |
6 | #define _QED_DBG_HSI_H |
7 | |
8 | #include <linux/types.h> |
9 | #include <linux/io.h> |
10 | #include <linux/bitops.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/list.h> |
14 | #include <linux/slab.h> |
15 | |
16 | /****************************************/ |
17 | /* Debug Tools HSI constants and macros */ |
18 | /****************************************/ |
19 | |
20 | enum block_id { |
21 | BLOCK_GRC, |
22 | BLOCK_MISCS, |
23 | BLOCK_MISC, |
24 | BLOCK_DBU, |
25 | BLOCK_PGLUE_B, |
26 | BLOCK_CNIG, |
27 | BLOCK_CPMU, |
28 | BLOCK_NCSI, |
29 | BLOCK_OPTE, |
30 | BLOCK_BMB, |
31 | BLOCK_PCIE, |
32 | BLOCK_MCP, |
33 | BLOCK_MCP2, |
34 | BLOCK_PSWHST, |
35 | BLOCK_PSWHST2, |
36 | BLOCK_PSWRD, |
37 | BLOCK_PSWRD2, |
38 | BLOCK_PSWWR, |
39 | BLOCK_PSWWR2, |
40 | BLOCK_PSWRQ, |
41 | BLOCK_PSWRQ2, |
42 | BLOCK_PGLCS, |
43 | BLOCK_DMAE, |
44 | BLOCK_PTU, |
45 | BLOCK_TCM, |
46 | BLOCK_MCM, |
47 | BLOCK_UCM, |
48 | BLOCK_XCM, |
49 | BLOCK_YCM, |
50 | BLOCK_PCM, |
51 | BLOCK_QM, |
52 | BLOCK_TM, |
53 | BLOCK_DORQ, |
54 | BLOCK_BRB, |
55 | BLOCK_SRC, |
56 | BLOCK_PRS, |
57 | BLOCK_TSDM, |
58 | BLOCK_MSDM, |
59 | BLOCK_USDM, |
60 | BLOCK_XSDM, |
61 | BLOCK_YSDM, |
62 | BLOCK_PSDM, |
63 | BLOCK_TSEM, |
64 | BLOCK_MSEM, |
65 | BLOCK_USEM, |
66 | BLOCK_XSEM, |
67 | BLOCK_YSEM, |
68 | BLOCK_PSEM, |
69 | , |
70 | BLOCK_TMLD, |
71 | BLOCK_MULD, |
72 | BLOCK_YULD, |
73 | BLOCK_XYLD, |
74 | BLOCK_PRM, |
75 | BLOCK_PBF_PB1, |
76 | BLOCK_PBF_PB2, |
77 | BLOCK_RPB, |
78 | BLOCK_BTB, |
79 | BLOCK_PBF, |
80 | BLOCK_RDIF, |
81 | BLOCK_TDIF, |
82 | BLOCK_CDU, |
83 | BLOCK_CCFC, |
84 | BLOCK_TCFC, |
85 | BLOCK_IGU, |
86 | BLOCK_CAU, |
87 | BLOCK_UMAC, |
88 | BLOCK_XMAC, |
89 | BLOCK_MSTAT, |
90 | BLOCK_DBG, |
91 | BLOCK_NIG, |
92 | BLOCK_WOL, |
93 | BLOCK_BMBN, |
94 | BLOCK_IPC, |
95 | BLOCK_NWM, |
96 | BLOCK_NWS, |
97 | BLOCK_MS, |
98 | BLOCK_PHY_PCIE, |
99 | BLOCK_LED, |
100 | BLOCK_AVS_WRAP, |
101 | BLOCK_PXPREQBUS, |
102 | BLOCK_BAR0_MAP, |
103 | BLOCK_MCP_FIO, |
104 | BLOCK_LAST_INIT, |
105 | BLOCK_PRS_FC, |
106 | BLOCK_PBF_FC, |
107 | BLOCK_NIG_LB_FC, |
108 | BLOCK_NIG_LB_FC_PLLH, |
109 | BLOCK_NIG_TX_FC_PLLH, |
110 | BLOCK_NIG_TX_FC, |
111 | BLOCK_NIG_RX_FC_PLLH, |
112 | BLOCK_NIG_RX_FC, |
113 | MAX_BLOCK_ID |
114 | }; |
115 | |
116 | /* binary debug buffer types */ |
117 | enum bin_dbg_buffer_type { |
118 | BIN_BUF_DBG_MODE_TREE, |
119 | BIN_BUF_DBG_DUMP_REG, |
120 | BIN_BUF_DBG_DUMP_MEM, |
121 | BIN_BUF_DBG_IDLE_CHK_REGS, |
122 | BIN_BUF_DBG_IDLE_CHK_IMMS, |
123 | BIN_BUF_DBG_IDLE_CHK_RULES, |
124 | BIN_BUF_DBG_IDLE_CHK_PARSING_DATA, |
125 | BIN_BUF_DBG_ATTN_BLOCKS, |
126 | BIN_BUF_DBG_ATTN_REGS, |
127 | BIN_BUF_DBG_ATTN_INDEXES, |
128 | BIN_BUF_DBG_ATTN_NAME_OFFSETS, |
129 | BIN_BUF_DBG_BLOCKS, |
130 | BIN_BUF_DBG_BLOCKS_CHIP_DATA, |
131 | BIN_BUF_DBG_BUS_LINES, |
132 | BIN_BUF_DBG_BLOCKS_USER_DATA, |
133 | BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA, |
134 | BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS, |
135 | BIN_BUF_DBG_RESET_REGS, |
136 | BIN_BUF_DBG_PARSING_STRINGS, |
137 | MAX_BIN_DBG_BUFFER_TYPE |
138 | }; |
139 | |
140 | /* Attention bit mapping */ |
141 | struct dbg_attn_bit_mapping { |
142 | u16 data; |
143 | #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF |
144 | #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 |
145 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 |
146 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 |
147 | }; |
148 | |
149 | /* Attention block per-type data */ |
150 | struct dbg_attn_block_type_data { |
151 | u16 names_offset; |
152 | u16 reserved1; |
153 | u8 num_regs; |
154 | u8 reserved2; |
155 | u16 regs_offset; |
156 | |
157 | }; |
158 | |
159 | /* Block attentions */ |
160 | struct dbg_attn_block { |
161 | struct dbg_attn_block_type_data per_type_data[2]; |
162 | }; |
163 | |
164 | /* Attention register result */ |
165 | struct dbg_attn_reg_result { |
166 | u32 data; |
167 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF |
168 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 |
169 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF |
170 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 |
171 | u16 block_attn_offset; |
172 | u16 reserved; |
173 | u32 sts_val; |
174 | u32 mask_val; |
175 | }; |
176 | |
177 | /* Attention block result */ |
178 | struct dbg_attn_block_result { |
179 | u8 block_id; |
180 | u8 data; |
181 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 |
182 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 |
183 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F |
184 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 |
185 | u16 names_offset; |
186 | struct dbg_attn_reg_result reg_results[15]; |
187 | }; |
188 | |
189 | /* Mode header */ |
190 | struct dbg_mode_hdr { |
191 | u16 data; |
192 | #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 |
193 | #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 |
194 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF |
195 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 |
196 | }; |
197 | |
198 | /* Attention register */ |
199 | struct dbg_attn_reg { |
200 | struct dbg_mode_hdr mode; |
201 | u16 block_attn_offset; |
202 | u32 data; |
203 | #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF |
204 | #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 |
205 | #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF |
206 | #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 |
207 | u32 sts_clr_address; |
208 | u32 mask_address; |
209 | }; |
210 | |
211 | /* Attention types */ |
212 | enum dbg_attn_type { |
213 | ATTN_TYPE_INTERRUPT, |
214 | ATTN_TYPE_PARITY, |
215 | MAX_DBG_ATTN_TYPE |
216 | }; |
217 | |
218 | /* Block debug data */ |
219 | struct dbg_block { |
220 | u8 name[15]; |
221 | u8 associated_storm_letter; |
222 | }; |
223 | |
224 | /* Chip-specific block debug data */ |
225 | struct dbg_block_chip { |
226 | u8 flags; |
227 | #define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1 |
228 | #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0 |
229 | #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1 |
230 | #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1 |
231 | #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1 |
232 | #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2 |
233 | #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1 |
234 | #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3 |
235 | #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1 |
236 | #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4 |
237 | #define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7 |
238 | #define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5 |
239 | u8 dbg_client_id; |
240 | u8 reset_reg_id; |
241 | u8 reset_reg_bit_offset; |
242 | struct dbg_mode_hdr dbg_bus_mode; |
243 | u16 reserved1; |
244 | u8 reserved2; |
245 | u8 num_of_dbg_bus_lines; |
246 | u16 dbg_bus_lines_offset; |
247 | u32 dbg_select_reg_addr; |
248 | u32 dbg_dword_enable_reg_addr; |
249 | u32 dbg_shift_reg_addr; |
250 | u32 dbg_force_valid_reg_addr; |
251 | u32 dbg_force_frame_reg_addr; |
252 | }; |
253 | |
254 | /* Chip-specific block user debug data */ |
255 | struct dbg_block_chip_user { |
256 | u8 num_of_dbg_bus_lines; |
257 | u8 has_latency_events; |
258 | u16 names_offset; |
259 | }; |
260 | |
261 | /* Block user debug data */ |
262 | struct dbg_block_user { |
263 | u8 name[16]; |
264 | }; |
265 | |
266 | /* Block Debug line data */ |
267 | struct dbg_bus_line { |
268 | u8 data; |
269 | #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF |
270 | #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 |
271 | #define DBG_BUS_LINE_IS_256B_MASK 0x1 |
272 | #define DBG_BUS_LINE_IS_256B_SHIFT 4 |
273 | #define DBG_BUS_LINE_RESERVED_MASK 0x7 |
274 | #define DBG_BUS_LINE_RESERVED_SHIFT 5 |
275 | u8 group_sizes; |
276 | }; |
277 | |
278 | /* Condition header for registers dump */ |
279 | struct dbg_dump_cond_hdr { |
280 | struct dbg_mode_hdr mode; /* Mode header */ |
281 | u8 block_id; /* block ID */ |
282 | u8 data_size; /* size in dwords of the data following this header */ |
283 | }; |
284 | |
285 | /* Memory data for registers dump */ |
286 | struct dbg_dump_mem { |
287 | u32 dword0; |
288 | #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF |
289 | #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 |
290 | #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF |
291 | #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 |
292 | u32 dword1; |
293 | #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF |
294 | #define DBG_DUMP_MEM_LENGTH_SHIFT 0 |
295 | #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 |
296 | #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 |
297 | #define DBG_DUMP_MEM_RESERVED_MASK 0x7F |
298 | #define DBG_DUMP_MEM_RESERVED_SHIFT 25 |
299 | }; |
300 | |
301 | /* Register data for registers dump */ |
302 | struct dbg_dump_reg { |
303 | u32 data; |
304 | #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF |
305 | #define DBG_DUMP_REG_ADDRESS_SHIFT 0 |
306 | #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 |
307 | #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 |
308 | #define DBG_DUMP_REG_LENGTH_MASK 0xFF |
309 | #define DBG_DUMP_REG_LENGTH_SHIFT 24 |
310 | }; |
311 | |
312 | /* Split header for registers dump */ |
313 | struct dbg_dump_split_hdr { |
314 | u32 hdr; |
315 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF |
316 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 |
317 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF |
318 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 |
319 | }; |
320 | |
321 | /* Condition header for idle check */ |
322 | struct dbg_idle_chk_cond_hdr { |
323 | struct dbg_mode_hdr mode; /* Mode header */ |
324 | u16 data_size; /* size in dwords of the data following this header */ |
325 | }; |
326 | |
327 | /* Idle Check condition register */ |
328 | struct dbg_idle_chk_cond_reg { |
329 | u32 data; |
330 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF |
331 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 |
332 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 |
333 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 |
334 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF |
335 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 |
336 | u16 num_entries; |
337 | u8 entry_size; |
338 | u8 start_entry; |
339 | }; |
340 | |
341 | /* Idle Check info register */ |
342 | struct dbg_idle_chk_info_reg { |
343 | u32 data; |
344 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF |
345 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 |
346 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 |
347 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 |
348 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF |
349 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 |
350 | u16 size; /* register size in dwords */ |
351 | struct dbg_mode_hdr mode; /* Mode header */ |
352 | }; |
353 | |
354 | /* Idle Check register */ |
355 | union dbg_idle_chk_reg { |
356 | struct dbg_idle_chk_cond_reg cond_reg; /* condition register */ |
357 | struct dbg_idle_chk_info_reg info_reg; /* info register */ |
358 | }; |
359 | |
360 | /* Idle Check result header */ |
361 | struct dbg_idle_chk_result_hdr { |
362 | u16 rule_id; /* Failing rule index */ |
363 | u16 mem_entry_id; /* Failing memory entry index */ |
364 | u8 num_dumped_cond_regs; /* number of dumped condition registers */ |
365 | u8 num_dumped_info_regs; /* number of dumped condition registers */ |
366 | u8 severity; /* from dbg_idle_chk_severity_types enum */ |
367 | u8 reserved; |
368 | }; |
369 | |
370 | /* Idle Check result register header */ |
371 | struct dbg_idle_chk_result_reg_hdr { |
372 | u8 data; |
373 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 |
374 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 |
375 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F |
376 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 |
377 | u8 start_entry; /* index of the first checked entry */ |
378 | u16 size; /* register size in dwords */ |
379 | }; |
380 | |
381 | /* Idle Check rule */ |
382 | struct dbg_idle_chk_rule { |
383 | u16 rule_id; /* Idle Check rule ID */ |
384 | u8 severity; /* value from dbg_idle_chk_severity_types enum */ |
385 | u8 cond_id; /* Condition ID */ |
386 | u8 num_cond_regs; /* number of condition registers */ |
387 | u8 num_info_regs; /* number of info registers */ |
388 | u8 num_imms; /* number of immediates in the condition */ |
389 | u8 reserved1; |
390 | u16 reg_offset; /* offset of this rules registers in the idle check |
391 | * register array (in dbg_idle_chk_reg units). |
392 | */ |
393 | u16 imm_offset; /* offset of this rules immediate values in the |
394 | * immediate values array (in dwords). |
395 | */ |
396 | }; |
397 | |
398 | /* Idle Check rule parsing data */ |
399 | struct dbg_idle_chk_rule_parsing_data { |
400 | u32 data; |
401 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 |
402 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 |
403 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF |
404 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 |
405 | }; |
406 | |
407 | /* Idle check severity types */ |
408 | enum dbg_idle_chk_severity_types { |
409 | /* idle check failure should cause an error */ |
410 | IDLE_CHK_SEVERITY_ERROR, |
411 | /* idle check failure should cause an error only if theres no traffic */ |
412 | IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, |
413 | /* idle check failure should cause a warning */ |
414 | IDLE_CHK_SEVERITY_WARNING, |
415 | MAX_DBG_IDLE_CHK_SEVERITY_TYPES |
416 | }; |
417 | |
418 | /* Reset register */ |
419 | struct dbg_reset_reg { |
420 | u32 data; |
421 | #define DBG_RESET_REG_ADDR_MASK 0xFFFFFF |
422 | #define DBG_RESET_REG_ADDR_SHIFT 0 |
423 | #define DBG_RESET_REG_IS_REMOVED_MASK 0x1 |
424 | #define DBG_RESET_REG_IS_REMOVED_SHIFT 24 |
425 | #define DBG_RESET_REG_RESERVED_MASK 0x7F |
426 | #define DBG_RESET_REG_RESERVED_SHIFT 25 |
427 | }; |
428 | |
429 | /* Debug Bus block data */ |
430 | struct dbg_bus_block_data { |
431 | u8 enable_mask; |
432 | u8 right_shift; |
433 | u8 force_valid_mask; |
434 | u8 force_frame_mask; |
435 | u8 dword_mask; |
436 | u8 line_num; |
437 | u8 hw_id; |
438 | u8 flags; |
439 | #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1 |
440 | #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0 |
441 | #define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F |
442 | #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1 |
443 | }; |
444 | |
445 | enum dbg_bus_clients { |
446 | DBG_BUS_CLIENT_RBCN, |
447 | DBG_BUS_CLIENT_RBCP, |
448 | DBG_BUS_CLIENT_RBCR, |
449 | DBG_BUS_CLIENT_RBCT, |
450 | DBG_BUS_CLIENT_RBCU, |
451 | DBG_BUS_CLIENT_RBCF, |
452 | DBG_BUS_CLIENT_RBCX, |
453 | DBG_BUS_CLIENT_RBCS, |
454 | DBG_BUS_CLIENT_RBCH, |
455 | DBG_BUS_CLIENT_RBCZ, |
456 | DBG_BUS_CLIENT_OTHER_ENGINE, |
457 | DBG_BUS_CLIENT_TIMESTAMP, |
458 | DBG_BUS_CLIENT_CPU, |
459 | DBG_BUS_CLIENT_RBCY, |
460 | DBG_BUS_CLIENT_RBCQ, |
461 | DBG_BUS_CLIENT_RBCM, |
462 | DBG_BUS_CLIENT_RBCB, |
463 | DBG_BUS_CLIENT_RBCW, |
464 | DBG_BUS_CLIENT_RBCV, |
465 | MAX_DBG_BUS_CLIENTS |
466 | }; |
467 | |
468 | /* Debug Bus constraint operation types */ |
469 | enum dbg_bus_constraint_ops { |
470 | DBG_BUS_CONSTRAINT_OP_EQ, |
471 | DBG_BUS_CONSTRAINT_OP_NE, |
472 | DBG_BUS_CONSTRAINT_OP_LT, |
473 | DBG_BUS_CONSTRAINT_OP_LTC, |
474 | DBG_BUS_CONSTRAINT_OP_LE, |
475 | DBG_BUS_CONSTRAINT_OP_LEC, |
476 | DBG_BUS_CONSTRAINT_OP_GT, |
477 | DBG_BUS_CONSTRAINT_OP_GTC, |
478 | DBG_BUS_CONSTRAINT_OP_GE, |
479 | DBG_BUS_CONSTRAINT_OP_GEC, |
480 | MAX_DBG_BUS_CONSTRAINT_OPS |
481 | }; |
482 | |
483 | /* Debug Bus trigger state data */ |
484 | struct dbg_bus_trigger_state_data { |
485 | u8 msg_len; |
486 | u8 constraint_dword_mask; |
487 | u8 storm_id; |
488 | u8 reserved; |
489 | }; |
490 | |
491 | /* Debug Bus memory address */ |
492 | struct dbg_bus_mem_addr { |
493 | u32 lo; |
494 | u32 hi; |
495 | }; |
496 | |
497 | /* Debug Bus PCI buffer data */ |
498 | struct dbg_bus_pci_buf_data { |
499 | struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ |
500 | struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ |
501 | u32 size; /* PCI buffer size in bytes */ |
502 | }; |
503 | |
504 | /* Debug Bus Storm EID range filter params */ |
505 | struct dbg_bus_storm_eid_range_params { |
506 | u8 min; /* Minimal event ID to filter on */ |
507 | u8 max; /* Maximal event ID to filter on */ |
508 | }; |
509 | |
510 | /* Debug Bus Storm EID mask filter params */ |
511 | struct dbg_bus_storm_eid_mask_params { |
512 | u8 val; /* Event ID value */ |
513 | u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ |
514 | }; |
515 | |
516 | /* Debug Bus Storm EID filter params */ |
517 | union dbg_bus_storm_eid_params { |
518 | struct dbg_bus_storm_eid_range_params range; |
519 | struct dbg_bus_storm_eid_mask_params mask; |
520 | }; |
521 | |
522 | /* Debug Bus Storm data */ |
523 | struct dbg_bus_storm_data { |
524 | u8 enabled; |
525 | u8 mode; |
526 | u8 hw_id; |
527 | u8 eid_filter_en; |
528 | u8 eid_range_not_mask; |
529 | u8 cid_filter_en; |
530 | union dbg_bus_storm_eid_params eid_filter_params; |
531 | u32 cid; |
532 | }; |
533 | |
534 | /* Debug Bus data */ |
535 | struct dbg_bus_data { |
536 | u32 app_version; |
537 | u8 state; |
538 | u8 mode_256b_en; |
539 | u8 num_enabled_blocks; |
540 | u8 num_enabled_storms; |
541 | u8 target; |
542 | u8 one_shot_en; |
543 | u8 grc_input_en; |
544 | u8 timestamp_input_en; |
545 | u8 filter_en; |
546 | u8 adding_filter; |
547 | u8 filter_pre_trigger; |
548 | u8 filter_post_trigger; |
549 | u8 trigger_en; |
550 | u8 filter_constraint_dword_mask; |
551 | u8 next_trigger_state; |
552 | u8 next_constraint_id; |
553 | struct dbg_bus_trigger_state_data trigger_states[3]; |
554 | u8 filter_msg_len; |
555 | u8 rcv_from_other_engine; |
556 | u8 blocks_dword_mask; |
557 | u8 blocks_dword_overlap; |
558 | u32 hw_id_mask; |
559 | struct dbg_bus_pci_buf_data pci_buf; |
560 | struct dbg_bus_block_data blocks[132]; |
561 | struct dbg_bus_storm_data storms[6]; |
562 | }; |
563 | |
564 | /* Debug bus states */ |
565 | enum dbg_bus_states { |
566 | DBG_BUS_STATE_IDLE, |
567 | DBG_BUS_STATE_READY, |
568 | DBG_BUS_STATE_RECORDING, |
569 | DBG_BUS_STATE_STOPPED, |
570 | MAX_DBG_BUS_STATES |
571 | }; |
572 | |
573 | /* Debug Bus Storm modes */ |
574 | enum dbg_bus_storm_modes { |
575 | DBG_BUS_STORM_MODE_PRINTF, |
576 | DBG_BUS_STORM_MODE_PRAM_ADDR, |
577 | DBG_BUS_STORM_MODE_DRA_RW, |
578 | DBG_BUS_STORM_MODE_DRA_W, |
579 | DBG_BUS_STORM_MODE_LD_ST_ADDR, |
580 | DBG_BUS_STORM_MODE_DRA_FSM, |
581 | DBG_BUS_STORM_MODE_FAST_DBGMUX, |
582 | DBG_BUS_STORM_MODE_RH, |
583 | DBG_BUS_STORM_MODE_RH_WITH_STORE, |
584 | DBG_BUS_STORM_MODE_FOC, |
585 | DBG_BUS_STORM_MODE_EXT_STORE, |
586 | MAX_DBG_BUS_STORM_MODES |
587 | }; |
588 | |
589 | /* Debug bus target IDs */ |
590 | enum dbg_bus_targets { |
591 | DBG_BUS_TARGET_ID_INT_BUF, |
592 | DBG_BUS_TARGET_ID_NIG, |
593 | DBG_BUS_TARGET_ID_PCI, |
594 | MAX_DBG_BUS_TARGETS |
595 | }; |
596 | |
597 | /* GRC Dump data */ |
598 | struct dbg_grc_data { |
599 | u8 params_initialized; |
600 | u8 reserved1; |
601 | u16 reserved2; |
602 | u32 param_val[48]; |
603 | }; |
604 | |
605 | /* Debug GRC params */ |
606 | enum dbg_grc_params { |
607 | DBG_GRC_PARAM_DUMP_TSTORM, |
608 | DBG_GRC_PARAM_DUMP_MSTORM, |
609 | DBG_GRC_PARAM_DUMP_USTORM, |
610 | DBG_GRC_PARAM_DUMP_XSTORM, |
611 | DBG_GRC_PARAM_DUMP_YSTORM, |
612 | DBG_GRC_PARAM_DUMP_PSTORM, |
613 | DBG_GRC_PARAM_DUMP_REGS, |
614 | DBG_GRC_PARAM_DUMP_RAM, |
615 | DBG_GRC_PARAM_DUMP_PBUF, |
616 | DBG_GRC_PARAM_DUMP_IOR, |
617 | DBG_GRC_PARAM_DUMP_VFC, |
618 | DBG_GRC_PARAM_DUMP_CM_CTX, |
619 | DBG_GRC_PARAM_DUMP_PXP, |
620 | , |
621 | DBG_GRC_PARAM_DUMP_CAU, |
622 | DBG_GRC_PARAM_DUMP_QM, |
623 | DBG_GRC_PARAM_DUMP_MCP, |
624 | DBG_GRC_PARAM_DUMP_DORQ, |
625 | DBG_GRC_PARAM_DUMP_CFC, |
626 | DBG_GRC_PARAM_DUMP_IGU, |
627 | DBG_GRC_PARAM_DUMP_BRB, |
628 | DBG_GRC_PARAM_DUMP_BTB, |
629 | DBG_GRC_PARAM_DUMP_BMB, |
630 | DBG_GRC_PARAM_RESERVD1, |
631 | DBG_GRC_PARAM_DUMP_MULD, |
632 | DBG_GRC_PARAM_DUMP_PRS, |
633 | DBG_GRC_PARAM_DUMP_DMAE, |
634 | DBG_GRC_PARAM_DUMP_TM, |
635 | DBG_GRC_PARAM_DUMP_SDM, |
636 | DBG_GRC_PARAM_DUMP_DIF, |
637 | DBG_GRC_PARAM_DUMP_STATIC, |
638 | DBG_GRC_PARAM_UNSTALL, |
639 | DBG_GRC_PARAM_RESERVED2, |
640 | DBG_GRC_PARAM_MCP_TRACE_META_SIZE, |
641 | DBG_GRC_PARAM_EXCLUDE_ALL, |
642 | DBG_GRC_PARAM_CRASH, |
643 | DBG_GRC_PARAM_PARITY_SAFE, |
644 | DBG_GRC_PARAM_DUMP_CM, |
645 | DBG_GRC_PARAM_DUMP_PHY, |
646 | DBG_GRC_PARAM_NO_MCP, |
647 | DBG_GRC_PARAM_NO_FW_VER, |
648 | DBG_GRC_PARAM_RESERVED3, |
649 | DBG_GRC_PARAM_DUMP_MCP_HW_DUMP, |
650 | DBG_GRC_PARAM_DUMP_ILT_CDUC, |
651 | DBG_GRC_PARAM_DUMP_ILT_CDUT, |
652 | DBG_GRC_PARAM_DUMP_CAU_EXT, |
653 | MAX_DBG_GRC_PARAMS |
654 | }; |
655 | |
656 | /* Debug status codes */ |
657 | enum dbg_status { |
658 | DBG_STATUS_OK, |
659 | DBG_STATUS_APP_VERSION_NOT_SET, |
660 | DBG_STATUS_UNSUPPORTED_APP_VERSION, |
661 | DBG_STATUS_DBG_BLOCK_NOT_RESET, |
662 | DBG_STATUS_INVALID_ARGS, |
663 | DBG_STATUS_OUTPUT_ALREADY_SET, |
664 | DBG_STATUS_INVALID_PCI_BUF_SIZE, |
665 | DBG_STATUS_PCI_BUF_ALLOC_FAILED, |
666 | DBG_STATUS_PCI_BUF_NOT_ALLOCATED, |
667 | DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS, |
668 | DBG_STATUS_NO_MATCHING_FRAMING_MODE, |
669 | DBG_STATUS_VFC_READ_ERROR, |
670 | DBG_STATUS_STORM_ALREADY_ENABLED, |
671 | DBG_STATUS_STORM_NOT_ENABLED, |
672 | DBG_STATUS_BLOCK_ALREADY_ENABLED, |
673 | DBG_STATUS_BLOCK_NOT_ENABLED, |
674 | DBG_STATUS_NO_INPUT_ENABLED, |
675 | DBG_STATUS_NO_FILTER_TRIGGER_256B, |
676 | DBG_STATUS_FILTER_ALREADY_ENABLED, |
677 | DBG_STATUS_TRIGGER_ALREADY_ENABLED, |
678 | DBG_STATUS_TRIGGER_NOT_ENABLED, |
679 | DBG_STATUS_CANT_ADD_CONSTRAINT, |
680 | DBG_STATUS_TOO_MANY_TRIGGER_STATES, |
681 | DBG_STATUS_TOO_MANY_CONSTRAINTS, |
682 | DBG_STATUS_RECORDING_NOT_STARTED, |
683 | DBG_STATUS_DATA_DIDNT_TRIGGER, |
684 | DBG_STATUS_NO_DATA_RECORDED, |
685 | DBG_STATUS_DUMP_BUF_TOO_SMALL, |
686 | DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, |
687 | DBG_STATUS_UNKNOWN_CHIP, |
688 | DBG_STATUS_VIRT_MEM_ALLOC_FAILED, |
689 | DBG_STATUS_BLOCK_IN_RESET, |
690 | DBG_STATUS_INVALID_TRACE_SIGNATURE, |
691 | DBG_STATUS_INVALID_NVRAM_BUNDLE, |
692 | DBG_STATUS_NVRAM_GET_IMAGE_FAILED, |
693 | DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, |
694 | DBG_STATUS_NVRAM_READ_FAILED, |
695 | DBG_STATUS_IDLE_CHK_PARSE_FAILED, |
696 | DBG_STATUS_MCP_TRACE_BAD_DATA, |
697 | DBG_STATUS_MCP_TRACE_NO_META, |
698 | DBG_STATUS_MCP_COULD_NOT_HALT, |
699 | DBG_STATUS_MCP_COULD_NOT_RESUME, |
700 | DBG_STATUS_RESERVED0, |
701 | DBG_STATUS_SEMI_FIFO_NOT_EMPTY, |
702 | DBG_STATUS_IGU_FIFO_BAD_DATA, |
703 | DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, |
704 | DBG_STATUS_FW_ASSERTS_PARSE_FAILED, |
705 | DBG_STATUS_REG_FIFO_BAD_DATA, |
706 | DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, |
707 | DBG_STATUS_DBG_ARRAY_NOT_SET, |
708 | DBG_STATUS_RESERVED1, |
709 | DBG_STATUS_NON_MATCHING_LINES, |
710 | DBG_STATUS_INSUFFICIENT_HW_IDS, |
711 | DBG_STATUS_DBG_BUS_IN_USE, |
712 | DBG_STATUS_INVALID_STORM_DBG_MODE, |
713 | DBG_STATUS_OTHER_ENGINE_BB_ONLY, |
714 | DBG_STATUS_FILTER_SINGLE_HW_ID, |
715 | DBG_STATUS_TRIGGER_SINGLE_HW_ID, |
716 | DBG_STATUS_MISSING_TRIGGER_STATE_STORM, |
717 | MAX_DBG_STATUS |
718 | }; |
719 | |
720 | /* Debug Storms IDs */ |
721 | enum dbg_storms { |
722 | DBG_TSTORM_ID, |
723 | DBG_MSTORM_ID, |
724 | DBG_USTORM_ID, |
725 | DBG_XSTORM_ID, |
726 | DBG_YSTORM_ID, |
727 | DBG_PSTORM_ID, |
728 | MAX_DBG_STORMS |
729 | }; |
730 | |
731 | /* Idle Check data */ |
732 | struct idle_chk_data { |
733 | u32 buf_size; |
734 | u8 buf_size_set; |
735 | u8 reserved1; |
736 | u16 reserved2; |
737 | }; |
738 | |
739 | struct pretend_params { |
740 | u8 split_type; |
741 | u8 reserved; |
742 | u16 split_id; |
743 | }; |
744 | |
745 | /* Debug Tools data (per HW function) |
746 | */ |
747 | struct dbg_tools_data { |
748 | struct dbg_grc_data grc; |
749 | struct dbg_bus_data bus; |
750 | struct idle_chk_data idle_chk; |
751 | u8 mode_enable[40]; |
752 | u8 block_in_reset[132]; |
753 | u8 chip_id; |
754 | u8 hw_type; |
755 | u8 num_ports; |
756 | u8 num_pfs_per_port; |
757 | u8 num_vfs; |
758 | u8 initialized; |
759 | u8 use_dmae; |
760 | u8 reserved; |
761 | struct pretend_params pretend; |
762 | u32 num_regs_read; |
763 | }; |
764 | |
765 | /* ILT Clients */ |
766 | enum ilt_clients { |
767 | ILT_CLI_CDUC, |
768 | ILT_CLI_CDUT, |
769 | ILT_CLI_QM, |
770 | ILT_CLI_TM, |
771 | ILT_CLI_SRC, |
772 | ILT_CLI_TSDM, |
773 | ILT_CLI_RGFS, |
774 | ILT_CLI_TGFS, |
775 | MAX_ILT_CLIENTS |
776 | }; |
777 | |
778 | /***************************** Public Functions *******************************/ |
779 | |
780 | /** |
781 | * qed_dbg_set_bin_ptr(): Sets a pointer to the binary data with debug |
782 | * arrays. |
783 | * |
784 | * @p_hwfn: HW device data. |
785 | * @bin_ptr: A pointer to the binary data with debug arrays. |
786 | * |
787 | * Return: enum dbg status. |
788 | */ |
789 | enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn, |
790 | const u8 * const bin_ptr); |
791 | |
792 | /** |
793 | * qed_read_regs(): Reads registers into a buffer (using GRC). |
794 | * |
795 | * @p_hwfn: HW device data. |
796 | * @p_ptt: Ptt window used for writing the registers. |
797 | * @buf: Destination buffer. |
798 | * @addr: Source GRC address in dwords. |
799 | * @len: Number of registers to read. |
800 | * |
801 | * Return: Void. |
802 | */ |
803 | void qed_read_regs(struct qed_hwfn *p_hwfn, |
804 | struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len); |
805 | |
806 | /** |
807 | * qed_read_fw_info(): Reads FW info from the chip. |
808 | * |
809 | * @p_hwfn: HW device data. |
810 | * @p_ptt: Ptt window used for writing the registers. |
811 | * @fw_info: (Out) a pointer to write the FW info into. |
812 | * |
813 | * Return: True if the FW info was read successfully from one of the Storms, |
814 | * or false if all Storms are in reset. |
815 | * |
816 | * The FW info contains FW-related information, such as the FW version, |
817 | * FW image (main/L2B/kuku), FW timestamp, etc. |
818 | * The FW info is read from the internal RAM of the first Storm that is not in |
819 | * reset. |
820 | */ |
821 | bool qed_read_fw_info(struct qed_hwfn *p_hwfn, |
822 | struct qed_ptt *p_ptt, struct fw_info *fw_info); |
823 | /** |
824 | * qed_dbg_grc_config(): Sets the value of a GRC parameter. |
825 | * |
826 | * @p_hwfn: HW device data. |
827 | * @grc_param: GRC parameter. |
828 | * @val: Value to set. |
829 | * |
830 | * Return: Error if one of the following holds: |
831 | * - The version wasn't set. |
832 | * - Grc_param is invalid. |
833 | * - Val is outside the allowed boundaries. |
834 | */ |
835 | enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn, |
836 | enum dbg_grc_params grc_param, u32 val); |
837 | |
838 | /** |
839 | * qed_dbg_grc_set_params_default(): Reverts all GRC parameters to their |
840 | * default value. |
841 | * |
842 | * @p_hwfn: HW device data. |
843 | * |
844 | * Return: Void. |
845 | */ |
846 | void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn); |
847 | /** |
848 | * qed_dbg_grc_get_dump_buf_size(): Returns the required buffer size for |
849 | * GRC Dump. |
850 | * |
851 | * @p_hwfn: HW device data. |
852 | * @p_ptt: Ptt window used for writing the registers. |
853 | * @buf_size: (OUT) required buffer size (in dwords) for the GRC Dump |
854 | * data. |
855 | * |
856 | * Return: Error if one of the following holds: |
857 | * - The version wasn't set |
858 | * Otherwise, returns ok. |
859 | */ |
860 | enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
861 | struct qed_ptt *p_ptt, |
862 | u32 *buf_size); |
863 | |
864 | /** |
865 | * qed_dbg_grc_dump(): Dumps GRC data into the specified buffer. |
866 | * |
867 | * @p_hwfn: HW device data. |
868 | * @p_ptt: Ptt window used for writing the registers. |
869 | * @dump_buf: Pointer to write the collected GRC data into. |
870 | * @buf_size_in_dwords:Size of the specified buffer in dwords. |
871 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
872 | * |
873 | * Return: Error if one of the following holds: |
874 | * - The version wasn't set. |
875 | * - The specified dump buffer is too small. |
876 | * Otherwise, returns ok. |
877 | */ |
878 | enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, |
879 | struct qed_ptt *p_ptt, |
880 | u32 *dump_buf, |
881 | u32 buf_size_in_dwords, |
882 | u32 *num_dumped_dwords); |
883 | |
884 | /** |
885 | * qed_dbg_idle_chk_get_dump_buf_size(): Returns the required buffer size |
886 | * for idle check results. |
887 | * |
888 | * @p_hwfn: HW device data. |
889 | * @p_ptt: Ptt window used for writing the registers. |
890 | * @buf_size: (OUT) required buffer size (in dwords) for the idle check |
891 | * data. |
892 | * |
893 | * return: Error if one of the following holds: |
894 | * - The version wasn't set. |
895 | * Otherwise, returns ok. |
896 | */ |
897 | enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
898 | struct qed_ptt *p_ptt, |
899 | u32 *buf_size); |
900 | |
901 | /** |
902 | * qed_dbg_idle_chk_dump: Performs idle check and writes the results |
903 | * into the specified buffer. |
904 | * |
905 | * @p_hwfn: HW device data. |
906 | * @p_ptt: Ptt window used for writing the registers. |
907 | * @dump_buf: Pointer to write the idle check data into. |
908 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
909 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
910 | * |
911 | * Return: Error if one of the following holds: |
912 | * - The version wasn't set. |
913 | * - The specified buffer is too small. |
914 | * Otherwise, returns ok. |
915 | */ |
916 | enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, |
917 | struct qed_ptt *p_ptt, |
918 | u32 *dump_buf, |
919 | u32 buf_size_in_dwords, |
920 | u32 *num_dumped_dwords); |
921 | |
922 | /** |
923 | * qed_dbg_mcp_trace_get_dump_buf_size(): Returns the required buffer size |
924 | * for mcp trace results. |
925 | * |
926 | * @p_hwfn: HW device data. |
927 | * @p_ptt: Ptt window used for writing the registers. |
928 | * @buf_size: (OUT) Required buffer size (in dwords) for mcp trace data. |
929 | * |
930 | * Return: Error if one of the following holds: |
931 | * - The version wasn't set. |
932 | * - The trace data in MCP scratchpad contain an invalid signature. |
933 | * - The bundle ID in NVRAM is invalid. |
934 | * - The trace meta data cannot be found (in NVRAM or image file). |
935 | * Otherwise, returns ok. |
936 | */ |
937 | enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
938 | struct qed_ptt *p_ptt, |
939 | u32 *buf_size); |
940 | |
941 | /** |
942 | * qed_dbg_mcp_trace_dump(): Performs mcp trace and writes the results |
943 | * into the specified buffer. |
944 | * |
945 | * @p_hwfn: HW device data. |
946 | * @p_ptt: Ptt window used for writing the registers. |
947 | * @dump_buf: Pointer to write the mcp trace data into. |
948 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
949 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
950 | * |
951 | * Return: Error if one of the following holds: |
952 | * - The version wasn't set. |
953 | * - The specified buffer is too small. |
954 | * - The trace data in MCP scratchpad contain an invalid signature. |
955 | * - The bundle ID in NVRAM is invalid. |
956 | * - The trace meta data cannot be found (in NVRAM or image file). |
957 | * - The trace meta data cannot be read (from NVRAM or image file). |
958 | * Otherwise, returns ok. |
959 | */ |
960 | enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, |
961 | struct qed_ptt *p_ptt, |
962 | u32 *dump_buf, |
963 | u32 buf_size_in_dwords, |
964 | u32 *num_dumped_dwords); |
965 | |
966 | /** |
967 | * qed_dbg_reg_fifo_get_dump_buf_size(): Returns the required buffer size |
968 | * for grc trace fifo results. |
969 | * |
970 | * @p_hwfn: HW device data. |
971 | * @p_ptt: Ptt window used for writing the registers. |
972 | * @buf_size: (OUT) Required buffer size (in dwords) for reg fifo data. |
973 | * |
974 | * Return: Error if one of the following holds: |
975 | * - The version wasn't set |
976 | * Otherwise, returns ok. |
977 | */ |
978 | enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
979 | struct qed_ptt *p_ptt, |
980 | u32 *buf_size); |
981 | |
982 | /** |
983 | * qed_dbg_reg_fifo_dump(): Reads the reg fifo and writes the results into |
984 | * the specified buffer. |
985 | * |
986 | * @p_hwfn: HW device data. |
987 | * @p_ptt: Ptt window used for writing the registers. |
988 | * @dump_buf: Pointer to write the reg fifo data into. |
989 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
990 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
991 | * |
992 | * Return: Error if one of the following holds: |
993 | * - The version wasn't set. |
994 | * - The specified buffer is too small. |
995 | * - DMAE transaction failed. |
996 | * Otherwise, returns ok. |
997 | */ |
998 | enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, |
999 | struct qed_ptt *p_ptt, |
1000 | u32 *dump_buf, |
1001 | u32 buf_size_in_dwords, |
1002 | u32 *num_dumped_dwords); |
1003 | |
1004 | /** |
1005 | * qed_dbg_igu_fifo_get_dump_buf_size(): Returns the required buffer size |
1006 | * for the IGU fifo results. |
1007 | * |
1008 | * @p_hwfn: HW device data. |
1009 | * @p_ptt: Ptt window used for writing the registers. |
1010 | * @buf_size: (OUT) Required buffer size (in dwords) for the IGU fifo |
1011 | * data. |
1012 | * |
1013 | * Return: Error if one of the following holds: |
1014 | * - The version wasn't set. |
1015 | * Otherwise, returns ok. |
1016 | */ |
1017 | enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
1018 | struct qed_ptt *p_ptt, |
1019 | u32 *buf_size); |
1020 | |
1021 | /** |
1022 | * qed_dbg_igu_fifo_dump(): Reads the IGU fifo and writes the results into |
1023 | * the specified buffer. |
1024 | * |
1025 | * @p_hwfn: HW device data. |
1026 | * @p_ptt: Ptt window used for writing the registers. |
1027 | * @dump_buf: Pointer to write the IGU fifo data into. |
1028 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
1029 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
1030 | * |
1031 | * Return: Error if one of the following holds: |
1032 | * - The version wasn't set |
1033 | * - The specified buffer is too small |
1034 | * - DMAE transaction failed |
1035 | * Otherwise, returns ok. |
1036 | */ |
1037 | enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, |
1038 | struct qed_ptt *p_ptt, |
1039 | u32 *dump_buf, |
1040 | u32 buf_size_in_dwords, |
1041 | u32 *num_dumped_dwords); |
1042 | |
1043 | /** |
1044 | * qed_dbg_protection_override_get_dump_buf_size(): Returns the required |
1045 | * buffer size for protection override window results. |
1046 | * |
1047 | * @p_hwfn: HW device data. |
1048 | * @p_ptt: Ptt window used for writing the registers. |
1049 | * @buf_size: (OUT) Required buffer size (in dwords) for protection |
1050 | * override data. |
1051 | * |
1052 | * Return: Error if one of the following holds: |
1053 | * - The version wasn't set |
1054 | * Otherwise, returns ok. |
1055 | */ |
1056 | enum dbg_status |
1057 | qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
1058 | struct qed_ptt *p_ptt, |
1059 | u32 *buf_size); |
1060 | /** |
1061 | * qed_dbg_protection_override_dump(): Reads protection override window |
1062 | * entries and writes the results into the specified buffer. |
1063 | * |
1064 | * @p_hwfn: HW device data. |
1065 | * @p_ptt: Ptt window used for writing the registers. |
1066 | * @dump_buf: Pointer to write the protection override data into. |
1067 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
1068 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
1069 | * |
1070 | * @return: Error if one of the following holds: |
1071 | * - The version wasn't set. |
1072 | * - The specified buffer is too small. |
1073 | * - DMAE transaction failed. |
1074 | * Otherwise, returns ok. |
1075 | */ |
1076 | enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, |
1077 | struct qed_ptt *p_ptt, |
1078 | u32 *dump_buf, |
1079 | u32 buf_size_in_dwords, |
1080 | u32 *num_dumped_dwords); |
1081 | /** |
1082 | * qed_dbg_fw_asserts_get_dump_buf_size(): Returns the required buffer |
1083 | * size for FW Asserts results. |
1084 | * |
1085 | * @p_hwfn: HW device data. |
1086 | * @p_ptt: Ptt window used for writing the registers. |
1087 | * @buf_size: (OUT) Required buffer size (in dwords) for FW Asserts data. |
1088 | * |
1089 | * Return: Error if one of the following holds: |
1090 | * - The version wasn't set. |
1091 | * Otherwise, returns ok. |
1092 | */ |
1093 | enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, |
1094 | struct qed_ptt *p_ptt, |
1095 | u32 *buf_size); |
1096 | /** |
1097 | * qed_dbg_fw_asserts_dump(): Reads the FW Asserts and writes the results |
1098 | * into the specified buffer. |
1099 | * |
1100 | * @p_hwfn: HW device data. |
1101 | * @p_ptt: Ptt window used for writing the registers. |
1102 | * @dump_buf: Pointer to write the FW Asserts data into. |
1103 | * @buf_size_in_dwords: Size of the specified buffer in dwords. |
1104 | * @num_dumped_dwords: (OUT) number of dumped dwords. |
1105 | * |
1106 | * Return: Error if one of the following holds: |
1107 | * - The version wasn't set. |
1108 | * - The specified buffer is too small. |
1109 | * Otherwise, returns ok. |
1110 | */ |
1111 | enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, |
1112 | struct qed_ptt *p_ptt, |
1113 | u32 *dump_buf, |
1114 | u32 buf_size_in_dwords, |
1115 | u32 *num_dumped_dwords); |
1116 | |
1117 | /** |
1118 | * qed_dbg_read_attn(): Reads the attention registers of the specified |
1119 | * block and type, and writes the results into the specified buffer. |
1120 | * |
1121 | * @p_hwfn: HW device data. |
1122 | * @p_ptt: Ptt window used for writing the registers. |
1123 | * @block: Block ID. |
1124 | * @attn_type: Attention type. |
1125 | * @clear_status: Indicates if the attention status should be cleared. |
1126 | * @results: (OUT) Pointer to write the read results into. |
1127 | * |
1128 | * Return: Error if one of the following holds: |
1129 | * - The version wasn't set |
1130 | * Otherwise, returns ok. |
1131 | */ |
1132 | enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, |
1133 | struct qed_ptt *p_ptt, |
1134 | enum block_id block, |
1135 | enum dbg_attn_type attn_type, |
1136 | bool clear_status, |
1137 | struct dbg_attn_block_result *results); |
1138 | |
1139 | /** |
1140 | * qed_dbg_print_attn(): Prints attention registers values in the |
1141 | * specified results struct. |
1142 | * |
1143 | * @p_hwfn: HW device data. |
1144 | * @results: Pointer to the attention read results |
1145 | * |
1146 | * Return: Error if one of the following holds: |
1147 | * - The version wasn't set |
1148 | * Otherwise, returns ok. |
1149 | */ |
1150 | enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, |
1151 | struct dbg_attn_block_result *results); |
1152 | |
1153 | /******************************* Data Types **********************************/ |
1154 | |
1155 | struct mcp_trace_format { |
1156 | u32 data; |
1157 | #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff |
1158 | #define MCP_TRACE_FORMAT_MODULE_OFFSET 0 |
1159 | #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000 |
1160 | #define MCP_TRACE_FORMAT_LEVEL_OFFSET 16 |
1161 | #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000 |
1162 | #define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18 |
1163 | #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000 |
1164 | #define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20 |
1165 | #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000 |
1166 | #define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22 |
1167 | #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000 |
1168 | #define MCP_TRACE_FORMAT_LEN_OFFSET 24 |
1169 | |
1170 | char *format_str; |
1171 | }; |
1172 | |
1173 | /* MCP Trace Meta data structure */ |
1174 | struct mcp_trace_meta { |
1175 | u32 modules_num; |
1176 | char **modules; |
1177 | u32 formats_num; |
1178 | struct mcp_trace_format *formats; |
1179 | bool is_allocated; |
1180 | }; |
1181 | |
1182 | /* Debug Tools user data */ |
1183 | struct dbg_tools_user_data { |
1184 | struct mcp_trace_meta mcp_trace_meta; |
1185 | const u32 *mcp_trace_user_meta_buf; |
1186 | }; |
1187 | |
1188 | /******************************** Constants **********************************/ |
1189 | |
1190 | #define MAX_NAME_LEN 16 |
1191 | |
1192 | /***************************** Public Functions *******************************/ |
1193 | |
1194 | /** |
1195 | * qed_dbg_user_set_bin_ptr(): Sets a pointer to the binary data with |
1196 | * debug arrays. |
1197 | * |
1198 | * @p_hwfn: HW device data. |
1199 | * @bin_ptr: a pointer to the binary data with debug arrays. |
1200 | * |
1201 | * Return: dbg_status. |
1202 | */ |
1203 | enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn, |
1204 | const u8 * const bin_ptr); |
1205 | |
1206 | /** |
1207 | * qed_dbg_alloc_user_data(): Allocates user debug data. |
1208 | * |
1209 | * @p_hwfn: HW device data. |
1210 | * @user_data_ptr: (OUT) a pointer to the allocated memory. |
1211 | * |
1212 | * Return: dbg_status. |
1213 | */ |
1214 | enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn, |
1215 | void **user_data_ptr); |
1216 | |
1217 | /** |
1218 | * qed_dbg_get_status_str(): Returns a string for the specified status. |
1219 | * |
1220 | * @status: A debug status code. |
1221 | * |
1222 | * Return: A string for the specified status. |
1223 | */ |
1224 | const char *qed_dbg_get_status_str(enum dbg_status status); |
1225 | |
1226 | /** |
1227 | * qed_get_idle_chk_results_buf_size(): Returns the required buffer size |
1228 | * for idle check results (in bytes). |
1229 | * |
1230 | * @p_hwfn: HW device data. |
1231 | * @dump_buf: idle check dump buffer. |
1232 | * @num_dumped_dwords: number of dwords that were dumped. |
1233 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1234 | * results. |
1235 | * |
1236 | * Return: Error if the parsing fails, ok otherwise. |
1237 | */ |
1238 | enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, |
1239 | u32 *dump_buf, |
1240 | u32 num_dumped_dwords, |
1241 | u32 *results_buf_size); |
1242 | /** |
1243 | * qed_print_idle_chk_results(): Prints idle check results |
1244 | * |
1245 | * @p_hwfn: HW device data. |
1246 | * @dump_buf: idle check dump buffer. |
1247 | * @num_dumped_dwords: number of dwords that were dumped. |
1248 | * @results_buf: buffer for printing the idle check results. |
1249 | * @num_errors: (OUT) number of errors found in idle check. |
1250 | * @num_warnings: (OUT) number of warnings found in idle check. |
1251 | * |
1252 | * Return: Error if the parsing fails, ok otherwise. |
1253 | */ |
1254 | enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, |
1255 | u32 *dump_buf, |
1256 | u32 num_dumped_dwords, |
1257 | char *results_buf, |
1258 | u32 *num_errors, |
1259 | u32 *num_warnings); |
1260 | |
1261 | /** |
1262 | * qed_dbg_mcp_trace_set_meta_data(): Sets the MCP Trace meta data. |
1263 | * |
1264 | * @p_hwfn: HW device data. |
1265 | * @meta_buf: Meta buffer. |
1266 | * |
1267 | * Return: Void. |
1268 | * |
1269 | * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to |
1270 | * no NVRAM access). |
1271 | */ |
1272 | void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn, |
1273 | const u32 *meta_buf); |
1274 | |
1275 | /** |
1276 | * qed_get_mcp_trace_results_buf_size(): Returns the required buffer size |
1277 | * for MCP Trace results (in bytes). |
1278 | * |
1279 | * @p_hwfn: HW device data. |
1280 | * @dump_buf: MCP Trace dump buffer. |
1281 | * @num_dumped_dwords: number of dwords that were dumped. |
1282 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1283 | * results. |
1284 | * |
1285 | * Return: Error if the parsing fails, ok otherwise. |
1286 | */ |
1287 | enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, |
1288 | u32 *dump_buf, |
1289 | u32 num_dumped_dwords, |
1290 | u32 *results_buf_size); |
1291 | |
1292 | /** |
1293 | * qed_print_mcp_trace_results(): Prints MCP Trace results |
1294 | * |
1295 | * @p_hwfn: HW device data. |
1296 | * @dump_buf: MCP trace dump buffer, starting from the header. |
1297 | * @num_dumped_dwords: Member of dwords that were dumped. |
1298 | * @results_buf: Buffer for printing the mcp trace results. |
1299 | * |
1300 | * Return: Error if the parsing fails, ok otherwise. |
1301 | */ |
1302 | enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, |
1303 | u32 *dump_buf, |
1304 | u32 num_dumped_dwords, |
1305 | char *results_buf); |
1306 | |
1307 | /** |
1308 | * qed_print_mcp_trace_results_cont(): Prints MCP Trace results, and |
1309 | * keeps the MCP trace meta data allocated, to support continuous MCP Trace |
1310 | * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should |
1311 | * be called to free the meta data. |
1312 | * |
1313 | * @p_hwfn: HW device data. |
1314 | * @dump_buf: MVP trace dump buffer, starting from the header. |
1315 | * @results_buf: Buffer for printing the mcp trace results. |
1316 | * |
1317 | * Return: Error if the parsing fails, ok otherwise. |
1318 | */ |
1319 | enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn, |
1320 | u32 *dump_buf, |
1321 | char *results_buf); |
1322 | |
1323 | /** |
1324 | * qed_print_mcp_trace_line(): Prints MCP Trace results for a single line |
1325 | * |
1326 | * @p_hwfn: HW device data. |
1327 | * @dump_buf: MCP trace dump buffer, starting from the header. |
1328 | * @num_dumped_bytes: Number of bytes that were dumped. |
1329 | * @results_buf: Buffer for printing the mcp trace results. |
1330 | * |
1331 | * Return: Error if the parsing fails, ok otherwise. |
1332 | */ |
1333 | enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn, |
1334 | u8 *dump_buf, |
1335 | u32 num_dumped_bytes, |
1336 | char *results_buf); |
1337 | |
1338 | /** |
1339 | * qed_mcp_trace_free_meta_data(): Frees the MCP Trace meta data. |
1340 | * Should be called after continuous MCP Trace parsing. |
1341 | * |
1342 | * @p_hwfn: HW device data. |
1343 | * |
1344 | * Return: Void. |
1345 | */ |
1346 | void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn); |
1347 | |
1348 | /** |
1349 | * qed_get_reg_fifo_results_buf_size(): Returns the required buffer size |
1350 | * for reg_fifo results (in bytes). |
1351 | * |
1352 | * @p_hwfn: HW device data. |
1353 | * @dump_buf: Reg fifo dump buffer. |
1354 | * @num_dumped_dwords: Number of dwords that were dumped. |
1355 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1356 | * results. |
1357 | * |
1358 | * Return: Error if the parsing fails, ok otherwise. |
1359 | */ |
1360 | enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, |
1361 | u32 *dump_buf, |
1362 | u32 num_dumped_dwords, |
1363 | u32 *results_buf_size); |
1364 | |
1365 | /** |
1366 | * qed_print_reg_fifo_results(): Prints reg fifo results. |
1367 | * |
1368 | * @p_hwfn: HW device data. |
1369 | * @dump_buf: Reg fifo dump buffer, starting from the header. |
1370 | * @num_dumped_dwords: Number of dwords that were dumped. |
1371 | * @results_buf: Buffer for printing the reg fifo results. |
1372 | * |
1373 | * Return: Error if the parsing fails, ok otherwise. |
1374 | */ |
1375 | enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, |
1376 | u32 *dump_buf, |
1377 | u32 num_dumped_dwords, |
1378 | char *results_buf); |
1379 | |
1380 | /** |
1381 | * qed_get_igu_fifo_results_buf_size(): Returns the required buffer size |
1382 | * for igu_fifo results (in bytes). |
1383 | * |
1384 | * @p_hwfn: HW device data. |
1385 | * @dump_buf: IGU fifo dump buffer. |
1386 | * @num_dumped_dwords: number of dwords that were dumped. |
1387 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1388 | * results. |
1389 | * |
1390 | * Return: Error if the parsing fails, ok otherwise. |
1391 | */ |
1392 | enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, |
1393 | u32 *dump_buf, |
1394 | u32 num_dumped_dwords, |
1395 | u32 *results_buf_size); |
1396 | |
1397 | /** |
1398 | * qed_print_igu_fifo_results(): Prints IGU fifo results |
1399 | * |
1400 | * @p_hwfn: HW device data. |
1401 | * @dump_buf: IGU fifo dump buffer, starting from the header. |
1402 | * @num_dumped_dwords: Number of dwords that were dumped. |
1403 | * @results_buf: Buffer for printing the IGU fifo results. |
1404 | * |
1405 | * Return: Error if the parsing fails, ok otherwise. |
1406 | */ |
1407 | enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, |
1408 | u32 *dump_buf, |
1409 | u32 num_dumped_dwords, |
1410 | char *results_buf); |
1411 | |
1412 | /** |
1413 | * qed_get_protection_override_results_buf_size(): Returns the required |
1414 | * buffer size for protection override results (in bytes). |
1415 | * |
1416 | * @p_hwfn: HW device data. |
1417 | * @dump_buf: Protection override dump buffer. |
1418 | * @num_dumped_dwords: Number of dwords that were dumped. |
1419 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1420 | * results. |
1421 | * |
1422 | * Return: Error if the parsing fails, ok otherwise. |
1423 | */ |
1424 | enum dbg_status |
1425 | qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, |
1426 | u32 *dump_buf, |
1427 | u32 num_dumped_dwords, |
1428 | u32 *results_buf_size); |
1429 | |
1430 | /** |
1431 | * qed_print_protection_override_results(): Prints protection override |
1432 | * results. |
1433 | * |
1434 | * @p_hwfn: HW device data. |
1435 | * @dump_buf: Protection override dump buffer, starting from the header. |
1436 | * @num_dumped_dwords: Number of dwords that were dumped. |
1437 | * @results_buf: Buffer for printing the reg fifo results. |
1438 | * |
1439 | * Return: Error if the parsing fails, ok otherwise. |
1440 | */ |
1441 | enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, |
1442 | u32 *dump_buf, |
1443 | u32 num_dumped_dwords, |
1444 | char *results_buf); |
1445 | |
1446 | /** |
1447 | * qed_get_fw_asserts_results_buf_size(): Returns the required buffer size |
1448 | * for FW Asserts results (in bytes). |
1449 | * |
1450 | * @p_hwfn: HW device data. |
1451 | * @dump_buf: FW Asserts dump buffer. |
1452 | * @num_dumped_dwords: number of dwords that were dumped. |
1453 | * @results_buf_size: (OUT) required buffer size (in bytes) for the parsed |
1454 | * results. |
1455 | * |
1456 | * Return: Error if the parsing fails, ok otherwise. |
1457 | */ |
1458 | enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, |
1459 | u32 *dump_buf, |
1460 | u32 num_dumped_dwords, |
1461 | u32 *results_buf_size); |
1462 | |
1463 | /** |
1464 | * qed_print_fw_asserts_results(): Prints FW Asserts results. |
1465 | * |
1466 | * @p_hwfn: HW device data. |
1467 | * @dump_buf: FW Asserts dump buffer, starting from the header. |
1468 | * @num_dumped_dwords: number of dwords that were dumped. |
1469 | * @results_buf: buffer for printing the FW Asserts results. |
1470 | * |
1471 | * Return: Error if the parsing fails, ok otherwise. |
1472 | */ |
1473 | enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, |
1474 | u32 *dump_buf, |
1475 | u32 num_dumped_dwords, |
1476 | char *results_buf); |
1477 | |
1478 | /** |
1479 | * qed_dbg_parse_attn(): Parses and prints attention registers values in |
1480 | * the specified results struct. |
1481 | * |
1482 | * @p_hwfn: HW device data. |
1483 | * @results: Pointer to the attention read results |
1484 | * |
1485 | * Return: Error if one of the following holds: |
1486 | * - The version wasn't set. |
1487 | * Otherwise, returns ok. |
1488 | */ |
1489 | enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, |
1490 | struct dbg_attn_block_result *results); |
1491 | #endif |
1492 | |