1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* TI K3 AM65x Common Platform Time Sync |
3 | * |
4 | * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com |
5 | * |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/clk-provider.h> |
10 | #include <linux/err.h> |
11 | #include <linux/if_vlan.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/module.h> |
14 | #include <linux/netdevice.h> |
15 | #include <linux/net_tstamp.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_irq.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/pm_runtime.h> |
20 | #include <linux/ptp_classify.h> |
21 | #include <linux/ptp_clock_kernel.h> |
22 | |
23 | #include "am65-cpts.h" |
24 | |
25 | struct am65_genf_regs { |
26 | u32 comp_lo; /* Comparison Low Value 0:31 */ |
27 | u32 comp_hi; /* Comparison High Value 32:63 */ |
28 | u32 control; /* control */ |
29 | u32 length; /* Length */ |
30 | u32 ppm_low; /* PPM Load Low Value 0:31 */ |
31 | u32 ppm_hi; /* PPM Load High Value 32:63 */ |
32 | u32 ts_nudge; /* Nudge value */ |
33 | } __aligned(32) __packed; |
34 | |
35 | #define AM65_CPTS_GENF_MAX_NUM 9 |
36 | #define AM65_CPTS_ESTF_MAX_NUM 8 |
37 | |
38 | struct am65_cpts_regs { |
39 | u32 idver; /* Identification and version */ |
40 | u32 control; /* Time sync control */ |
41 | u32 rftclk_sel; /* Reference Clock Select Register */ |
42 | u32 ts_push; /* Time stamp event push */ |
43 | u32 ts_load_val_lo; /* Time Stamp Load Low Value 0:31 */ |
44 | u32 ts_load_en; /* Time stamp load enable */ |
45 | u32 ts_comp_lo; /* Time Stamp Comparison Low Value 0:31 */ |
46 | u32 ts_comp_length; /* Time Stamp Comparison Length */ |
47 | u32 intstat_raw; /* Time sync interrupt status raw */ |
48 | u32 intstat_masked; /* Time sync interrupt status masked */ |
49 | u32 int_enable; /* Time sync interrupt enable */ |
50 | u32 ts_comp_nudge; /* Time Stamp Comparison Nudge Value */ |
51 | u32 event_pop; /* Event interrupt pop */ |
52 | u32 event_0; /* Event Time Stamp lo 0:31 */ |
53 | u32 event_1; /* Event Type Fields */ |
54 | u32 event_2; /* Event Type Fields domain */ |
55 | u32 event_3; /* Event Time Stamp hi 32:63 */ |
56 | u32 ts_load_val_hi; /* Time Stamp Load High Value 32:63 */ |
57 | u32 ts_comp_hi; /* Time Stamp Comparison High Value 32:63 */ |
58 | u32 ts_add_val; /* Time Stamp Add value */ |
59 | u32 ts_ppm_low; /* Time Stamp PPM Load Low Value 0:31 */ |
60 | u32 ts_ppm_hi; /* Time Stamp PPM Load High Value 32:63 */ |
61 | u32 ts_nudge; /* Time Stamp Nudge value */ |
62 | u32 reserv[33]; |
63 | struct am65_genf_regs genf[AM65_CPTS_GENF_MAX_NUM]; |
64 | struct am65_genf_regs estf[AM65_CPTS_ESTF_MAX_NUM]; |
65 | }; |
66 | |
67 | /* CONTROL_REG */ |
68 | #define AM65_CPTS_CONTROL_EN BIT(0) |
69 | #define AM65_CPTS_CONTROL_INT_TEST BIT(1) |
70 | #define AM65_CPTS_CONTROL_TS_COMP_POLARITY BIT(2) |
71 | #define AM65_CPTS_CONTROL_TSTAMP_EN BIT(3) |
72 | #define AM65_CPTS_CONTROL_SEQUENCE_EN BIT(4) |
73 | #define AM65_CPTS_CONTROL_64MODE BIT(5) |
74 | #define AM65_CPTS_CONTROL_TS_COMP_TOG BIT(6) |
75 | #define AM65_CPTS_CONTROL_TS_PPM_DIR BIT(7) |
76 | #define AM65_CPTS_CONTROL_HW1_TS_PUSH_EN BIT(8) |
77 | #define AM65_CPTS_CONTROL_HW2_TS_PUSH_EN BIT(9) |
78 | #define AM65_CPTS_CONTROL_HW3_TS_PUSH_EN BIT(10) |
79 | #define AM65_CPTS_CONTROL_HW4_TS_PUSH_EN BIT(11) |
80 | #define AM65_CPTS_CONTROL_HW5_TS_PUSH_EN BIT(12) |
81 | #define AM65_CPTS_CONTROL_HW6_TS_PUSH_EN BIT(13) |
82 | #define AM65_CPTS_CONTROL_HW7_TS_PUSH_EN BIT(14) |
83 | #define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15) |
84 | #define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8) |
85 | |
86 | #define AM65_CPTS_CONTROL_TX_GENF_CLR_EN BIT(17) |
87 | |
88 | #define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF) |
89 | #define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28) |
90 | |
91 | /* RFTCLK_SEL_REG */ |
92 | #define AM65_CPTS_RFTCLK_SEL_MASK (0x1F) |
93 | |
94 | /* TS_PUSH_REG */ |
95 | #define AM65_CPTS_TS_PUSH BIT(0) |
96 | |
97 | /* TS_LOAD_EN_REG */ |
98 | #define AM65_CPTS_TS_LOAD_EN BIT(0) |
99 | |
100 | /* INTSTAT_RAW_REG */ |
101 | #define AM65_CPTS_INTSTAT_RAW_TS_PEND BIT(0) |
102 | |
103 | /* INTSTAT_MASKED_REG */ |
104 | #define AM65_CPTS_INTSTAT_MASKED_TS_PEND BIT(0) |
105 | |
106 | /* INT_ENABLE_REG */ |
107 | #define AM65_CPTS_INT_ENABLE_TS_PEND_EN BIT(0) |
108 | |
109 | /* TS_COMP_NUDGE_REG */ |
110 | #define AM65_CPTS_TS_COMP_NUDGE_MASK (0xFF) |
111 | |
112 | /* EVENT_POP_REG */ |
113 | #define AM65_CPTS_EVENT_POP BIT(0) |
114 | |
115 | /* EVENT_1_REG */ |
116 | #define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0) |
117 | |
118 | #define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16) |
119 | #define AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT (16) |
120 | |
121 | #define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20) |
122 | #define AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT (20) |
123 | |
124 | #define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24) |
125 | #define AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT (24) |
126 | |
127 | /* EVENT_2_REG */ |
128 | #define AM65_CPTS_EVENT_2_REG_DOMAIN_MASK (0xFF) |
129 | #define AM65_CPTS_EVENT_2_REG_DOMAIN_SHIFT (0) |
130 | |
131 | enum { |
132 | AM65_CPTS_EV_PUSH, /* Time Stamp Push Event */ |
133 | AM65_CPTS_EV_ROLL, /* Time Stamp Rollover Event */ |
134 | AM65_CPTS_EV_HALF, /* Time Stamp Half Rollover Event */ |
135 | AM65_CPTS_EV_HW, /* Hardware Time Stamp Push Event */ |
136 | AM65_CPTS_EV_RX, /* Ethernet Receive Event */ |
137 | AM65_CPTS_EV_TX, /* Ethernet Transmit Event */ |
138 | AM65_CPTS_EV_TS_COMP, /* Time Stamp Compare Event */ |
139 | AM65_CPTS_EV_HOST, /* Host Transmit Event */ |
140 | }; |
141 | |
142 | struct am65_cpts_event { |
143 | struct list_head list; |
144 | unsigned long tmo; |
145 | u32 event1; |
146 | u32 event2; |
147 | u64 timestamp; |
148 | }; |
149 | |
150 | #define AM65_CPTS_FIFO_DEPTH (16) |
151 | #define AM65_CPTS_MAX_EVENTS (32) |
152 | #define AM65_CPTS_EVENT_RX_TX_TIMEOUT (20) /* ms */ |
153 | #define AM65_CPTS_SKB_TX_WORK_TIMEOUT 1 /* jiffies */ |
154 | #define AM65_CPTS_MIN_PPM 0x400 |
155 | |
156 | struct am65_cpts { |
157 | struct device *dev; |
158 | struct am65_cpts_regs __iomem *reg; |
159 | struct ptp_clock_info ptp_info; |
160 | struct ptp_clock *ptp_clock; |
161 | int phc_index; |
162 | struct clk_hw *clk_mux_hw; |
163 | struct device_node *clk_mux_np; |
164 | struct clk *refclk; |
165 | u32 refclk_freq; |
166 | struct list_head events; |
167 | struct list_head pool; |
168 | struct am65_cpts_event pool_data[AM65_CPTS_MAX_EVENTS]; |
169 | spinlock_t lock; /* protects events lists*/ |
170 | u32 ext_ts_inputs; |
171 | u32 genf_num; |
172 | u32 ts_add_val; |
173 | int irq; |
174 | struct mutex ptp_clk_lock; /* PHC access sync */ |
175 | u64 timestamp; |
176 | u32 genf_enable; |
177 | u32 hw_ts_enable; |
178 | u32 estf_enable; |
179 | struct sk_buff_head txq; |
180 | bool pps_enabled; |
181 | bool pps_present; |
182 | u32 pps_hw_ts_idx; |
183 | u32 pps_genf_idx; |
184 | /* context save/restore */ |
185 | u64 sr_cpts_ns; |
186 | u64 sr_ktime_ns; |
187 | u32 sr_control; |
188 | u32 sr_int_enable; |
189 | u32 sr_rftclk_sel; |
190 | u32 sr_ts_ppm_hi; |
191 | u32 sr_ts_ppm_low; |
192 | struct am65_genf_regs sr_genf[AM65_CPTS_GENF_MAX_NUM]; |
193 | struct am65_genf_regs sr_estf[AM65_CPTS_ESTF_MAX_NUM]; |
194 | }; |
195 | |
196 | struct am65_cpts_skb_cb_data { |
197 | unsigned long tmo; |
198 | u32 skb_mtype_seqid; |
199 | }; |
200 | |
201 | #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r) |
202 | #define am65_cpts_read32(c, r) readl(&(c)->reg->r) |
203 | |
204 | static void am65_cpts_settime(struct am65_cpts *cpts, u64 start_tstamp) |
205 | { |
206 | u32 val; |
207 | |
208 | val = upper_32_bits(start_tstamp); |
209 | am65_cpts_write32(cpts, val, ts_load_val_hi); |
210 | val = lower_32_bits(start_tstamp); |
211 | am65_cpts_write32(cpts, val, ts_load_val_lo); |
212 | |
213 | am65_cpts_write32(cpts, AM65_CPTS_TS_LOAD_EN, ts_load_en); |
214 | } |
215 | |
216 | static void am65_cpts_set_add_val(struct am65_cpts *cpts) |
217 | { |
218 | /* select coefficient according to the rate */ |
219 | cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; |
220 | |
221 | am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); |
222 | } |
223 | |
224 | static void am65_cpts_disable(struct am65_cpts *cpts) |
225 | { |
226 | am65_cpts_write32(cpts, 0, control); |
227 | am65_cpts_write32(cpts, 0, int_enable); |
228 | } |
229 | |
230 | static int am65_cpts_event_get_port(struct am65_cpts_event *event) |
231 | { |
232 | return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >> |
233 | AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT; |
234 | } |
235 | |
236 | static int am65_cpts_event_get_type(struct am65_cpts_event *event) |
237 | { |
238 | return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >> |
239 | AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT; |
240 | } |
241 | |
242 | static int am65_cpts_cpts_purge_events(struct am65_cpts *cpts) |
243 | { |
244 | struct list_head *this, *next; |
245 | struct am65_cpts_event *event; |
246 | int removed = 0; |
247 | |
248 | list_for_each_safe(this, next, &cpts->events) { |
249 | event = list_entry(this, struct am65_cpts_event, list); |
250 | if (time_after(jiffies, event->tmo)) { |
251 | list_del_init(entry: &event->list); |
252 | list_add(new: &event->list, head: &cpts->pool); |
253 | ++removed; |
254 | } |
255 | } |
256 | |
257 | if (removed) |
258 | dev_dbg(cpts->dev, "event pool cleaned up %d\n" , removed); |
259 | return removed ? 0 : -1; |
260 | } |
261 | |
262 | static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts, |
263 | struct am65_cpts_event *event) |
264 | { |
265 | u32 r = am65_cpts_read32(cpts, intstat_raw); |
266 | |
267 | if (r & AM65_CPTS_INTSTAT_RAW_TS_PEND) { |
268 | event->timestamp = am65_cpts_read32(cpts, event_0); |
269 | event->event1 = am65_cpts_read32(cpts, event_1); |
270 | event->event2 = am65_cpts_read32(cpts, event_2); |
271 | event->timestamp |= (u64)am65_cpts_read32(cpts, event_3) << 32; |
272 | am65_cpts_write32(cpts, AM65_CPTS_EVENT_POP, event_pop); |
273 | return false; |
274 | } |
275 | return true; |
276 | } |
277 | |
278 | static int am65_cpts_fifo_read(struct am65_cpts *cpts) |
279 | { |
280 | struct ptp_clock_event pevent; |
281 | struct am65_cpts_event *event; |
282 | bool schedule = false; |
283 | int i, type, ret = 0; |
284 | unsigned long flags; |
285 | |
286 | spin_lock_irqsave(&cpts->lock, flags); |
287 | for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) { |
288 | event = list_first_entry_or_null(&cpts->pool, |
289 | struct am65_cpts_event, list); |
290 | |
291 | if (!event) { |
292 | if (am65_cpts_cpts_purge_events(cpts)) { |
293 | dev_err(cpts->dev, "cpts: event pool empty\n" ); |
294 | ret = -1; |
295 | goto out; |
296 | } |
297 | continue; |
298 | } |
299 | |
300 | if (am65_cpts_fifo_pop_event(cpts, event)) |
301 | break; |
302 | |
303 | type = am65_cpts_event_get_type(event); |
304 | switch (type) { |
305 | case AM65_CPTS_EV_PUSH: |
306 | cpts->timestamp = event->timestamp; |
307 | dev_dbg(cpts->dev, "AM65_CPTS_EV_PUSH t:%llu\n" , |
308 | cpts->timestamp); |
309 | break; |
310 | case AM65_CPTS_EV_RX: |
311 | case AM65_CPTS_EV_TX: |
312 | event->tmo = jiffies + |
313 | msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT); |
314 | |
315 | list_del_init(entry: &event->list); |
316 | list_add_tail(new: &event->list, head: &cpts->events); |
317 | |
318 | dev_dbg(cpts->dev, |
319 | "AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n" , |
320 | event->event1, event->event2, |
321 | event->timestamp); |
322 | schedule = true; |
323 | break; |
324 | case AM65_CPTS_EV_HW: |
325 | pevent.index = am65_cpts_event_get_port(event) - 1; |
326 | pevent.timestamp = event->timestamp; |
327 | if (cpts->pps_enabled && pevent.index == cpts->pps_hw_ts_idx) { |
328 | pevent.type = PTP_CLOCK_PPSUSR; |
329 | pevent.pps_times.ts_real = ns_to_timespec64(nsec: pevent.timestamp); |
330 | } else { |
331 | pevent.type = PTP_CLOCK_EXTTS; |
332 | } |
333 | dev_dbg(cpts->dev, "AM65_CPTS_EV_HW:%s p:%d t:%llu\n" , |
334 | pevent.type == PTP_CLOCK_EXTTS ? |
335 | "extts" : "pps" , |
336 | pevent.index, event->timestamp); |
337 | |
338 | ptp_clock_event(ptp: cpts->ptp_clock, event: &pevent); |
339 | break; |
340 | case AM65_CPTS_EV_HOST: |
341 | break; |
342 | case AM65_CPTS_EV_ROLL: |
343 | case AM65_CPTS_EV_HALF: |
344 | case AM65_CPTS_EV_TS_COMP: |
345 | dev_dbg(cpts->dev, |
346 | "AM65_CPTS_EVT: %d e1:%08x e2:%08x t:%lld\n" , |
347 | type, |
348 | event->event1, event->event2, |
349 | event->timestamp); |
350 | break; |
351 | default: |
352 | dev_err(cpts->dev, "cpts: unknown event type\n" ); |
353 | ret = -1; |
354 | goto out; |
355 | } |
356 | } |
357 | |
358 | out: |
359 | spin_unlock_irqrestore(lock: &cpts->lock, flags); |
360 | |
361 | if (schedule) |
362 | ptp_schedule_worker(ptp: cpts->ptp_clock, delay: 0); |
363 | |
364 | return ret; |
365 | } |
366 | |
367 | static u64 am65_cpts_gettime(struct am65_cpts *cpts, |
368 | struct ptp_system_timestamp *sts) |
369 | { |
370 | unsigned long flags; |
371 | u64 val = 0; |
372 | |
373 | /* temporarily disable cpts interrupt to avoid intentional |
374 | * doubled read. Interrupt can be in-flight - it's Ok. |
375 | */ |
376 | am65_cpts_write32(cpts, 0, int_enable); |
377 | |
378 | /* use spin_lock_irqsave() here as it has to run very fast */ |
379 | spin_lock_irqsave(&cpts->lock, flags); |
380 | ptp_read_system_prets(sts); |
381 | am65_cpts_write32(cpts, AM65_CPTS_TS_PUSH, ts_push); |
382 | am65_cpts_read32(cpts, ts_push); |
383 | ptp_read_system_postts(sts); |
384 | spin_unlock_irqrestore(lock: &cpts->lock, flags); |
385 | |
386 | am65_cpts_fifo_read(cpts); |
387 | |
388 | am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable); |
389 | |
390 | val = cpts->timestamp; |
391 | |
392 | return val; |
393 | } |
394 | |
395 | static irqreturn_t am65_cpts_interrupt(int irq, void *dev_id) |
396 | { |
397 | struct am65_cpts *cpts = dev_id; |
398 | |
399 | if (am65_cpts_fifo_read(cpts)) |
400 | dev_dbg(cpts->dev, "cpts: unable to obtain a time stamp\n" ); |
401 | |
402 | return IRQ_HANDLED; |
403 | } |
404 | |
405 | /* PTP clock operations */ |
406 | static int am65_cpts_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) |
407 | { |
408 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
409 | u32 estf_ctrl_val = 0, estf_ppm_hi = 0, estf_ppm_low = 0; |
410 | s32 ppb = scaled_ppm_to_ppb(ppm: scaled_ppm); |
411 | int pps_index = cpts->pps_genf_idx; |
412 | u64 adj_period, pps_adj_period; |
413 | u32 ctrl_val, ppm_hi, ppm_low; |
414 | unsigned long flags; |
415 | int neg_adj = 0, i; |
416 | |
417 | if (ppb < 0) { |
418 | neg_adj = 1; |
419 | ppb = -ppb; |
420 | } |
421 | |
422 | /* base freq = 1GHz = 1 000 000 000 |
423 | * ppb_norm = ppb * base_freq / clock_freq; |
424 | * ppm_norm = ppb_norm / 1000 |
425 | * adj_period = 1 000 000 / ppm_norm |
426 | * adj_period = 1 000 000 000 / ppb_norm |
427 | * adj_period = 1 000 000 000 / (ppb * base_freq / clock_freq) |
428 | * adj_period = (1 000 000 000 * clock_freq) / (ppb * base_freq) |
429 | * adj_period = clock_freq / ppb |
430 | */ |
431 | adj_period = div_u64(dividend: cpts->refclk_freq, divisor: ppb); |
432 | |
433 | mutex_lock(&cpts->ptp_clk_lock); |
434 | |
435 | ctrl_val = am65_cpts_read32(cpts, control); |
436 | if (neg_adj) |
437 | ctrl_val |= AM65_CPTS_CONTROL_TS_PPM_DIR; |
438 | else |
439 | ctrl_val &= ~AM65_CPTS_CONTROL_TS_PPM_DIR; |
440 | |
441 | ppm_hi = upper_32_bits(adj_period) & 0x3FF; |
442 | ppm_low = lower_32_bits(adj_period); |
443 | |
444 | if (cpts->pps_enabled) { |
445 | estf_ctrl_val = am65_cpts_read32(cpts, genf[pps_index].control); |
446 | if (neg_adj) |
447 | estf_ctrl_val &= ~BIT(1); |
448 | else |
449 | estf_ctrl_val |= BIT(1); |
450 | |
451 | /* GenF PPM will do correction using cpts refclk tick which is |
452 | * (cpts->ts_add_val + 1) ns, so GenF length PPM adj period |
453 | * need to be corrected. |
454 | */ |
455 | pps_adj_period = adj_period * (cpts->ts_add_val + 1); |
456 | estf_ppm_hi = upper_32_bits(pps_adj_period) & 0x3FF; |
457 | estf_ppm_low = lower_32_bits(pps_adj_period); |
458 | } |
459 | |
460 | spin_lock_irqsave(&cpts->lock, flags); |
461 | |
462 | /* All below writes must be done extremely fast: |
463 | * - delay between PPM dir and PPM value changes can cause err due old |
464 | * PPM correction applied in wrong direction |
465 | * - delay between CPTS-clock PPM cfg and GenF PPM cfg can cause err |
466 | * due CPTS-clock PPM working with new cfg while GenF PPM cfg still |
467 | * with old for short period of time |
468 | */ |
469 | |
470 | am65_cpts_write32(cpts, ctrl_val, control); |
471 | am65_cpts_write32(cpts, ppm_hi, ts_ppm_hi); |
472 | am65_cpts_write32(cpts, ppm_low, ts_ppm_low); |
473 | |
474 | if (cpts->pps_enabled) { |
475 | am65_cpts_write32(cpts, estf_ctrl_val, genf[pps_index].control); |
476 | am65_cpts_write32(cpts, estf_ppm_hi, genf[pps_index].ppm_hi); |
477 | am65_cpts_write32(cpts, estf_ppm_low, genf[pps_index].ppm_low); |
478 | } |
479 | |
480 | for (i = 0; i < AM65_CPTS_ESTF_MAX_NUM; i++) { |
481 | if (cpts->estf_enable & BIT(i)) { |
482 | am65_cpts_write32(cpts, estf_ctrl_val, estf[i].control); |
483 | am65_cpts_write32(cpts, estf_ppm_hi, estf[i].ppm_hi); |
484 | am65_cpts_write32(cpts, estf_ppm_low, estf[i].ppm_low); |
485 | } |
486 | } |
487 | /* All GenF/EstF can be updated here the same way */ |
488 | spin_unlock_irqrestore(lock: &cpts->lock, flags); |
489 | |
490 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
491 | |
492 | return 0; |
493 | } |
494 | |
495 | static int am65_cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) |
496 | { |
497 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
498 | s64 ns; |
499 | |
500 | mutex_lock(&cpts->ptp_clk_lock); |
501 | ns = am65_cpts_gettime(cpts, NULL); |
502 | ns += delta; |
503 | am65_cpts_settime(cpts, start_tstamp: ns); |
504 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
505 | |
506 | return 0; |
507 | } |
508 | |
509 | static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp, |
510 | struct timespec64 *ts, |
511 | struct ptp_system_timestamp *sts) |
512 | { |
513 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
514 | u64 ns; |
515 | |
516 | mutex_lock(&cpts->ptp_clk_lock); |
517 | ns = am65_cpts_gettime(cpts, sts); |
518 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
519 | *ts = ns_to_timespec64(nsec: ns); |
520 | |
521 | return 0; |
522 | } |
523 | |
524 | u64 am65_cpts_ns_gettime(struct am65_cpts *cpts) |
525 | { |
526 | u64 ns; |
527 | |
528 | /* reuse ptp_clk_lock as it serialize ts push */ |
529 | mutex_lock(&cpts->ptp_clk_lock); |
530 | ns = am65_cpts_gettime(cpts, NULL); |
531 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
532 | |
533 | return ns; |
534 | } |
535 | EXPORT_SYMBOL_GPL(am65_cpts_ns_gettime); |
536 | |
537 | static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp, |
538 | const struct timespec64 *ts) |
539 | { |
540 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
541 | u64 ns; |
542 | |
543 | ns = timespec64_to_ns(ts); |
544 | mutex_lock(&cpts->ptp_clk_lock); |
545 | am65_cpts_settime(cpts, start_tstamp: ns); |
546 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
547 | |
548 | return 0; |
549 | } |
550 | |
551 | static void am65_cpts_extts_enable_hw(struct am65_cpts *cpts, u32 index, int on) |
552 | { |
553 | u32 v; |
554 | |
555 | v = am65_cpts_read32(cpts, control); |
556 | if (on) { |
557 | v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index); |
558 | cpts->hw_ts_enable |= BIT(index); |
559 | } else { |
560 | v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index); |
561 | cpts->hw_ts_enable &= ~BIT(index); |
562 | } |
563 | am65_cpts_write32(cpts, v, control); |
564 | } |
565 | |
566 | static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on) |
567 | { |
568 | if (index >= cpts->ptp_info.n_ext_ts) |
569 | return -ENXIO; |
570 | |
571 | if (cpts->pps_present && index == cpts->pps_hw_ts_idx) |
572 | return -EINVAL; |
573 | |
574 | if (((cpts->hw_ts_enable & BIT(index)) >> index) == on) |
575 | return 0; |
576 | |
577 | mutex_lock(&cpts->ptp_clk_lock); |
578 | am65_cpts_extts_enable_hw(cpts, index, on); |
579 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
580 | |
581 | dev_dbg(cpts->dev, "%s: ExtTS:%u %s\n" , |
582 | __func__, index, on ? "enabled" : "disabled" ); |
583 | |
584 | return 0; |
585 | } |
586 | |
587 | int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx, |
588 | struct am65_cpts_estf_cfg *cfg) |
589 | { |
590 | u64 cycles; |
591 | u32 val; |
592 | |
593 | cycles = cfg->ns_period * cpts->refclk_freq; |
594 | cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC); |
595 | if (cycles > U32_MAX) |
596 | return -EINVAL; |
597 | |
598 | /* according to TRM should be zeroed */ |
599 | am65_cpts_write32(cpts, 0, estf[idx].length); |
600 | |
601 | val = upper_32_bits(cfg->ns_start); |
602 | am65_cpts_write32(cpts, val, estf[idx].comp_hi); |
603 | val = lower_32_bits(cfg->ns_start); |
604 | am65_cpts_write32(cpts, val, estf[idx].comp_lo); |
605 | val = lower_32_bits(cycles); |
606 | am65_cpts_write32(cpts, val, estf[idx].length); |
607 | am65_cpts_write32(cpts, 0, estf[idx].control); |
608 | am65_cpts_write32(cpts, 0, estf[idx].ppm_hi); |
609 | am65_cpts_write32(cpts, 0, estf[idx].ppm_low); |
610 | |
611 | cpts->estf_enable |= BIT(idx); |
612 | |
613 | dev_dbg(cpts->dev, "%s: ESTF:%u enabled\n" , __func__, idx); |
614 | |
615 | return 0; |
616 | } |
617 | EXPORT_SYMBOL_GPL(am65_cpts_estf_enable); |
618 | |
619 | void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx) |
620 | { |
621 | am65_cpts_write32(cpts, 0, estf[idx].length); |
622 | cpts->estf_enable &= ~BIT(idx); |
623 | |
624 | dev_dbg(cpts->dev, "%s: ESTF:%u disabled\n" , __func__, idx); |
625 | } |
626 | EXPORT_SYMBOL_GPL(am65_cpts_estf_disable); |
627 | |
628 | static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts, |
629 | struct ptp_perout_request *req, int on) |
630 | { |
631 | u64 ns_period, ns_start, cycles; |
632 | struct timespec64 ts; |
633 | u32 val; |
634 | |
635 | if (on) { |
636 | ts.tv_sec = req->period.sec; |
637 | ts.tv_nsec = req->period.nsec; |
638 | ns_period = timespec64_to_ns(ts: &ts); |
639 | |
640 | cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC; |
641 | |
642 | ts.tv_sec = req->start.sec; |
643 | ts.tv_nsec = req->start.nsec; |
644 | ns_start = timespec64_to_ns(ts: &ts); |
645 | |
646 | val = upper_32_bits(ns_start); |
647 | am65_cpts_write32(cpts, val, genf[req->index].comp_hi); |
648 | val = lower_32_bits(ns_start); |
649 | am65_cpts_write32(cpts, val, genf[req->index].comp_lo); |
650 | val = lower_32_bits(cycles); |
651 | am65_cpts_write32(cpts, val, genf[req->index].length); |
652 | |
653 | am65_cpts_write32(cpts, 0, genf[req->index].control); |
654 | am65_cpts_write32(cpts, 0, genf[req->index].ppm_hi); |
655 | am65_cpts_write32(cpts, 0, genf[req->index].ppm_low); |
656 | |
657 | cpts->genf_enable |= BIT(req->index); |
658 | } else { |
659 | am65_cpts_write32(cpts, 0, genf[req->index].length); |
660 | |
661 | cpts->genf_enable &= ~BIT(req->index); |
662 | } |
663 | } |
664 | |
665 | static int am65_cpts_perout_enable(struct am65_cpts *cpts, |
666 | struct ptp_perout_request *req, int on) |
667 | { |
668 | if (req->index >= cpts->ptp_info.n_per_out) |
669 | return -ENXIO; |
670 | |
671 | if (cpts->pps_present && req->index == cpts->pps_genf_idx) |
672 | return -EINVAL; |
673 | |
674 | if (!!(cpts->genf_enable & BIT(req->index)) == !!on) |
675 | return 0; |
676 | |
677 | mutex_lock(&cpts->ptp_clk_lock); |
678 | am65_cpts_perout_enable_hw(cpts, req, on); |
679 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
680 | |
681 | dev_dbg(cpts->dev, "%s: GenF:%u %s\n" , |
682 | __func__, req->index, on ? "enabled" : "disabled" ); |
683 | |
684 | return 0; |
685 | } |
686 | |
687 | static int am65_cpts_pps_enable(struct am65_cpts *cpts, int on) |
688 | { |
689 | int ret = 0; |
690 | struct timespec64 ts; |
691 | struct ptp_clock_request rq; |
692 | u64 ns; |
693 | |
694 | if (!cpts->pps_present) |
695 | return -EINVAL; |
696 | |
697 | if (cpts->pps_enabled == !!on) |
698 | return 0; |
699 | |
700 | mutex_lock(&cpts->ptp_clk_lock); |
701 | |
702 | if (on) { |
703 | am65_cpts_extts_enable_hw(cpts, index: cpts->pps_hw_ts_idx, on); |
704 | |
705 | ns = am65_cpts_gettime(cpts, NULL); |
706 | ts = ns_to_timespec64(nsec: ns); |
707 | rq.perout.period.sec = 1; |
708 | rq.perout.period.nsec = 0; |
709 | rq.perout.start.sec = ts.tv_sec + 2; |
710 | rq.perout.start.nsec = 0; |
711 | rq.perout.index = cpts->pps_genf_idx; |
712 | |
713 | am65_cpts_perout_enable_hw(cpts, req: &rq.perout, on); |
714 | cpts->pps_enabled = true; |
715 | } else { |
716 | rq.perout.index = cpts->pps_genf_idx; |
717 | am65_cpts_perout_enable_hw(cpts, req: &rq.perout, on); |
718 | am65_cpts_extts_enable_hw(cpts, index: cpts->pps_hw_ts_idx, on); |
719 | cpts->pps_enabled = false; |
720 | } |
721 | |
722 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
723 | |
724 | dev_dbg(cpts->dev, "%s: pps: %s\n" , |
725 | __func__, on ? "enabled" : "disabled" ); |
726 | return ret; |
727 | } |
728 | |
729 | static int am65_cpts_ptp_enable(struct ptp_clock_info *ptp, |
730 | struct ptp_clock_request *rq, int on) |
731 | { |
732 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
733 | |
734 | switch (rq->type) { |
735 | case PTP_CLK_REQ_EXTTS: |
736 | return am65_cpts_extts_enable(cpts, index: rq->extts.index, on); |
737 | case PTP_CLK_REQ_PEROUT: |
738 | return am65_cpts_perout_enable(cpts, req: &rq->perout, on); |
739 | case PTP_CLK_REQ_PPS: |
740 | return am65_cpts_pps_enable(cpts, on); |
741 | default: |
742 | break; |
743 | } |
744 | |
745 | return -EOPNOTSUPP; |
746 | } |
747 | |
748 | static long am65_cpts_ts_work(struct ptp_clock_info *ptp); |
749 | |
750 | static struct ptp_clock_info am65_ptp_info = { |
751 | .owner = THIS_MODULE, |
752 | .name = "CTPS timer" , |
753 | .adjfine = am65_cpts_ptp_adjfine, |
754 | .adjtime = am65_cpts_ptp_adjtime, |
755 | .gettimex64 = am65_cpts_ptp_gettimex, |
756 | .settime64 = am65_cpts_ptp_settime, |
757 | .enable = am65_cpts_ptp_enable, |
758 | .do_aux_work = am65_cpts_ts_work, |
759 | }; |
760 | |
761 | static bool am65_cpts_match_tx_ts(struct am65_cpts *cpts, |
762 | struct am65_cpts_event *event) |
763 | { |
764 | struct sk_buff_head txq_list; |
765 | struct sk_buff *skb, *tmp; |
766 | unsigned long flags; |
767 | bool found = false; |
768 | u32 mtype_seqid; |
769 | |
770 | mtype_seqid = event->event1 & |
771 | (AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK | |
772 | AM65_CPTS_EVENT_1_EVENT_TYPE_MASK | |
773 | AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK); |
774 | |
775 | __skb_queue_head_init(list: &txq_list); |
776 | |
777 | spin_lock_irqsave(&cpts->txq.lock, flags); |
778 | skb_queue_splice_init(list: &cpts->txq, head: &txq_list); |
779 | spin_unlock_irqrestore(lock: &cpts->txq.lock, flags); |
780 | |
781 | /* no need to grab txq.lock as access is always done under cpts->lock */ |
782 | skb_queue_walk_safe(&txq_list, skb, tmp) { |
783 | struct skb_shared_hwtstamps ssh; |
784 | struct am65_cpts_skb_cb_data *skb_cb = |
785 | (struct am65_cpts_skb_cb_data *)skb->cb; |
786 | |
787 | if (mtype_seqid == skb_cb->skb_mtype_seqid) { |
788 | u64 ns = event->timestamp; |
789 | |
790 | memset(&ssh, 0, sizeof(ssh)); |
791 | ssh.hwtstamp = ns_to_ktime(ns); |
792 | skb_tstamp_tx(orig_skb: skb, hwtstamps: &ssh); |
793 | found = true; |
794 | __skb_unlink(skb, list: &txq_list); |
795 | dev_consume_skb_any(skb); |
796 | dev_dbg(cpts->dev, |
797 | "match tx timestamp mtype_seqid %08x\n" , |
798 | mtype_seqid); |
799 | break; |
800 | } |
801 | |
802 | if (time_after(jiffies, skb_cb->tmo)) { |
803 | /* timeout any expired skbs over 100 ms */ |
804 | dev_dbg(cpts->dev, |
805 | "expiring tx timestamp mtype_seqid %08x\n" , |
806 | mtype_seqid); |
807 | __skb_unlink(skb, list: &txq_list); |
808 | dev_consume_skb_any(skb); |
809 | } |
810 | } |
811 | |
812 | spin_lock_irqsave(&cpts->txq.lock, flags); |
813 | skb_queue_splice(list: &txq_list, head: &cpts->txq); |
814 | spin_unlock_irqrestore(lock: &cpts->txq.lock, flags); |
815 | |
816 | return found; |
817 | } |
818 | |
819 | static void am65_cpts_find_ts(struct am65_cpts *cpts) |
820 | { |
821 | struct am65_cpts_event *event; |
822 | struct list_head *this, *next; |
823 | LIST_HEAD(events_free); |
824 | unsigned long flags; |
825 | LIST_HEAD(events); |
826 | |
827 | spin_lock_irqsave(&cpts->lock, flags); |
828 | list_splice_init(list: &cpts->events, head: &events); |
829 | spin_unlock_irqrestore(lock: &cpts->lock, flags); |
830 | |
831 | list_for_each_safe(this, next, &events) { |
832 | event = list_entry(this, struct am65_cpts_event, list); |
833 | if (am65_cpts_match_tx_ts(cpts, event) || |
834 | time_after(jiffies, event->tmo)) { |
835 | list_del_init(entry: &event->list); |
836 | list_add(new: &event->list, head: &events_free); |
837 | } |
838 | } |
839 | |
840 | spin_lock_irqsave(&cpts->lock, flags); |
841 | list_splice_tail(list: &events, head: &cpts->events); |
842 | list_splice_tail(list: &events_free, head: &cpts->pool); |
843 | spin_unlock_irqrestore(lock: &cpts->lock, flags); |
844 | } |
845 | |
846 | static long am65_cpts_ts_work(struct ptp_clock_info *ptp) |
847 | { |
848 | struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info); |
849 | unsigned long flags; |
850 | long delay = -1; |
851 | |
852 | am65_cpts_find_ts(cpts); |
853 | |
854 | spin_lock_irqsave(&cpts->txq.lock, flags); |
855 | if (!skb_queue_empty(list: &cpts->txq)) |
856 | delay = AM65_CPTS_SKB_TX_WORK_TIMEOUT; |
857 | spin_unlock_irqrestore(lock: &cpts->txq.lock, flags); |
858 | |
859 | return delay; |
860 | } |
861 | |
862 | /** |
863 | * am65_cpts_rx_enable - enable rx timestamping |
864 | * @cpts: cpts handle |
865 | * @en: enable |
866 | * |
867 | * This functions enables rx packets timestamping. The CPTS can timestamp all |
868 | * rx packets. |
869 | */ |
870 | void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en) |
871 | { |
872 | u32 val; |
873 | |
874 | mutex_lock(&cpts->ptp_clk_lock); |
875 | val = am65_cpts_read32(cpts, control); |
876 | if (en) |
877 | val |= AM65_CPTS_CONTROL_TSTAMP_EN; |
878 | else |
879 | val &= ~AM65_CPTS_CONTROL_TSTAMP_EN; |
880 | am65_cpts_write32(cpts, val, control); |
881 | mutex_unlock(lock: &cpts->ptp_clk_lock); |
882 | } |
883 | EXPORT_SYMBOL_GPL(am65_cpts_rx_enable); |
884 | |
885 | static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid) |
886 | { |
887 | unsigned int ptp_class = ptp_classify_raw(skb); |
888 | struct ptp_header *hdr; |
889 | u8 msgtype; |
890 | u16 seqid; |
891 | |
892 | if (ptp_class == PTP_CLASS_NONE) |
893 | return 0; |
894 | |
895 | hdr = ptp_parse_header(skb, type: ptp_class); |
896 | if (!hdr) |
897 | return 0; |
898 | |
899 | msgtype = ptp_get_msgtype(hdr, type: ptp_class); |
900 | seqid = ntohs(hdr->sequence_id); |
901 | |
902 | *mtype_seqid = (msgtype << AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT) & |
903 | AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK; |
904 | *mtype_seqid |= (seqid & AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK); |
905 | |
906 | return 1; |
907 | } |
908 | |
909 | /** |
910 | * am65_cpts_tx_timestamp - save tx packet for timestamping |
911 | * @cpts: cpts handle |
912 | * @skb: packet |
913 | * |
914 | * This functions saves tx packet for timestamping if packet can be timestamped. |
915 | * The future processing is done in from PTP auxiliary worker. |
916 | */ |
917 | void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb) |
918 | { |
919 | struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb; |
920 | |
921 | if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
922 | return; |
923 | |
924 | /* add frame to queue for processing later. |
925 | * The periodic FIFO check will handle this. |
926 | */ |
927 | skb_get(skb); |
928 | /* get the timestamp for timeouts */ |
929 | skb_cb->tmo = jiffies + msecs_to_jiffies(m: 100); |
930 | skb_queue_tail(list: &cpts->txq, newsk: skb); |
931 | ptp_schedule_worker(ptp: cpts->ptp_clock, delay: 0); |
932 | } |
933 | EXPORT_SYMBOL_GPL(am65_cpts_tx_timestamp); |
934 | |
935 | /** |
936 | * am65_cpts_prep_tx_timestamp - check and prepare tx packet for timestamping |
937 | * @cpts: cpts handle |
938 | * @skb: packet |
939 | * |
940 | * This functions should be called from .xmit(). |
941 | * It checks if packet can be timestamped, fills internal cpts data |
942 | * in skb-cb and marks packet as SKBTX_IN_PROGRESS. |
943 | */ |
944 | void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb) |
945 | { |
946 | struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb; |
947 | int ret; |
948 | |
949 | if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) |
950 | return; |
951 | |
952 | ret = am65_skb_get_mtype_seqid(skb, mtype_seqid: &skb_cb->skb_mtype_seqid); |
953 | if (!ret) |
954 | return; |
955 | skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_TX << |
956 | AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT); |
957 | |
958 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
959 | } |
960 | EXPORT_SYMBOL_GPL(am65_cpts_prep_tx_timestamp); |
961 | |
962 | int am65_cpts_phc_index(struct am65_cpts *cpts) |
963 | { |
964 | return cpts->phc_index; |
965 | } |
966 | EXPORT_SYMBOL_GPL(am65_cpts_phc_index); |
967 | |
968 | static void cpts_free_clk_mux(void *data) |
969 | { |
970 | struct am65_cpts *cpts = data; |
971 | |
972 | of_clk_del_provider(np: cpts->clk_mux_np); |
973 | clk_hw_unregister_mux(hw: cpts->clk_mux_hw); |
974 | of_node_put(node: cpts->clk_mux_np); |
975 | } |
976 | |
977 | static int cpts_of_mux_clk_setup(struct am65_cpts *cpts, |
978 | struct device_node *node) |
979 | { |
980 | unsigned int num_parents; |
981 | const char **parent_names; |
982 | char *clk_mux_name; |
983 | void __iomem *reg; |
984 | int ret = -EINVAL; |
985 | |
986 | cpts->clk_mux_np = of_get_child_by_name(node, name: "refclk-mux" ); |
987 | if (!cpts->clk_mux_np) |
988 | return 0; |
989 | |
990 | num_parents = of_clk_get_parent_count(np: cpts->clk_mux_np); |
991 | if (num_parents < 1) { |
992 | dev_err(cpts->dev, "mux-clock %pOF must have parents\n" , |
993 | cpts->clk_mux_np); |
994 | goto mux_fail; |
995 | } |
996 | |
997 | parent_names = devm_kcalloc(dev: cpts->dev, n: sizeof(char *), size: num_parents, |
998 | GFP_KERNEL); |
999 | if (!parent_names) { |
1000 | ret = -ENOMEM; |
1001 | goto mux_fail; |
1002 | } |
1003 | |
1004 | of_clk_parent_fill(np: cpts->clk_mux_np, parents: parent_names, size: num_parents); |
1005 | |
1006 | clk_mux_name = devm_kasprintf(dev: cpts->dev, GFP_KERNEL, fmt: "%s.%pOFn" , |
1007 | dev_name(dev: cpts->dev), cpts->clk_mux_np); |
1008 | if (!clk_mux_name) { |
1009 | ret = -ENOMEM; |
1010 | goto mux_fail; |
1011 | } |
1012 | |
1013 | reg = &cpts->reg->rftclk_sel; |
1014 | /* dev must be NULL to avoid recursive incrementing |
1015 | * of module refcnt |
1016 | */ |
1017 | cpts->clk_mux_hw = clk_hw_register_mux(NULL, clk_mux_name, |
1018 | parent_names, num_parents, |
1019 | 0, reg, 0, 5, 0, NULL); |
1020 | if (IS_ERR(ptr: cpts->clk_mux_hw)) { |
1021 | ret = PTR_ERR(ptr: cpts->clk_mux_hw); |
1022 | goto mux_fail; |
1023 | } |
1024 | |
1025 | ret = of_clk_add_hw_provider(np: cpts->clk_mux_np, get: of_clk_hw_simple_get, |
1026 | data: cpts->clk_mux_hw); |
1027 | if (ret) |
1028 | goto clk_hw_register; |
1029 | |
1030 | ret = devm_add_action_or_reset(cpts->dev, cpts_free_clk_mux, cpts); |
1031 | if (ret) |
1032 | dev_err(cpts->dev, "failed to add clkmux reset action %d" , ret); |
1033 | |
1034 | return ret; |
1035 | |
1036 | clk_hw_register: |
1037 | clk_hw_unregister_mux(hw: cpts->clk_mux_hw); |
1038 | mux_fail: |
1039 | of_node_put(node: cpts->clk_mux_np); |
1040 | return ret; |
1041 | } |
1042 | |
1043 | static int am65_cpts_of_parse(struct am65_cpts *cpts, struct device_node *node) |
1044 | { |
1045 | u32 prop[2]; |
1046 | |
1047 | if (!of_property_read_u32(np: node, propname: "ti,cpts-ext-ts-inputs" , out_value: &prop[0])) |
1048 | cpts->ext_ts_inputs = prop[0]; |
1049 | |
1050 | if (!of_property_read_u32(np: node, propname: "ti,cpts-periodic-outputs" , out_value: &prop[0])) |
1051 | cpts->genf_num = prop[0]; |
1052 | |
1053 | if (!of_property_read_u32_array(np: node, propname: "ti,pps" , out_values: prop, sz: 2)) { |
1054 | cpts->pps_present = true; |
1055 | |
1056 | if (prop[0] > 7) { |
1057 | dev_err(cpts->dev, "invalid HWx_TS_PUSH index: %u provided\n" , prop[0]); |
1058 | cpts->pps_present = false; |
1059 | } |
1060 | if (prop[1] > 1) { |
1061 | dev_err(cpts->dev, "invalid GENFy index: %u provided\n" , prop[1]); |
1062 | cpts->pps_present = false; |
1063 | } |
1064 | if (cpts->pps_present) { |
1065 | cpts->pps_hw_ts_idx = prop[0]; |
1066 | cpts->pps_genf_idx = prop[1]; |
1067 | } |
1068 | } |
1069 | |
1070 | return cpts_of_mux_clk_setup(cpts, node); |
1071 | } |
1072 | |
1073 | void am65_cpts_release(struct am65_cpts *cpts) |
1074 | { |
1075 | ptp_clock_unregister(ptp: cpts->ptp_clock); |
1076 | am65_cpts_disable(cpts); |
1077 | clk_disable_unprepare(clk: cpts->refclk); |
1078 | } |
1079 | EXPORT_SYMBOL_GPL(am65_cpts_release); |
1080 | |
1081 | struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs, |
1082 | struct device_node *node) |
1083 | { |
1084 | struct am65_cpts *cpts; |
1085 | int ret, i; |
1086 | |
1087 | cpts = devm_kzalloc(dev, size: sizeof(*cpts), GFP_KERNEL); |
1088 | if (!cpts) |
1089 | return ERR_PTR(error: -ENOMEM); |
1090 | |
1091 | cpts->dev = dev; |
1092 | cpts->reg = (struct am65_cpts_regs __iomem *)regs; |
1093 | |
1094 | cpts->irq = of_irq_get_byname(dev: node, name: "cpts" ); |
1095 | if (cpts->irq <= 0) { |
1096 | ret = cpts->irq ?: -ENXIO; |
1097 | dev_err_probe(dev, err: ret, fmt: "Failed to get IRQ number\n" ); |
1098 | return ERR_PTR(error: ret); |
1099 | } |
1100 | |
1101 | ret = am65_cpts_of_parse(cpts, node); |
1102 | if (ret) |
1103 | return ERR_PTR(error: ret); |
1104 | |
1105 | mutex_init(&cpts->ptp_clk_lock); |
1106 | INIT_LIST_HEAD(list: &cpts->events); |
1107 | INIT_LIST_HEAD(list: &cpts->pool); |
1108 | spin_lock_init(&cpts->lock); |
1109 | skb_queue_head_init(list: &cpts->txq); |
1110 | |
1111 | for (i = 0; i < AM65_CPTS_MAX_EVENTS; i++) |
1112 | list_add(new: &cpts->pool_data[i].list, head: &cpts->pool); |
1113 | |
1114 | cpts->refclk = devm_get_clk_from_child(dev, np: node, con_id: "cpts" ); |
1115 | if (IS_ERR(ptr: cpts->refclk)) { |
1116 | ret = PTR_ERR(ptr: cpts->refclk); |
1117 | dev_err_probe(dev, err: ret, fmt: "Failed to get refclk\n" ); |
1118 | return ERR_PTR(error: ret); |
1119 | } |
1120 | |
1121 | ret = clk_prepare_enable(clk: cpts->refclk); |
1122 | if (ret) { |
1123 | dev_err(dev, "Failed to enable refclk %d\n" , ret); |
1124 | return ERR_PTR(error: ret); |
1125 | } |
1126 | |
1127 | cpts->refclk_freq = clk_get_rate(clk: cpts->refclk); |
1128 | |
1129 | am65_ptp_info.max_adj = cpts->refclk_freq / AM65_CPTS_MIN_PPM; |
1130 | cpts->ptp_info = am65_ptp_info; |
1131 | |
1132 | if (cpts->ext_ts_inputs) |
1133 | cpts->ptp_info.n_ext_ts = cpts->ext_ts_inputs; |
1134 | if (cpts->genf_num) |
1135 | cpts->ptp_info.n_per_out = cpts->genf_num; |
1136 | if (cpts->pps_present) |
1137 | cpts->ptp_info.pps = 1; |
1138 | |
1139 | am65_cpts_set_add_val(cpts); |
1140 | |
1141 | am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN | |
1142 | AM65_CPTS_CONTROL_64MODE | |
1143 | AM65_CPTS_CONTROL_TX_GENF_CLR_EN, |
1144 | control); |
1145 | am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable); |
1146 | |
1147 | /* set time to the current system time */ |
1148 | am65_cpts_settime(cpts, start_tstamp: ktime_to_ns(kt: ktime_get_real())); |
1149 | |
1150 | cpts->ptp_clock = ptp_clock_register(info: &cpts->ptp_info, parent: cpts->dev); |
1151 | if (IS_ERR_OR_NULL(ptr: cpts->ptp_clock)) { |
1152 | dev_err(dev, "Failed to register ptp clk %ld\n" , |
1153 | PTR_ERR(cpts->ptp_clock)); |
1154 | ret = cpts->ptp_clock ? PTR_ERR(ptr: cpts->ptp_clock) : -ENODEV; |
1155 | goto refclk_disable; |
1156 | } |
1157 | cpts->phc_index = ptp_clock_index(ptp: cpts->ptp_clock); |
1158 | |
1159 | ret = devm_request_threaded_irq(dev, irq: cpts->irq, NULL, |
1160 | thread_fn: am65_cpts_interrupt, |
1161 | IRQF_ONESHOT, devname: dev_name(dev), dev_id: cpts); |
1162 | if (ret < 0) { |
1163 | dev_err(cpts->dev, "error attaching irq %d\n" , ret); |
1164 | goto reset_ptpclk; |
1165 | } |
1166 | |
1167 | dev_info(dev, "CPTS ver 0x%08x, freq:%u, add_val:%u pps:%d\n" , |
1168 | am65_cpts_read32(cpts, idver), |
1169 | cpts->refclk_freq, cpts->ts_add_val, cpts->pps_present); |
1170 | |
1171 | return cpts; |
1172 | |
1173 | reset_ptpclk: |
1174 | am65_cpts_release(cpts); |
1175 | refclk_disable: |
1176 | clk_disable_unprepare(clk: cpts->refclk); |
1177 | return ERR_PTR(error: ret); |
1178 | } |
1179 | EXPORT_SYMBOL_GPL(am65_cpts_create); |
1180 | |
1181 | void am65_cpts_suspend(struct am65_cpts *cpts) |
1182 | { |
1183 | /* save state and disable CPTS */ |
1184 | cpts->sr_control = am65_cpts_read32(cpts, control); |
1185 | cpts->sr_int_enable = am65_cpts_read32(cpts, int_enable); |
1186 | cpts->sr_rftclk_sel = am65_cpts_read32(cpts, rftclk_sel); |
1187 | cpts->sr_ts_ppm_hi = am65_cpts_read32(cpts, ts_ppm_hi); |
1188 | cpts->sr_ts_ppm_low = am65_cpts_read32(cpts, ts_ppm_low); |
1189 | cpts->sr_cpts_ns = am65_cpts_gettime(cpts, NULL); |
1190 | cpts->sr_ktime_ns = ktime_to_ns(kt: ktime_get_real()); |
1191 | am65_cpts_disable(cpts); |
1192 | clk_disable(clk: cpts->refclk); |
1193 | |
1194 | /* Save GENF state */ |
1195 | memcpy_fromio(&cpts->sr_genf, &cpts->reg->genf, sizeof(cpts->sr_genf)); |
1196 | |
1197 | /* Save ESTF state */ |
1198 | memcpy_fromio(&cpts->sr_estf, &cpts->reg->estf, sizeof(cpts->sr_estf)); |
1199 | } |
1200 | EXPORT_SYMBOL_GPL(am65_cpts_suspend); |
1201 | |
1202 | void am65_cpts_resume(struct am65_cpts *cpts) |
1203 | { |
1204 | int i; |
1205 | s64 ktime_ns; |
1206 | |
1207 | /* restore state and enable CPTS */ |
1208 | clk_enable(clk: cpts->refclk); |
1209 | am65_cpts_write32(cpts, cpts->sr_rftclk_sel, rftclk_sel); |
1210 | am65_cpts_set_add_val(cpts); |
1211 | am65_cpts_write32(cpts, cpts->sr_control, control); |
1212 | am65_cpts_write32(cpts, cpts->sr_int_enable, int_enable); |
1213 | |
1214 | /* Restore time to saved CPTS time + time in suspend/resume */ |
1215 | ktime_ns = ktime_to_ns(kt: ktime_get_real()); |
1216 | ktime_ns -= cpts->sr_ktime_ns; |
1217 | am65_cpts_settime(cpts, start_tstamp: cpts->sr_cpts_ns + ktime_ns); |
1218 | |
1219 | /* Restore compensation (PPM) */ |
1220 | am65_cpts_write32(cpts, cpts->sr_ts_ppm_hi, ts_ppm_hi); |
1221 | am65_cpts_write32(cpts, cpts->sr_ts_ppm_low, ts_ppm_low); |
1222 | |
1223 | /* Restore GENF state */ |
1224 | for (i = 0; i < AM65_CPTS_GENF_MAX_NUM; i++) { |
1225 | am65_cpts_write32(cpts, 0, genf[i].length); /* TRM sequence */ |
1226 | am65_cpts_write32(cpts, cpts->sr_genf[i].comp_hi, genf[i].comp_hi); |
1227 | am65_cpts_write32(cpts, cpts->sr_genf[i].comp_lo, genf[i].comp_lo); |
1228 | am65_cpts_write32(cpts, cpts->sr_genf[i].length, genf[i].length); |
1229 | am65_cpts_write32(cpts, cpts->sr_genf[i].control, genf[i].control); |
1230 | am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_hi, genf[i].ppm_hi); |
1231 | am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_low, genf[i].ppm_low); |
1232 | } |
1233 | |
1234 | /* Restore ESTTF state */ |
1235 | for (i = 0; i < AM65_CPTS_ESTF_MAX_NUM; i++) { |
1236 | am65_cpts_write32(cpts, 0, estf[i].length); /* TRM sequence */ |
1237 | am65_cpts_write32(cpts, cpts->sr_estf[i].comp_hi, estf[i].comp_hi); |
1238 | am65_cpts_write32(cpts, cpts->sr_estf[i].comp_lo, estf[i].comp_lo); |
1239 | am65_cpts_write32(cpts, cpts->sr_estf[i].length, estf[i].length); |
1240 | am65_cpts_write32(cpts, cpts->sr_estf[i].control, estf[i].control); |
1241 | am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_hi, estf[i].ppm_hi); |
1242 | am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_low, estf[i].ppm_low); |
1243 | } |
1244 | } |
1245 | EXPORT_SYMBOL_GPL(am65_cpts_resume); |
1246 | |
1247 | static int am65_cpts_probe(struct platform_device *pdev) |
1248 | { |
1249 | struct device_node *node = pdev->dev.of_node; |
1250 | struct device *dev = &pdev->dev; |
1251 | struct am65_cpts *cpts; |
1252 | void __iomem *base; |
1253 | |
1254 | base = devm_platform_ioremap_resource_byname(pdev, name: "cpts" ); |
1255 | if (IS_ERR(ptr: base)) |
1256 | return PTR_ERR(ptr: base); |
1257 | |
1258 | cpts = am65_cpts_create(dev, base, node); |
1259 | return PTR_ERR_OR_ZERO(ptr: cpts); |
1260 | } |
1261 | |
1262 | static const struct of_device_id am65_cpts_of_match[] = { |
1263 | { .compatible = "ti,am65-cpts" , }, |
1264 | { .compatible = "ti,j721e-cpts" , }, |
1265 | {}, |
1266 | }; |
1267 | MODULE_DEVICE_TABLE(of, am65_cpts_of_match); |
1268 | |
1269 | static struct platform_driver am65_cpts_driver = { |
1270 | .probe = am65_cpts_probe, |
1271 | .driver = { |
1272 | .name = "am65-cpts" , |
1273 | .of_match_table = am65_cpts_of_match, |
1274 | }, |
1275 | }; |
1276 | module_platform_driver(am65_cpts_driver); |
1277 | |
1278 | MODULE_LICENSE("GPL v2" ); |
1279 | MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>" ); |
1280 | MODULE_DESCRIPTION("TI K3 AM65 CPTS driver" ); |
1281 | |