1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | |
3 | /* PRU-ICSS MII_RT register definitions |
4 | * |
5 | * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com |
6 | */ |
7 | |
8 | #ifndef __NET_PRUSS_MII_RT_H__ |
9 | #define __NET_PRUSS_MII_RT_H__ |
10 | |
11 | #include <linux/if_ether.h> |
12 | #include <linux/phy.h> |
13 | |
14 | /* PRUSS_MII_RT Registers */ |
15 | #define PRUSS_MII_RT_RXCFG0 0x0 |
16 | #define PRUSS_MII_RT_RXCFG1 0x4 |
17 | #define PRUSS_MII_RT_TXCFG0 0x10 |
18 | #define PRUSS_MII_RT_TXCFG1 0x14 |
19 | #define PRUSS_MII_RT_TX_CRC0 0x20 |
20 | #define PRUSS_MII_RT_TX_CRC1 0x24 |
21 | #define PRUSS_MII_RT_TX_IPG0 0x30 |
22 | #define PRUSS_MII_RT_TX_IPG1 0x34 |
23 | #define PRUSS_MII_RT_PRS0 0x38 |
24 | #define PRUSS_MII_RT_PRS1 0x3c |
25 | #define PRUSS_MII_RT_RX_FRMS0 0x40 |
26 | #define PRUSS_MII_RT_RX_FRMS1 0x44 |
27 | #define PRUSS_MII_RT_RX_PCNT0 0x48 |
28 | #define PRUSS_MII_RT_RX_PCNT1 0x4c |
29 | #define PRUSS_MII_RT_RX_ERR0 0x50 |
30 | #define PRUSS_MII_RT_RX_ERR1 0x54 |
31 | |
32 | /* PRUSS_MII_RT_RXCFG0/1 bits */ |
33 | #define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) |
34 | #define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS BIT(1) |
35 | #define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) |
36 | #define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) |
37 | #define PRUSS_MII_RT_RXCFG_RX_L2_EN BIT(4) |
38 | #define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAP BIT(5) |
39 | #define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) |
40 | #define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) |
41 | |
42 | /* PRUSS_MII_RT_TXCFG0/1 bits */ |
43 | #define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) |
44 | #define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE BIT(1) |
45 | #define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) |
46 | #define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAP BIT(3) |
47 | #define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) |
48 | #define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCE BIT(9) |
49 | #define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) |
50 | #define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) |
51 | #define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ |
52 | |
53 | #define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT 16 |
54 | #define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) |
55 | |
56 | #define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 |
57 | #define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) |
58 | |
59 | /* PRUSS_MII_RT_TX_IPG0/1 bits */ |
60 | #define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 |
61 | #define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) |
62 | |
63 | /* PRUSS_MII_RT_PRS0/1 bits */ |
64 | #define PRUSS_MII_RT_PRS_COL BIT(0) |
65 | #define PRUSS_MII_RT_PRS_CRS BIT(1) |
66 | |
67 | /* PRUSS_MII_RT_RX_FRMS0/1 bits */ |
68 | #define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 |
69 | #define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) |
70 | |
71 | #define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 |
72 | #define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) |
73 | |
74 | /* Min/Max in MII_RT_RX_FRMS */ |
75 | /* For EMAC and Switch */ |
76 | #define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) |
77 | #define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) |
78 | |
79 | /* for HSR and PRP */ |
80 | #define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ |
81 | ICSS_LRE_TAG_RCT_SIZE) |
82 | /* PRUSS_MII_RT_RX_PCNT0/1 bits */ |
83 | #define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT 0 |
84 | #define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) |
85 | |
86 | #define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT 4 |
87 | #define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) |
88 | |
89 | /* PRUSS_MII_RT_RX_ERR0/1 bits */ |
90 | #define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) |
91 | #define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) |
92 | #define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERR BIT(2) |
93 | #define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERR BIT(3) |
94 | |
95 | #define ICSSG_CFG_OFFSET 0 |
96 | #define RGMII_CFG_OFFSET 4 |
97 | |
98 | /* Constant to choose between MII0 and MII1 */ |
99 | #define ICSS_MII0 0 |
100 | #define ICSS_MII1 1 |
101 | |
102 | /* ICSSG_CFG Register bits */ |
103 | #define ICSSG_CFG_SGMII_MODE BIT(16) |
104 | #define ICSSG_CFG_TX_PRU_EN BIT(11) |
105 | #define ICSSG_CFG_RX_SFD_TX_SOF_EN BIT(10) |
106 | #define ICSSG_CFG_RTU_PRU_PSI_SHARE_EN BIT(9) |
107 | #define ICSSG_CFG_IEP1_TX_EN BIT(8) |
108 | #define ICSSG_CFG_MII1_MODE GENMASK(6, 5) |
109 | #define ICSSG_CFG_MII1_MODE_SHIFT 5 |
110 | #define ICSSG_CFG_MII0_MODE GENMASK(4, 3) |
111 | #define ICSSG_CFG_MII0_MODE_SHIFT 3 |
112 | #define ICSSG_CFG_RX_L2_G_EN BIT(2) |
113 | #define ICSSG_CFG_TX_L2_EN BIT(1) |
114 | #define ICSSG_CFG_TX_L1_EN BIT(0) |
115 | |
116 | enum mii_mode { |
117 | MII_MODE_MII = 0, |
118 | MII_MODE_RGMII |
119 | }; |
120 | |
121 | /* RGMII CFG Register bits */ |
122 | #define RGMII_CFG_INBAND_EN_MII0 BIT(16) |
123 | #define RGMII_CFG_GIG_EN_MII0 BIT(17) |
124 | #define RGMII_CFG_INBAND_EN_MII1 BIT(20) |
125 | #define RGMII_CFG_GIG_EN_MII1 BIT(21) |
126 | #define RGMII_CFG_FULL_DUPLEX_MII0 BIT(18) |
127 | #define RGMII_CFG_FULL_DUPLEX_MII1 BIT(22) |
128 | #define RGMII_CFG_SPEED_MII0 GENMASK(2, 1) |
129 | #define RGMII_CFG_SPEED_MII1 GENMASK(6, 5) |
130 | #define RGMII_CFG_SPEED_MII0_SHIFT 1 |
131 | #define RGMII_CFG_SPEED_MII1_SHIFT 5 |
132 | #define RGMII_CFG_FULLDUPLEX_MII0 BIT(3) |
133 | #define RGMII_CFG_FULLDUPLEX_MII1 BIT(7) |
134 | #define RGMII_CFG_FULLDUPLEX_MII0_SHIFT 3 |
135 | #define RGMII_CFG_FULLDUPLEX_MII1_SHIFT 7 |
136 | #define RGMII_CFG_SPEED_10M 0 |
137 | #define RGMII_CFG_SPEED_100M 1 |
138 | #define RGMII_CFG_SPEED_1G 2 |
139 | |
140 | struct regmap; |
141 | struct prueth_emac; |
142 | |
143 | void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg); |
144 | void icssg_mii_update_mtu(struct regmap *mii_rt, int mii, int mtu); |
145 | void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac); |
146 | u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift); |
147 | u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii); |
148 | u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii); |
149 | void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if); |
150 | |
151 | #endif /* __NET_PRUSS_MII_RT_H__ */ |
152 | |