1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Driver for the Texas Instruments DP83TD510 PHY |
3 | * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> |
4 | */ |
5 | |
6 | #include <linux/bitfield.h> |
7 | #include <linux/kernel.h> |
8 | #include <linux/module.h> |
9 | #include <linux/phy.h> |
10 | |
11 | #define DP83TD510E_PHY_ID 0x20000181 |
12 | |
13 | /* MDIO_MMD_VEND2 registers */ |
14 | #define DP83TD510E_PHY_STS 0x10 |
15 | /* Bit 7 - mii_interrupt, active high. Clears on read. |
16 | * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending. |
17 | * This differs from the DP83TD510E datasheet (2020) which states this bit |
18 | * clears on write 0. |
19 | */ |
20 | #define DP83TD510E_STS_MII_INT BIT(7) |
21 | #define DP83TD510E_LINK_STATUS BIT(0) |
22 | |
23 | #define DP83TD510E_GEN_CFG 0x11 |
24 | #define DP83TD510E_GENCFG_INT_POLARITY BIT(3) |
25 | #define DP83TD510E_GENCFG_INT_EN BIT(1) |
26 | #define DP83TD510E_GENCFG_INT_OE BIT(0) |
27 | |
28 | #define DP83TD510E_INTERRUPT_REG_1 0x12 |
29 | #define DP83TD510E_INT1_LINK BIT(13) |
30 | #define DP83TD510E_INT1_LINK_EN BIT(5) |
31 | |
32 | #define DP83TD510E_AN_STAT_1 0x60c |
33 | #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15) |
34 | |
35 | #define DP83TD510E_MSE_DETECT 0xa85 |
36 | |
37 | #define DP83TD510_SQI_MAX 7 |
38 | |
39 | /* Register values are converted to SNR(dB) as suggested by |
40 | * "Application Report - DP83TD510E Cable Diagnostics Toolkit": |
41 | * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB. |
42 | * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic |
43 | * features for 100BASE-T1 automotive Ethernet PHYs" |
44 | */ |
45 | static const u16 dp83td510_mse_sqi_map[] = { |
46 | 0x0569, /* < 18dB */ |
47 | 0x044c, /* 18dB =< SNR < 19dB */ |
48 | 0x0369, /* 19dB =< SNR < 20dB */ |
49 | 0x02b6, /* 20dB =< SNR < 21dB */ |
50 | 0x0227, /* 21dB =< SNR < 22dB */ |
51 | 0x01b6, /* 22dB =< SNR < 23dB */ |
52 | 0x015b, /* 23dB =< SNR < 24dB */ |
53 | 0x0000 /* 24dB =< SNR */ |
54 | }; |
55 | |
56 | static int dp83td510_config_intr(struct phy_device *phydev) |
57 | { |
58 | int ret; |
59 | |
60 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
61 | ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, |
62 | DP83TD510E_INTERRUPT_REG_1, |
63 | DP83TD510E_INT1_LINK_EN); |
64 | if (ret) |
65 | return ret; |
66 | |
67 | ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, |
68 | DP83TD510E_GEN_CFG, |
69 | DP83TD510E_GENCFG_INT_POLARITY | |
70 | DP83TD510E_GENCFG_INT_EN | |
71 | DP83TD510E_GENCFG_INT_OE); |
72 | } else { |
73 | ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, |
74 | DP83TD510E_INTERRUPT_REG_1, val: 0x0); |
75 | if (ret) |
76 | return ret; |
77 | |
78 | ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, |
79 | DP83TD510E_GEN_CFG, |
80 | DP83TD510E_GENCFG_INT_EN); |
81 | if (ret) |
82 | return ret; |
83 | } |
84 | |
85 | return ret; |
86 | } |
87 | |
88 | static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev) |
89 | { |
90 | int ret; |
91 | |
92 | /* Read the current enabled interrupts */ |
93 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); |
94 | if (ret < 0) { |
95 | phy_error(phydev); |
96 | return IRQ_NONE; |
97 | } else if (!(ret & DP83TD510E_INT1_LINK_EN) || |
98 | !(ret & DP83TD510E_INT1_LINK)) { |
99 | return IRQ_NONE; |
100 | } |
101 | |
102 | phy_trigger_machine(phydev); |
103 | |
104 | return IRQ_HANDLED; |
105 | } |
106 | |
107 | static int dp83td510_read_status(struct phy_device *phydev) |
108 | { |
109 | u16 phy_sts; |
110 | int ret; |
111 | |
112 | phydev->speed = SPEED_UNKNOWN; |
113 | phydev->duplex = DUPLEX_UNKNOWN; |
114 | phydev->pause = 0; |
115 | phydev->asym_pause = 0; |
116 | linkmode_zero(dst: phydev->lp_advertising); |
117 | |
118 | phy_sts = phy_read(phydev, DP83TD510E_PHY_STS); |
119 | |
120 | phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS); |
121 | if (phydev->link) { |
122 | /* This PHY supports only one link mode: 10BaseT1L_Full */ |
123 | phydev->duplex = DUPLEX_FULL; |
124 | phydev->speed = SPEED_10; |
125 | |
126 | if (phydev->autoneg == AUTONEG_ENABLE) { |
127 | ret = genphy_c45_read_lpa(phydev); |
128 | if (ret) |
129 | return ret; |
130 | |
131 | phy_resolve_aneg_linkmode(phydev); |
132 | } |
133 | } |
134 | |
135 | if (phydev->autoneg == AUTONEG_ENABLE) { |
136 | ret = genphy_c45_baset1_read_status(phydev); |
137 | if (ret < 0) |
138 | return ret; |
139 | |
140 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, |
141 | DP83TD510E_AN_STAT_1); |
142 | if (ret < 0) |
143 | return ret; |
144 | |
145 | if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL) |
146 | phydev->master_slave_state = MASTER_SLAVE_STATE_ERR; |
147 | } else { |
148 | return genphy_c45_pma_baset1_read_master_slave(phydev); |
149 | } |
150 | |
151 | return 0; |
152 | } |
153 | |
154 | static int dp83td510_config_aneg(struct phy_device *phydev) |
155 | { |
156 | bool changed = false; |
157 | int ret; |
158 | |
159 | ret = genphy_c45_pma_baset1_setup_master_slave(phydev); |
160 | if (ret < 0) |
161 | return ret; |
162 | |
163 | if (phydev->autoneg == AUTONEG_DISABLE) |
164 | return genphy_c45_an_disable_aneg(phydev); |
165 | |
166 | ret = genphy_c45_an_config_aneg(phydev); |
167 | if (ret < 0) |
168 | return ret; |
169 | if (ret > 0) |
170 | changed = true; |
171 | |
172 | return genphy_c45_check_and_restart_aneg(phydev, restart: changed); |
173 | } |
174 | |
175 | static int dp83td510_get_sqi(struct phy_device *phydev) |
176 | { |
177 | int sqi, ret; |
178 | u16 mse_val; |
179 | |
180 | if (!phydev->link) |
181 | return 0; |
182 | |
183 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); |
184 | if (ret < 0) |
185 | return ret; |
186 | |
187 | mse_val = 0xFFFF & ret; |
188 | for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) { |
189 | if (mse_val >= dp83td510_mse_sqi_map[sqi]) |
190 | return sqi; |
191 | } |
192 | |
193 | return -EINVAL; |
194 | } |
195 | |
196 | static int dp83td510_get_sqi_max(struct phy_device *phydev) |
197 | { |
198 | return DP83TD510_SQI_MAX; |
199 | } |
200 | |
201 | static int dp83td510_get_features(struct phy_device *phydev) |
202 | { |
203 | /* This PHY can't respond on MDIO bus if no RMII clock is enabled. |
204 | * In case RMII mode is used (most meaningful mode for this PHY) and |
205 | * the PHY do not have own XTAL, and CLK providing MAC is not probed, |
206 | * we won't be able to read all needed ability registers. |
207 | * So provide it manually. |
208 | */ |
209 | |
210 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_Autoneg_BIT, addr: phydev->supported); |
211 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_Asym_Pause_BIT, addr: phydev->supported); |
212 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_Pause_BIT, addr: phydev->supported); |
213 | linkmode_set_bit(nr: ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, |
214 | addr: phydev->supported); |
215 | |
216 | return 0; |
217 | } |
218 | |
219 | static struct phy_driver dp83td510_driver[] = { |
220 | { |
221 | PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID), |
222 | .name = "TI DP83TD510E" , |
223 | |
224 | .config_aneg = dp83td510_config_aneg, |
225 | .read_status = dp83td510_read_status, |
226 | .get_features = dp83td510_get_features, |
227 | .config_intr = dp83td510_config_intr, |
228 | .handle_interrupt = dp83td510_handle_interrupt, |
229 | .get_sqi = dp83td510_get_sqi, |
230 | .get_sqi_max = dp83td510_get_sqi_max, |
231 | |
232 | .suspend = genphy_suspend, |
233 | .resume = genphy_resume, |
234 | } }; |
235 | module_phy_driver(dp83td510_driver); |
236 | |
237 | static struct mdio_device_id __maybe_unused dp83td510_tbl[] = { |
238 | { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) }, |
239 | { } |
240 | }; |
241 | MODULE_DEVICE_TABLE(mdio, dp83td510_tbl); |
242 | |
243 | MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver" ); |
244 | MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>" ); |
245 | MODULE_LICENSE("GPL v2" ); |
246 | |