1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | #include <linux/bitfield.h> |
3 | #include <linux/bitmap.h> |
4 | #include <linux/mfd/syscon.h> |
5 | #include <linux/module.h> |
6 | #include <linux/nvmem-consumer.h> |
7 | #include <linux/pinctrl/consumer.h> |
8 | #include <linux/phy.h> |
9 | #include <linux/regmap.h> |
10 | |
11 | #define MTK_GPHY_ID_MT7981 0x03a29461 |
12 | #define MTK_GPHY_ID_MT7988 0x03a29481 |
13 | |
14 | #define MTK_EXT_PAGE_ACCESS 0x1f |
15 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
16 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
17 | |
18 | #define MTK_PHY_LPI_REG_14 0x14 |
19 | #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) |
20 | |
21 | #define MTK_PHY_LPI_REG_1c 0x1c |
22 | #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) |
23 | |
24 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
25 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
26 | |
27 | #define ANALOG_INTERNAL_OPERATION_MAX_US 20 |
28 | #define TXRESERVE_MIN 0 |
29 | #define TXRESERVE_MAX 7 |
30 | |
31 | #define MTK_PHY_ANARG_RG 0x10 |
32 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
33 | |
34 | /* Registers on MDIO_MMD_VEND1 */ |
35 | #define MTK_PHY_TXVLD_DA_RG 0x12 |
36 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
37 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
38 | |
39 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 |
40 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
41 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
42 | |
43 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 |
44 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
45 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
46 | |
47 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 |
48 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
49 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
50 | |
51 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 |
52 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
53 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
54 | |
55 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 |
56 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
57 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
58 | |
59 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 |
60 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
61 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
62 | |
63 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 |
64 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
65 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
66 | |
67 | #define MTK_PHY_RXADC_CTRL_RG7 0xc6 |
68 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
69 | |
70 | #define MTK_PHY_RXADC_CTRL_RG9 0xc8 |
71 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
72 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
73 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
74 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
75 | |
76 | #define MTK_PHY_LDO_OUTPUT_V 0xd7 |
77 | |
78 | #define MTK_PHY_RG_ANA_CAL_RG0 0xdb |
79 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
80 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
81 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
82 | |
83 | #define MTK_PHY_RG_ANA_CAL_RG1 0xdc |
84 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
85 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
86 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
87 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
88 | |
89 | #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 |
90 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
91 | |
92 | #define MTK_PHY_RG_TX_FILTER 0xfe |
93 | |
94 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 |
95 | #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) |
96 | #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) |
97 | |
98 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 |
99 | #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) |
100 | |
101 | #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 |
102 | #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) |
103 | |
104 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 |
105 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
106 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
107 | |
108 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 |
109 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
110 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
111 | |
112 | #define MTK_PHY_RG_AD_CAL_COMP 0x17a |
113 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
114 | |
115 | #define MTK_PHY_RG_AD_CAL_CLK 0x17b |
116 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
117 | |
118 | #define MTK_PHY_RG_AD_CALIN 0x17c |
119 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
120 | |
121 | #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d |
122 | #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) |
123 | |
124 | #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e |
125 | #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) |
126 | |
127 | #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f |
128 | #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) |
129 | |
130 | #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 |
131 | #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) |
132 | |
133 | #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 |
134 | #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) |
135 | |
136 | #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 |
137 | #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) |
138 | |
139 | #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 |
140 | #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) |
141 | |
142 | #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 |
143 | #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) |
144 | |
145 | #define MTK_PHY_RG_DEV1E_REG19b 0x19b |
146 | #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) |
147 | |
148 | #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a |
149 | #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b |
150 | #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c |
151 | #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d |
152 | #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e |
153 | #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f |
154 | #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 |
155 | #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 |
156 | #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 |
157 | #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 |
158 | |
159 | #define MTK_PHY_RG_DEV1E_REG234 0x234 |
160 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
161 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
162 | #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) |
163 | |
164 | #define MTK_PHY_RG_LPF_CNT_VAL 0x235 |
165 | |
166 | #define MTK_PHY_RG_DEV1E_REG238 0x238 |
167 | #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) |
168 | #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) |
169 | |
170 | #define MTK_PHY_RG_DEV1E_REG239 0x239 |
171 | #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) |
172 | #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) |
173 | |
174 | #define MTK_PHY_RG_DEV1E_REG27C 0x27c |
175 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
176 | #define MTK_PHY_RG_DEV1E_REG27D 0x27d |
177 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
178 | |
179 | #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 |
180 | #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) |
181 | #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) |
182 | |
183 | #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 |
184 | #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) |
185 | #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) |
186 | #define MTK_PHY_LPI_TR_READY BIT(9) |
187 | #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) |
188 | |
189 | #define MTK_PHY_RG_DEV1E_REG323 0x323 |
190 | #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) |
191 | #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) |
192 | |
193 | #define MTK_PHY_RG_DEV1E_REG324 0x324 |
194 | #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) |
195 | #define MTK_PHY_SMI_DET_MAX_EN BIT(8) |
196 | |
197 | #define MTK_PHY_RG_DEV1E_REG326 0x326 |
198 | #define MTK_PHY_LPI_MODE_SD_ON BIT(0) |
199 | #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) |
200 | #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) |
201 | #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) |
202 | #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) |
203 | |
204 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 |
205 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 |
206 | |
207 | #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d |
208 | #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e |
209 | #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f |
210 | #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 |
211 | |
212 | /* Registers on MDIO_MMD_VEND2 */ |
213 | #define MTK_PHY_LED0_ON_CTRL 0x24 |
214 | #define MTK_PHY_LED1_ON_CTRL 0x26 |
215 | #define MTK_PHY_LED_ON_MASK GENMASK(6, 0) |
216 | #define MTK_PHY_LED_ON_LINK1000 BIT(0) |
217 | #define MTK_PHY_LED_ON_LINK100 BIT(1) |
218 | #define MTK_PHY_LED_ON_LINK10 BIT(2) |
219 | #define MTK_PHY_LED_ON_LINKDOWN BIT(3) |
220 | #define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ |
221 | #define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ |
222 | #define MTK_PHY_LED_ON_FORCE_ON BIT(6) |
223 | #define MTK_PHY_LED_ON_POLARITY BIT(14) |
224 | #define MTK_PHY_LED_ON_ENABLE BIT(15) |
225 | |
226 | #define MTK_PHY_LED0_BLINK_CTRL 0x25 |
227 | #define MTK_PHY_LED1_BLINK_CTRL 0x27 |
228 | #define MTK_PHY_LED_BLINK_1000TX BIT(0) |
229 | #define MTK_PHY_LED_BLINK_1000RX BIT(1) |
230 | #define MTK_PHY_LED_BLINK_100TX BIT(2) |
231 | #define MTK_PHY_LED_BLINK_100RX BIT(3) |
232 | #define MTK_PHY_LED_BLINK_10TX BIT(4) |
233 | #define MTK_PHY_LED_BLINK_10RX BIT(5) |
234 | #define MTK_PHY_LED_BLINK_COLLISION BIT(6) |
235 | #define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) |
236 | #define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) |
237 | #define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) |
238 | |
239 | #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) |
240 | |
241 | #define MTK_PHY_RG_BG_RASEL 0x115 |
242 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
243 | |
244 | /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ |
245 | #define RG_GPIO_MISC_TPBANK0 0x6f0 |
246 | #define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) |
247 | |
248 | /* These macro privides efuse parsing for internal phy. */ |
249 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
250 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
251 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
252 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
253 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
254 | |
255 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
256 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
257 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
258 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
259 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
260 | |
261 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
262 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
263 | |
264 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
265 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
266 | |
267 | enum { |
268 | NO_PAIR, |
269 | PAIR_A, |
270 | PAIR_B, |
271 | PAIR_C, |
272 | PAIR_D, |
273 | }; |
274 | |
275 | enum calibration_mode { |
276 | EFUSE_K, |
277 | SW_K |
278 | }; |
279 | |
280 | enum CAL_ITEM { |
281 | REXT, |
282 | TX_OFFSET, |
283 | TX_AMP, |
284 | TX_R50, |
285 | TX_VCM |
286 | }; |
287 | |
288 | enum CAL_MODE { |
289 | EFUSE_M, |
290 | SW_M |
291 | }; |
292 | |
293 | #define MTK_PHY_LED_STATE_FORCE_ON 0 |
294 | #define MTK_PHY_LED_STATE_FORCE_BLINK 1 |
295 | #define MTK_PHY_LED_STATE_NETDEV 2 |
296 | |
297 | struct mtk_socphy_priv { |
298 | unsigned long led_state; |
299 | }; |
300 | |
301 | struct mtk_socphy_shared { |
302 | u32 boottrap; |
303 | struct mtk_socphy_priv priv[4]; |
304 | }; |
305 | |
306 | static int mtk_socphy_read_page(struct phy_device *phydev) |
307 | { |
308 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
309 | } |
310 | |
311 | static int mtk_socphy_write_page(struct phy_device *phydev, int page) |
312 | { |
313 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, val: page); |
314 | } |
315 | |
316 | /* One calibration cycle consists of: |
317 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
318 | * until AD_CAL_COMP is ready to output calibration result. |
319 | * 2.Wait until DA_CAL_CLK is available. |
320 | * 3.Fetch AD_CAL_COMP_OUT. |
321 | */ |
322 | static int cal_cycle(struct phy_device *phydev, int devad, |
323 | u32 regnum, u16 mask, u16 cal_val) |
324 | { |
325 | int reg_val; |
326 | int ret; |
327 | |
328 | phy_modify_mmd(phydev, devad, regnum, |
329 | mask, set: cal_val); |
330 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
331 | MTK_PHY_DA_CALIN_FLAG); |
332 | |
333 | ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, |
334 | MTK_PHY_RG_AD_CAL_CLK, reg_val, |
335 | reg_val & MTK_PHY_DA_CAL_CLK, 500, |
336 | ANALOG_INTERNAL_OPERATION_MAX_US, false); |
337 | if (ret) { |
338 | phydev_err(phydev, "Calibration cycle timeout\n" ); |
339 | return ret; |
340 | } |
341 | |
342 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
343 | MTK_PHY_DA_CALIN_FLAG); |
344 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> |
345 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
346 | phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n" , cal_val, ret); |
347 | |
348 | return ret; |
349 | } |
350 | |
351 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
352 | { |
353 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
354 | MTK_PHY_RG_REXT_TRIM_MASK, set: buf[0] << 8); |
355 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, |
356 | MTK_PHY_RG_BG_RASEL_MASK, set: buf[1]); |
357 | |
358 | return 0; |
359 | } |
360 | |
361 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
362 | { |
363 | u16 rext_cal_val[2]; |
364 | |
365 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
366 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
367 | rext_fill_result(phydev, buf: rext_cal_val); |
368 | |
369 | return 0; |
370 | } |
371 | |
372 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
373 | { |
374 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
375 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, set: buf[0] << 8); |
376 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
377 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, set: buf[1]); |
378 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
379 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, set: buf[2] << 8); |
380 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
381 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, set: buf[3]); |
382 | |
383 | return 0; |
384 | } |
385 | |
386 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
387 | { |
388 | u16 tx_offset_cal_val[4]; |
389 | |
390 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
391 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
392 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
393 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
394 | |
395 | tx_offset_fill_result(phydev, buf: tx_offset_cal_val); |
396 | |
397 | return 0; |
398 | } |
399 | |
400 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
401 | { |
402 | int i; |
403 | int bias[16] = {}; |
404 | const int vals_9461[16] = { 7, 1, 4, 7, |
405 | 7, 1, 4, 7, |
406 | 7, 1, 4, 7, |
407 | 7, 1, 4, 7 }; |
408 | const int vals_9481[16] = { 10, 6, 6, 10, |
409 | 10, 6, 6, 10, |
410 | 10, 6, 6, 10, |
411 | 10, 6, 6, 10 }; |
412 | switch (phydev->drv->phy_id) { |
413 | case MTK_GPHY_ID_MT7981: |
414 | /* We add some calibration to efuse values |
415 | * due to board level influence. |
416 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
417 | */ |
418 | memcpy(bias, (const void *)vals_9461, sizeof(bias)); |
419 | break; |
420 | case MTK_GPHY_ID_MT7988: |
421 | memcpy(bias, (const void *)vals_9481, sizeof(bias)); |
422 | break; |
423 | } |
424 | |
425 | /* Prevent overflow */ |
426 | for (i = 0; i < 12; i++) { |
427 | if (buf[i >> 2] + bias[i] > 63) { |
428 | buf[i >> 2] = 63; |
429 | bias[i] = 0; |
430 | } |
431 | } |
432 | |
433 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
434 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, set: (buf[0] + bias[0]) << 10); |
435 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
436 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, set: buf[0] + bias[1]); |
437 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
438 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, set: (buf[0] + bias[2]) << 10); |
439 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
440 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, set: buf[0] + bias[3]); |
441 | |
442 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
443 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, set: (buf[1] + bias[4]) << 8); |
444 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
445 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, set: buf[1] + bias[5]); |
446 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
447 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, set: (buf[1] + bias[6]) << 8); |
448 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
449 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, set: buf[1] + bias[7]); |
450 | |
451 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
452 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, set: (buf[2] + bias[8]) << 8); |
453 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
454 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, set: buf[2] + bias[9]); |
455 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
456 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, set: (buf[2] + bias[10]) << 8); |
457 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
458 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, set: buf[2] + bias[11]); |
459 | |
460 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
461 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, set: (buf[3] + bias[12]) << 8); |
462 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
463 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, set: buf[3] + bias[13]); |
464 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
465 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, set: (buf[3] + bias[14]) << 8); |
466 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
467 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, set: buf[3] + bias[15]); |
468 | |
469 | return 0; |
470 | } |
471 | |
472 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
473 | { |
474 | u16 tx_amp_cal_val[4]; |
475 | |
476 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
477 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
478 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
479 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
480 | tx_amp_fill_result(phydev, buf: tx_amp_cal_val); |
481 | |
482 | return 0; |
483 | } |
484 | |
485 | static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, |
486 | u8 txg_calen_x) |
487 | { |
488 | int bias = 0; |
489 | u16 reg, val; |
490 | |
491 | if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) |
492 | bias = -1; |
493 | |
494 | val = clamp_val(bias + tx_r50_cal_val, 0, 63); |
495 | |
496 | switch (txg_calen_x) { |
497 | case PAIR_A: |
498 | reg = MTK_PHY_DA_TX_R50_PAIR_A; |
499 | break; |
500 | case PAIR_B: |
501 | reg = MTK_PHY_DA_TX_R50_PAIR_B; |
502 | break; |
503 | case PAIR_C: |
504 | reg = MTK_PHY_DA_TX_R50_PAIR_C; |
505 | break; |
506 | case PAIR_D: |
507 | reg = MTK_PHY_DA_TX_R50_PAIR_D; |
508 | break; |
509 | default: |
510 | return -EINVAL; |
511 | } |
512 | |
513 | phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: reg, val: val | val << 8); |
514 | |
515 | return 0; |
516 | } |
517 | |
518 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
519 | u8 txg_calen_x) |
520 | { |
521 | u16 tx_r50_cal_val; |
522 | |
523 | switch (txg_calen_x) { |
524 | case PAIR_A: |
525 | tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); |
526 | break; |
527 | case PAIR_B: |
528 | tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); |
529 | break; |
530 | case PAIR_C: |
531 | tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); |
532 | break; |
533 | case PAIR_D: |
534 | tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); |
535 | break; |
536 | default: |
537 | return -EINVAL; |
538 | } |
539 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
540 | |
541 | return 0; |
542 | } |
543 | |
544 | static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) |
545 | { |
546 | u8 lower_idx, upper_idx, txreserve_val; |
547 | u8 lower_ret, upper_ret; |
548 | int ret; |
549 | |
550 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
551 | MTK_PHY_RG_ANA_CALEN); |
552 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
553 | MTK_PHY_RG_CAL_CKINV); |
554 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
555 | MTK_PHY_RG_TXVOS_CALEN); |
556 | |
557 | switch (rg_txreserve_x) { |
558 | case PAIR_A: |
559 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
560 | MTK_PHY_RG_DASN_DAC_IN0_A, |
561 | MTK_PHY_DASN_DAC_IN0_A_MASK); |
562 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
563 | MTK_PHY_RG_DASN_DAC_IN1_A, |
564 | MTK_PHY_DASN_DAC_IN1_A_MASK); |
565 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
566 | MTK_PHY_RG_ANA_CAL_RG0, |
567 | MTK_PHY_RG_ZCALEN_A); |
568 | break; |
569 | case PAIR_B: |
570 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
571 | MTK_PHY_RG_DASN_DAC_IN0_B, |
572 | MTK_PHY_DASN_DAC_IN0_B_MASK); |
573 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
574 | MTK_PHY_RG_DASN_DAC_IN1_B, |
575 | MTK_PHY_DASN_DAC_IN1_B_MASK); |
576 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
577 | MTK_PHY_RG_ANA_CAL_RG1, |
578 | MTK_PHY_RG_ZCALEN_B); |
579 | break; |
580 | case PAIR_C: |
581 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
582 | MTK_PHY_RG_DASN_DAC_IN0_C, |
583 | MTK_PHY_DASN_DAC_IN0_C_MASK); |
584 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
585 | MTK_PHY_RG_DASN_DAC_IN1_C, |
586 | MTK_PHY_DASN_DAC_IN1_C_MASK); |
587 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
588 | MTK_PHY_RG_ANA_CAL_RG1, |
589 | MTK_PHY_RG_ZCALEN_C); |
590 | break; |
591 | case PAIR_D: |
592 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
593 | MTK_PHY_RG_DASN_DAC_IN0_D, |
594 | MTK_PHY_DASN_DAC_IN0_D_MASK); |
595 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
596 | MTK_PHY_RG_DASN_DAC_IN1_D, |
597 | MTK_PHY_DASN_DAC_IN1_D_MASK); |
598 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
599 | MTK_PHY_RG_ANA_CAL_RG1, |
600 | MTK_PHY_RG_ZCALEN_D); |
601 | break; |
602 | default: |
603 | ret = -EINVAL; |
604 | goto restore; |
605 | } |
606 | |
607 | lower_idx = TXRESERVE_MIN; |
608 | upper_idx = TXRESERVE_MAX; |
609 | |
610 | phydev_dbg(phydev, "Start TX-VCM SW cal.\n" ); |
611 | while ((upper_idx - lower_idx) > 1) { |
612 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); |
613 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
614 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
615 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
616 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
617 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
618 | cal_val: txreserve_val << 12 | txreserve_val << 8 | |
619 | txreserve_val << 4 | txreserve_val); |
620 | if (ret == 1) { |
621 | upper_idx = txreserve_val; |
622 | upper_ret = ret; |
623 | } else if (ret == 0) { |
624 | lower_idx = txreserve_val; |
625 | lower_ret = ret; |
626 | } else { |
627 | goto restore; |
628 | } |
629 | } |
630 | |
631 | if (lower_idx == TXRESERVE_MIN) { |
632 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
633 | MTK_PHY_RXADC_CTRL_RG9, |
634 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
635 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
636 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
637 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
638 | cal_val: lower_idx << 12 | lower_idx << 8 | |
639 | lower_idx << 4 | lower_idx); |
640 | ret = lower_ret; |
641 | } else if (upper_idx == TXRESERVE_MAX) { |
642 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
643 | MTK_PHY_RXADC_CTRL_RG9, |
644 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
645 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
646 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
647 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
648 | cal_val: upper_idx << 12 | upper_idx << 8 | |
649 | upper_idx << 4 | upper_idx); |
650 | ret = upper_ret; |
651 | } |
652 | if (ret < 0) |
653 | goto restore; |
654 | |
655 | /* We calibrate TX-VCM in different logic. Check upper index and then |
656 | * lower index. If this calibration is valid, apply lower index's result. |
657 | */ |
658 | ret = upper_ret - lower_ret; |
659 | if (ret == 1) { |
660 | ret = 0; |
661 | /* Make sure we use upper_idx in our calibration system */ |
662 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
663 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
664 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
665 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
666 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
667 | cal_val: upper_idx << 12 | upper_idx << 8 | |
668 | upper_idx << 4 | upper_idx); |
669 | phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n" , upper_idx); |
670 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && |
671 | lower_ret == 1) { |
672 | ret = 0; |
673 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
674 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
675 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
676 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
677 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
678 | cal_val: lower_idx << 12 | lower_idx << 8 | |
679 | lower_idx << 4 | lower_idx); |
680 | phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n" , |
681 | lower_idx); |
682 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && |
683 | lower_ret == 0) { |
684 | ret = 0; |
685 | phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n" , |
686 | upper_idx); |
687 | } else { |
688 | ret = -EINVAL; |
689 | } |
690 | |
691 | restore: |
692 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
693 | MTK_PHY_RG_ANA_CALEN); |
694 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
695 | MTK_PHY_RG_TXVOS_CALEN); |
696 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
697 | MTK_PHY_RG_ZCALEN_A); |
698 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
699 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | |
700 | MTK_PHY_RG_ZCALEN_D); |
701 | |
702 | return ret; |
703 | } |
704 | |
705 | static void mt798x_phy_common_finetune(struct phy_device *phydev) |
706 | { |
707 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
708 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ |
709 | __phy_write(phydev, regnum: 0x11, val: 0xc71); |
710 | __phy_write(phydev, regnum: 0x12, val: 0xc); |
711 | __phy_write(phydev, regnum: 0x10, val: 0x8fae); |
712 | |
713 | /* EnabRandUpdTrig = 1 */ |
714 | __phy_write(phydev, regnum: 0x11, val: 0x2f00); |
715 | __phy_write(phydev, regnum: 0x12, val: 0xe); |
716 | __phy_write(phydev, regnum: 0x10, val: 0x8fb0); |
717 | |
718 | /* NormMseLoThresh = 85 */ |
719 | __phy_write(phydev, regnum: 0x11, val: 0x55a0); |
720 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
721 | __phy_write(phydev, regnum: 0x10, val: 0x83aa); |
722 | |
723 | /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ |
724 | __phy_write(phydev, regnum: 0x11, val: 0x240); |
725 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
726 | __phy_write(phydev, regnum: 0x10, val: 0x9680); |
727 | |
728 | /* TrFreeze = 0 (mt7988 default) */ |
729 | __phy_write(phydev, regnum: 0x11, val: 0x0); |
730 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
731 | __phy_write(phydev, regnum: 0x10, val: 0x9686); |
732 | |
733 | /* SSTrKp100 = 5 */ |
734 | /* SSTrKf100 = 6 */ |
735 | /* SSTrKp1000Mas = 5 */ |
736 | /* SSTrKf1000Mas = 6 */ |
737 | /* SSTrKp1000Slv = 5 */ |
738 | /* SSTrKf1000Slv = 6 */ |
739 | __phy_write(phydev, regnum: 0x11, val: 0xbaef); |
740 | __phy_write(phydev, regnum: 0x12, val: 0x2e); |
741 | __phy_write(phydev, regnum: 0x10, val: 0x968c); |
742 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, ret: 0); |
743 | } |
744 | |
745 | static void mt7981_phy_finetune(struct phy_device *phydev) |
746 | { |
747 | u16 val[8] = { 0x01ce, 0x01c1, |
748 | 0x020f, 0x0202, |
749 | 0x03d0, 0x03c0, |
750 | 0x0013, 0x0005 }; |
751 | int i, k; |
752 | |
753 | /* 100M eye finetune: |
754 | * Keep middle level of TX MLT3 shapper as default. |
755 | * Only change TX MLT3 overshoot level here. |
756 | */ |
757 | for (k = 0, i = 1; i < 12; i++) { |
758 | if (i % 3 == 0) |
759 | continue; |
760 | phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: i, val: val[k++]); |
761 | } |
762 | |
763 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
764 | /* ResetSyncOffset = 6 */ |
765 | __phy_write(phydev, regnum: 0x11, val: 0x600); |
766 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
767 | __phy_write(phydev, regnum: 0x10, val: 0x8fc0); |
768 | |
769 | /* VgaDecRate = 1 */ |
770 | __phy_write(phydev, regnum: 0x11, val: 0x4c2a); |
771 | __phy_write(phydev, regnum: 0x12, val: 0x3e); |
772 | __phy_write(phydev, regnum: 0x10, val: 0x8fa4); |
773 | |
774 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
775 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
776 | */ |
777 | __phy_write(phydev, regnum: 0x11, val: 0xd10a); |
778 | __phy_write(phydev, regnum: 0x12, val: 0x34); |
779 | __phy_write(phydev, regnum: 0x10, val: 0x8f82); |
780 | |
781 | /* VcoSlicerThreshBitsHigh */ |
782 | __phy_write(phydev, regnum: 0x11, val: 0x5555); |
783 | __phy_write(phydev, regnum: 0x12, val: 0x55); |
784 | __phy_write(phydev, regnum: 0x10, val: 0x8ec0); |
785 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, ret: 0); |
786 | |
787 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ |
788 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
789 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
790 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
791 | |
792 | /* rg_tr_lpf_cnt_val = 512 */ |
793 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, val: 0x200); |
794 | |
795 | /* IIR2 related */ |
796 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, val: 0x82); |
797 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, val: 0x0); |
798 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, val: 0x103); |
799 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, val: 0x0); |
800 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, val: 0x82); |
801 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, val: 0x0); |
802 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, val: 0xd177); |
803 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, val: 0x3); |
804 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, val: 0x2c82); |
805 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, val: 0xe); |
806 | |
807 | /* FFE peaking */ |
808 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
809 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, set: 0x1b << 8); |
810 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
811 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, set: 0x1e); |
812 | |
813 | /* Disable LDO pump */ |
814 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, val: 0x0); |
815 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, val: 0x0); |
816 | /* Adjust LDO output voltage */ |
817 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, val: 0x2222); |
818 | } |
819 | |
820 | static void mt7988_phy_finetune(struct phy_device *phydev) |
821 | { |
822 | u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, |
823 | 0x020d, 0x0206, 0x0384, 0x03d0, |
824 | 0x03c6, 0x030a, 0x0011, 0x0005 }; |
825 | int i; |
826 | |
827 | /* Set default MLT3 shaper first */ |
828 | for (i = 0; i < 12; i++) |
829 | phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: i, val: val[i]); |
830 | |
831 | /* TCT finetune */ |
832 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, val: 0x5); |
833 | |
834 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
835 | /* ResetSyncOffset = 5 */ |
836 | __phy_write(phydev, regnum: 0x11, val: 0x500); |
837 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
838 | __phy_write(phydev, regnum: 0x10, val: 0x8fc0); |
839 | |
840 | /* VgaDecRate is 1 at default on mt7988 */ |
841 | |
842 | /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, |
843 | * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 |
844 | */ |
845 | __phy_write(phydev, regnum: 0x11, val: 0xb90a); |
846 | __phy_write(phydev, regnum: 0x12, val: 0x6f); |
847 | __phy_write(phydev, regnum: 0x10, val: 0x8f82); |
848 | |
849 | /* RemAckCntLimitCtrl = 1 */ |
850 | __phy_write(phydev, regnum: 0x11, val: 0xfbba); |
851 | __phy_write(phydev, regnum: 0x12, val: 0xc3); |
852 | __phy_write(phydev, regnum: 0x10, val: 0x87f8); |
853 | |
854 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, ret: 0); |
855 | |
856 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ |
857 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
858 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
859 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); |
860 | |
861 | /* rg_tr_lpf_cnt_val = 1023 */ |
862 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, val: 0x3ff); |
863 | } |
864 | |
865 | static void mt798x_phy_eee(struct phy_device *phydev) |
866 | { |
867 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
868 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, |
869 | MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | |
870 | MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, |
871 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | |
872 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); |
873 | |
874 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
875 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
876 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
877 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
878 | 0xff)); |
879 | |
880 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
881 | MTK_PHY_RG_TESTMUX_ADC_CTRL, |
882 | MTK_PHY_RG_TXEN_DIG_MASK); |
883 | |
884 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
885 | MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); |
886 | |
887 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
888 | MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); |
889 | |
890 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, |
891 | MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | |
892 | MTK_PHY_LPI_SLV_SEND_TX_EN, |
893 | FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); |
894 | |
895 | /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ |
896 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, |
897 | MTK_PHY_LPI_TXPCS_LOC_RCV); |
898 | |
899 | /* This also fixes some IoT issues, such as CH340 */ |
900 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, |
901 | MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, |
902 | FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | |
903 | FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); |
904 | |
905 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, |
906 | MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
907 | FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
908 | 0x33) | |
909 | MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | |
910 | MTK_PHY_LPI_VCO_EEE_STG0_EN); |
911 | |
912 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, |
913 | MTK_PHY_EEE_WAKE_MAS_INT_DC | |
914 | MTK_PHY_EEE_WAKE_SLV_INT_DC); |
915 | |
916 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, |
917 | MTK_PHY_SMI_DETCNT_MAX_MASK, |
918 | FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | |
919 | MTK_PHY_SMI_DET_MAX_EN); |
920 | |
921 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, |
922 | MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | |
923 | MTK_PHY_TREC_UPDATE_ENAB_CLR | |
924 | MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | |
925 | MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); |
926 | |
927 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
928 | /* Regsigdet_sel_1000 = 0 */ |
929 | __phy_write(phydev, regnum: 0x11, val: 0xb); |
930 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
931 | __phy_write(phydev, regnum: 0x10, val: 0x9690); |
932 | |
933 | /* REG_EEE_st2TrKf1000 = 2 */ |
934 | __phy_write(phydev, regnum: 0x11, val: 0x114f); |
935 | __phy_write(phydev, regnum: 0x12, val: 0x2); |
936 | __phy_write(phydev, regnum: 0x10, val: 0x969a); |
937 | |
938 | /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ |
939 | __phy_write(phydev, regnum: 0x11, val: 0x3028); |
940 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
941 | __phy_write(phydev, regnum: 0x10, val: 0x969e); |
942 | |
943 | /* RegEEE_slv_wake_int_timer_tar = 8 */ |
944 | __phy_write(phydev, regnum: 0x11, val: 0x5010); |
945 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
946 | __phy_write(phydev, regnum: 0x10, val: 0x96a0); |
947 | |
948 | /* RegEEE_trfreeze_timer2 = 586 */ |
949 | __phy_write(phydev, regnum: 0x11, val: 0x24a); |
950 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
951 | __phy_write(phydev, regnum: 0x10, val: 0x96a8); |
952 | |
953 | /* RegEEE100Stg1_tar = 16 */ |
954 | __phy_write(phydev, regnum: 0x11, val: 0x3210); |
955 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
956 | __phy_write(phydev, regnum: 0x10, val: 0x96b8); |
957 | |
958 | /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ |
959 | __phy_write(phydev, regnum: 0x11, val: 0x1463); |
960 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
961 | __phy_write(phydev, regnum: 0x10, val: 0x96ca); |
962 | |
963 | /* DfeTailEnableVgaThresh1000 = 27 */ |
964 | __phy_write(phydev, regnum: 0x11, val: 0x36); |
965 | __phy_write(phydev, regnum: 0x12, val: 0x0); |
966 | __phy_write(phydev, regnum: 0x10, val: 0x8f80); |
967 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, ret: 0); |
968 | |
969 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); |
970 | __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, |
971 | FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); |
972 | |
973 | __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, |
974 | FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); |
975 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, ret: 0); |
976 | |
977 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
978 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
979 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
980 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
981 | } |
982 | |
983 | static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, |
984 | u8 start_pair, u8 end_pair) |
985 | { |
986 | u8 pair_n; |
987 | int ret; |
988 | |
989 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
990 | /* TX_OFFSET & TX_AMP have no SW calibration. */ |
991 | switch (cal_item) { |
992 | case TX_VCM: |
993 | ret = tx_vcm_cal_sw(phydev, rg_txreserve_x: pair_n); |
994 | break; |
995 | default: |
996 | return -EINVAL; |
997 | } |
998 | if (ret) |
999 | return ret; |
1000 | } |
1001 | return 0; |
1002 | } |
1003 | |
1004 | static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, |
1005 | u8 start_pair, u8 end_pair, u32 *buf) |
1006 | { |
1007 | u8 pair_n; |
1008 | int ret; |
1009 | |
1010 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
1011 | /* TX_VCM has no efuse calibration. */ |
1012 | switch (cal_item) { |
1013 | case REXT: |
1014 | ret = rext_cal_efuse(phydev, buf); |
1015 | break; |
1016 | case TX_OFFSET: |
1017 | ret = tx_offset_cal_efuse(phydev, buf); |
1018 | break; |
1019 | case TX_AMP: |
1020 | ret = tx_amp_cal_efuse(phydev, buf); |
1021 | break; |
1022 | case TX_R50: |
1023 | ret = tx_r50_cal_efuse(phydev, buf, txg_calen_x: pair_n); |
1024 | break; |
1025 | default: |
1026 | return -EINVAL; |
1027 | } |
1028 | if (ret) |
1029 | return ret; |
1030 | } |
1031 | |
1032 | return 0; |
1033 | } |
1034 | |
1035 | static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, |
1036 | enum CAL_MODE cal_mode, u8 start_pair, |
1037 | u8 end_pair, u32 *buf) |
1038 | { |
1039 | int ret; |
1040 | |
1041 | switch (cal_mode) { |
1042 | case EFUSE_M: |
1043 | ret = cal_efuse(phydev, cal_item, start_pair, |
1044 | end_pair, buf); |
1045 | break; |
1046 | case SW_M: |
1047 | ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
1048 | break; |
1049 | default: |
1050 | return -EINVAL; |
1051 | } |
1052 | |
1053 | if (ret) { |
1054 | phydev_err(phydev, "cal %d failed\n" , cal_item); |
1055 | return -EIO; |
1056 | } |
1057 | |
1058 | return 0; |
1059 | } |
1060 | |
1061 | static int mt798x_phy_calibration(struct phy_device *phydev) |
1062 | { |
1063 | int ret = 0; |
1064 | u32 *buf; |
1065 | size_t len; |
1066 | struct nvmem_cell *cell; |
1067 | |
1068 | cell = nvmem_cell_get(dev: &phydev->mdio.dev, id: "phy-cal-data" ); |
1069 | if (IS_ERR(ptr: cell)) { |
1070 | if (PTR_ERR(ptr: cell) == -EPROBE_DEFER) |
1071 | return PTR_ERR(ptr: cell); |
1072 | return 0; |
1073 | } |
1074 | |
1075 | buf = (u32 *)nvmem_cell_read(cell, len: &len); |
1076 | if (IS_ERR(ptr: buf)) |
1077 | return PTR_ERR(ptr: buf); |
1078 | nvmem_cell_put(cell); |
1079 | |
1080 | if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { |
1081 | phydev_err(phydev, "invalid efuse data\n" ); |
1082 | ret = -EINVAL; |
1083 | goto out; |
1084 | } |
1085 | |
1086 | ret = start_cal(phydev, cal_item: REXT, cal_mode: EFUSE_M, start_pair: NO_PAIR, end_pair: NO_PAIR, buf); |
1087 | if (ret) |
1088 | goto out; |
1089 | ret = start_cal(phydev, cal_item: TX_OFFSET, cal_mode: EFUSE_M, start_pair: NO_PAIR, end_pair: NO_PAIR, buf); |
1090 | if (ret) |
1091 | goto out; |
1092 | ret = start_cal(phydev, cal_item: TX_AMP, cal_mode: EFUSE_M, start_pair: NO_PAIR, end_pair: NO_PAIR, buf); |
1093 | if (ret) |
1094 | goto out; |
1095 | ret = start_cal(phydev, cal_item: TX_R50, cal_mode: EFUSE_M, start_pair: PAIR_A, end_pair: PAIR_D, buf); |
1096 | if (ret) |
1097 | goto out; |
1098 | ret = start_cal(phydev, cal_item: TX_VCM, cal_mode: SW_M, start_pair: PAIR_A, end_pair: PAIR_A, buf); |
1099 | if (ret) |
1100 | goto out; |
1101 | |
1102 | out: |
1103 | kfree(objp: buf); |
1104 | return ret; |
1105 | } |
1106 | |
1107 | static int mt798x_phy_config_init(struct phy_device *phydev) |
1108 | { |
1109 | switch (phydev->drv->phy_id) { |
1110 | case MTK_GPHY_ID_MT7981: |
1111 | mt7981_phy_finetune(phydev); |
1112 | break; |
1113 | case MTK_GPHY_ID_MT7988: |
1114 | mt7988_phy_finetune(phydev); |
1115 | break; |
1116 | } |
1117 | |
1118 | mt798x_phy_common_finetune(phydev); |
1119 | mt798x_phy_eee(phydev); |
1120 | |
1121 | return mt798x_phy_calibration(phydev); |
1122 | } |
1123 | |
1124 | static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, |
1125 | bool on) |
1126 | { |
1127 | unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); |
1128 | struct mtk_socphy_priv *priv = phydev->priv; |
1129 | bool changed; |
1130 | |
1131 | if (on) |
1132 | changed = !test_and_set_bit(nr: bit_on, addr: &priv->led_state); |
1133 | else |
1134 | changed = !!test_and_clear_bit(nr: bit_on, addr: &priv->led_state); |
1135 | |
1136 | changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + |
1137 | (index ? 16 : 0), addr: &priv->led_state); |
1138 | if (changed) |
1139 | return phy_modify_mmd(phydev, MDIO_MMD_VEND2, regnum: index ? |
1140 | MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, |
1141 | MTK_PHY_LED_ON_MASK, |
1142 | set: on ? MTK_PHY_LED_ON_FORCE_ON : 0); |
1143 | else |
1144 | return 0; |
1145 | } |
1146 | |
1147 | static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, |
1148 | bool blinking) |
1149 | { |
1150 | unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); |
1151 | struct mtk_socphy_priv *priv = phydev->priv; |
1152 | bool changed; |
1153 | |
1154 | if (blinking) |
1155 | changed = !test_and_set_bit(nr: bit_blink, addr: &priv->led_state); |
1156 | else |
1157 | changed = !!test_and_clear_bit(nr: bit_blink, addr: &priv->led_state); |
1158 | |
1159 | changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + |
1160 | (index ? 16 : 0), &priv->led_state); |
1161 | if (changed) |
1162 | return phy_write_mmd(phydev, MDIO_MMD_VEND2, regnum: index ? |
1163 | MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, |
1164 | val: blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); |
1165 | else |
1166 | return 0; |
1167 | } |
1168 | |
1169 | static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, |
1170 | unsigned long *delay_on, |
1171 | unsigned long *delay_off) |
1172 | { |
1173 | bool blinking = false; |
1174 | int err = 0; |
1175 | |
1176 | if (index > 1) |
1177 | return -EINVAL; |
1178 | |
1179 | if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { |
1180 | blinking = true; |
1181 | *delay_on = 50; |
1182 | *delay_off = 50; |
1183 | } |
1184 | |
1185 | err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); |
1186 | if (err) |
1187 | return err; |
1188 | |
1189 | return mt798x_phy_hw_led_on_set(phydev, index, on: false); |
1190 | } |
1191 | |
1192 | static int mt798x_phy_led_brightness_set(struct phy_device *phydev, |
1193 | u8 index, enum led_brightness value) |
1194 | { |
1195 | int err; |
1196 | |
1197 | err = mt798x_phy_hw_led_blink_set(phydev, index, blinking: false); |
1198 | if (err) |
1199 | return err; |
1200 | |
1201 | return mt798x_phy_hw_led_on_set(phydev, index, on: (value != LED_OFF)); |
1202 | } |
1203 | |
1204 | static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | |
1205 | BIT(TRIGGER_NETDEV_HALF_DUPLEX) | |
1206 | BIT(TRIGGER_NETDEV_LINK) | |
1207 | BIT(TRIGGER_NETDEV_LINK_10) | |
1208 | BIT(TRIGGER_NETDEV_LINK_100) | |
1209 | BIT(TRIGGER_NETDEV_LINK_1000) | |
1210 | BIT(TRIGGER_NETDEV_RX) | |
1211 | BIT(TRIGGER_NETDEV_TX)); |
1212 | |
1213 | static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, |
1214 | unsigned long rules) |
1215 | { |
1216 | if (index > 1) |
1217 | return -EINVAL; |
1218 | |
1219 | /* All combinations of the supported triggers are allowed */ |
1220 | if (rules & ~supported_triggers) |
1221 | return -EOPNOTSUPP; |
1222 | |
1223 | return 0; |
1224 | }; |
1225 | |
1226 | static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, |
1227 | unsigned long *rules) |
1228 | { |
1229 | unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); |
1230 | unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); |
1231 | unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); |
1232 | struct mtk_socphy_priv *priv = phydev->priv; |
1233 | int on, blink; |
1234 | |
1235 | if (index > 1) |
1236 | return -EINVAL; |
1237 | |
1238 | on = phy_read_mmd(phydev, MDIO_MMD_VEND2, |
1239 | regnum: index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); |
1240 | |
1241 | if (on < 0) |
1242 | return -EIO; |
1243 | |
1244 | blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, |
1245 | regnum: index ? MTK_PHY_LED1_BLINK_CTRL : |
1246 | MTK_PHY_LED0_BLINK_CTRL); |
1247 | if (blink < 0) |
1248 | return -EIO; |
1249 | |
1250 | if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | |
1251 | MTK_PHY_LED_ON_LINK10)) || |
1252 | (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | |
1253 | MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX | |
1254 | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))) |
1255 | set_bit(nr: bit_netdev, addr: &priv->led_state); |
1256 | else |
1257 | clear_bit(nr: bit_netdev, addr: &priv->led_state); |
1258 | |
1259 | if (on & MTK_PHY_LED_ON_FORCE_ON) |
1260 | set_bit(nr: bit_on, addr: &priv->led_state); |
1261 | else |
1262 | clear_bit(nr: bit_on, addr: &priv->led_state); |
1263 | |
1264 | if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) |
1265 | set_bit(nr: bit_blink, addr: &priv->led_state); |
1266 | else |
1267 | clear_bit(nr: bit_blink, addr: &priv->led_state); |
1268 | |
1269 | if (!rules) |
1270 | return 0; |
1271 | |
1272 | if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10)) |
1273 | *rules |= BIT(TRIGGER_NETDEV_LINK); |
1274 | |
1275 | if (on & MTK_PHY_LED_ON_LINK10) |
1276 | *rules |= BIT(TRIGGER_NETDEV_LINK_10); |
1277 | |
1278 | if (on & MTK_PHY_LED_ON_LINK100) |
1279 | *rules |= BIT(TRIGGER_NETDEV_LINK_100); |
1280 | |
1281 | if (on & MTK_PHY_LED_ON_LINK1000) |
1282 | *rules |= BIT(TRIGGER_NETDEV_LINK_1000); |
1283 | |
1284 | if (on & MTK_PHY_LED_ON_FDX) |
1285 | *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); |
1286 | |
1287 | if (on & MTK_PHY_LED_ON_HDX) |
1288 | *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); |
1289 | |
1290 | if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX)) |
1291 | *rules |= BIT(TRIGGER_NETDEV_RX); |
1292 | |
1293 | if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)) |
1294 | *rules |= BIT(TRIGGER_NETDEV_TX); |
1295 | |
1296 | return 0; |
1297 | }; |
1298 | |
1299 | static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, |
1300 | unsigned long rules) |
1301 | { |
1302 | unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); |
1303 | struct mtk_socphy_priv *priv = phydev->priv; |
1304 | u16 on = 0, blink = 0; |
1305 | int ret; |
1306 | |
1307 | if (index > 1) |
1308 | return -EINVAL; |
1309 | |
1310 | if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) |
1311 | on |= MTK_PHY_LED_ON_FDX; |
1312 | |
1313 | if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) |
1314 | on |= MTK_PHY_LED_ON_HDX; |
1315 | |
1316 | if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) |
1317 | on |= MTK_PHY_LED_ON_LINK10; |
1318 | |
1319 | if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) |
1320 | on |= MTK_PHY_LED_ON_LINK100; |
1321 | |
1322 | if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) |
1323 | on |= MTK_PHY_LED_ON_LINK1000; |
1324 | |
1325 | if (rules & BIT(TRIGGER_NETDEV_RX)) { |
1326 | blink |= MTK_PHY_LED_BLINK_10RX | |
1327 | MTK_PHY_LED_BLINK_100RX | |
1328 | MTK_PHY_LED_BLINK_1000RX; |
1329 | } |
1330 | |
1331 | if (rules & BIT(TRIGGER_NETDEV_TX)) { |
1332 | blink |= MTK_PHY_LED_BLINK_10TX | |
1333 | MTK_PHY_LED_BLINK_100TX | |
1334 | MTK_PHY_LED_BLINK_1000TX; |
1335 | } |
1336 | |
1337 | if (blink || on) |
1338 | set_bit(nr: bit_netdev, addr: &priv->led_state); |
1339 | else |
1340 | clear_bit(nr: bit_netdev, addr: &priv->led_state); |
1341 | |
1342 | ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, regnum: index ? |
1343 | MTK_PHY_LED1_ON_CTRL : |
1344 | MTK_PHY_LED0_ON_CTRL, |
1345 | MTK_PHY_LED_ON_FDX | |
1346 | MTK_PHY_LED_ON_HDX | |
1347 | MTK_PHY_LED_ON_LINK10 | |
1348 | MTK_PHY_LED_ON_LINK100 | |
1349 | MTK_PHY_LED_ON_LINK1000, |
1350 | set: on); |
1351 | |
1352 | if (ret) |
1353 | return ret; |
1354 | |
1355 | return phy_write_mmd(phydev, MDIO_MMD_VEND2, regnum: index ? |
1356 | MTK_PHY_LED1_BLINK_CTRL : |
1357 | MTK_PHY_LED0_BLINK_CTRL, val: blink); |
1358 | }; |
1359 | |
1360 | static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) |
1361 | { |
1362 | struct mtk_socphy_shared *priv = phydev->shared->priv; |
1363 | u32 polarities; |
1364 | |
1365 | if (led_num == 0) |
1366 | polarities = ~(priv->boottrap); |
1367 | else |
1368 | polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; |
1369 | |
1370 | if (polarities & BIT(phydev->mdio.addr)) |
1371 | return true; |
1372 | |
1373 | return false; |
1374 | } |
1375 | |
1376 | static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) |
1377 | { |
1378 | struct pinctrl *pinctrl; |
1379 | int index; |
1380 | |
1381 | /* Setup LED polarity according to bootstrap use of LED pins */ |
1382 | for (index = 0; index < 2; ++index) |
1383 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, regnum: index ? |
1384 | MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, |
1385 | MTK_PHY_LED_ON_POLARITY, |
1386 | set: mt7988_phy_led_get_polarity(phydev, led_num: index) ? |
1387 | MTK_PHY_LED_ON_POLARITY : 0); |
1388 | |
1389 | /* Only now setup pinctrl to avoid bogus blinking */ |
1390 | pinctrl = devm_pinctrl_get_select(dev: &phydev->mdio.dev, name: "gbe-led" ); |
1391 | if (IS_ERR(ptr: pinctrl)) |
1392 | dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n" ); |
1393 | |
1394 | return 0; |
1395 | } |
1396 | |
1397 | static int mt7988_phy_probe_shared(struct phy_device *phydev) |
1398 | { |
1399 | struct device_node *np = dev_of_node(dev: &phydev->mdio.bus->dev); |
1400 | struct mtk_socphy_shared *shared = phydev->shared->priv; |
1401 | struct regmap *regmap; |
1402 | u32 reg; |
1403 | int ret; |
1404 | |
1405 | /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, |
1406 | * LED_C and LED_D respectively. At the same time those pins are used to |
1407 | * bootstrap configuration of the reference clock source (LED_A), |
1408 | * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). |
1409 | * In practise this is done using a LED and a resistor pulling the pin |
1410 | * either to GND or to VIO. |
1411 | * The detected value at boot time is accessible at run-time using the |
1412 | * TPBANK0 register located in the gpio base of the pinctrl, in order |
1413 | * to read it here it needs to be referenced by a phandle called |
1414 | * 'mediatek,pio' in the MDIO bus hosting the PHY. |
1415 | * The 4 bits in TPBANK0 are kept as package shared data and are used to |
1416 | * set LED polarity for each of the LED0. |
1417 | */ |
1418 | regmap = syscon_regmap_lookup_by_phandle(np, property: "mediatek,pio" ); |
1419 | if (IS_ERR(ptr: regmap)) |
1420 | return PTR_ERR(ptr: regmap); |
1421 | |
1422 | ret = regmap_read(map: regmap, RG_GPIO_MISC_TPBANK0, val: ®); |
1423 | if (ret) |
1424 | return ret; |
1425 | |
1426 | shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); |
1427 | |
1428 | return 0; |
1429 | } |
1430 | |
1431 | static void mt798x_phy_leds_state_init(struct phy_device *phydev) |
1432 | { |
1433 | int i; |
1434 | |
1435 | for (i = 0; i < 2; ++i) |
1436 | mt798x_phy_led_hw_control_get(phydev, index: i, NULL); |
1437 | } |
1438 | |
1439 | static int mt7988_phy_probe(struct phy_device *phydev) |
1440 | { |
1441 | struct mtk_socphy_shared *shared; |
1442 | struct mtk_socphy_priv *priv; |
1443 | int err; |
1444 | |
1445 | if (phydev->mdio.addr > 3) |
1446 | return -EINVAL; |
1447 | |
1448 | err = devm_phy_package_join(dev: &phydev->mdio.dev, phydev, base_addr: 0, |
1449 | priv_size: sizeof(struct mtk_socphy_shared)); |
1450 | if (err) |
1451 | return err; |
1452 | |
1453 | if (phy_package_probe_once(phydev)) { |
1454 | err = mt7988_phy_probe_shared(phydev); |
1455 | if (err) |
1456 | return err; |
1457 | } |
1458 | |
1459 | shared = phydev->shared->priv; |
1460 | priv = &shared->priv[phydev->mdio.addr]; |
1461 | |
1462 | phydev->priv = priv; |
1463 | |
1464 | mt798x_phy_leds_state_init(phydev); |
1465 | |
1466 | err = mt7988_phy_fix_leds_polarities(phydev); |
1467 | if (err) |
1468 | return err; |
1469 | |
1470 | /* Disable TX power saving at probing to: |
1471 | * 1. Meet common mode compliance test criteria |
1472 | * 2. Make sure that TX-VCM calibration works fine |
1473 | */ |
1474 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
1475 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, set: 0x3 << 8); |
1476 | |
1477 | return mt798x_phy_calibration(phydev); |
1478 | } |
1479 | |
1480 | static int mt7981_phy_probe(struct phy_device *phydev) |
1481 | { |
1482 | struct mtk_socphy_priv *priv; |
1483 | |
1484 | priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(struct mtk_socphy_priv), |
1485 | GFP_KERNEL); |
1486 | if (!priv) |
1487 | return -ENOMEM; |
1488 | |
1489 | phydev->priv = priv; |
1490 | |
1491 | mt798x_phy_leds_state_init(phydev); |
1492 | |
1493 | return mt798x_phy_calibration(phydev); |
1494 | } |
1495 | |
1496 | static struct phy_driver mtk_socphy_driver[] = { |
1497 | { |
1498 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), |
1499 | .name = "MediaTek MT7981 PHY" , |
1500 | .config_init = mt798x_phy_config_init, |
1501 | .config_intr = genphy_no_config_intr, |
1502 | .handle_interrupt = genphy_handle_interrupt_no_ack, |
1503 | .probe = mt7981_phy_probe, |
1504 | .suspend = genphy_suspend, |
1505 | .resume = genphy_resume, |
1506 | .read_page = mtk_socphy_read_page, |
1507 | .write_page = mtk_socphy_write_page, |
1508 | .led_blink_set = mt798x_phy_led_blink_set, |
1509 | .led_brightness_set = mt798x_phy_led_brightness_set, |
1510 | .led_hw_is_supported = mt798x_phy_led_hw_is_supported, |
1511 | .led_hw_control_set = mt798x_phy_led_hw_control_set, |
1512 | .led_hw_control_get = mt798x_phy_led_hw_control_get, |
1513 | }, |
1514 | { |
1515 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), |
1516 | .name = "MediaTek MT7988 PHY" , |
1517 | .config_init = mt798x_phy_config_init, |
1518 | .config_intr = genphy_no_config_intr, |
1519 | .handle_interrupt = genphy_handle_interrupt_no_ack, |
1520 | .probe = mt7988_phy_probe, |
1521 | .suspend = genphy_suspend, |
1522 | .resume = genphy_resume, |
1523 | .read_page = mtk_socphy_read_page, |
1524 | .write_page = mtk_socphy_write_page, |
1525 | .led_blink_set = mt798x_phy_led_blink_set, |
1526 | .led_brightness_set = mt798x_phy_led_brightness_set, |
1527 | .led_hw_is_supported = mt798x_phy_led_hw_is_supported, |
1528 | .led_hw_control_set = mt798x_phy_led_hw_control_set, |
1529 | .led_hw_control_get = mt798x_phy_led_hw_control_get, |
1530 | }, |
1531 | }; |
1532 | |
1533 | module_phy_driver(mtk_socphy_driver); |
1534 | |
1535 | static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { |
1536 | { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, |
1537 | { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, |
1538 | { } |
1539 | }; |
1540 | |
1541 | MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver" ); |
1542 | MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>" ); |
1543 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>" ); |
1544 | MODULE_LICENSE("GPL" ); |
1545 | |
1546 | MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); |
1547 | |