1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* Copyright (C) 2021 Maxlinear Corporation |
3 | * Copyright (C) 2020 Intel Corporation |
4 | * |
5 | * Drivers for Maxlinear Ethernet GPY |
6 | * |
7 | */ |
8 | |
9 | #include <linux/module.h> |
10 | #include <linux/bitfield.h> |
11 | #include <linux/hwmon.h> |
12 | #include <linux/mutex.h> |
13 | #include <linux/phy.h> |
14 | #include <linux/polynomial.h> |
15 | #include <linux/property.h> |
16 | #include <linux/netdevice.h> |
17 | |
18 | /* PHY ID */ |
19 | #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC |
20 | #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 |
21 | #define PHY_ID_GPY2xx 0x67C9DC00 |
22 | #define PHY_ID_GPY115B 0x67C9DF00 |
23 | #define PHY_ID_GPY115C 0x67C9DF10 |
24 | #define PHY_ID_GPY211B 0x67C9DE08 |
25 | #define PHY_ID_GPY211C 0x67C9DE10 |
26 | #define PHY_ID_GPY212B 0x67C9DE09 |
27 | #define PHY_ID_GPY212C 0x67C9DE20 |
28 | #define PHY_ID_GPY215B 0x67C9DF04 |
29 | #define PHY_ID_GPY215C 0x67C9DF20 |
30 | #define PHY_ID_GPY241B 0x67C9DE40 |
31 | #define PHY_ID_GPY241BM 0x67C9DE80 |
32 | #define PHY_ID_GPY245B 0x67C9DEC0 |
33 | |
34 | #define PHY_CTL1 0x13 |
35 | #define PHY_CTL1_MDICD BIT(3) |
36 | #define PHY_CTL1_MDIAB BIT(2) |
37 | #define PHY_CTL1_AMDIX BIT(0) |
38 | #define PHY_MIISTAT 0x18 /* MII state */ |
39 | #define PHY_IMASK 0x19 /* interrupt mask */ |
40 | #define PHY_ISTAT 0x1A /* interrupt status */ |
41 | #define PHY_FWV 0x1E /* firmware version */ |
42 | |
43 | #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) |
44 | #define PHY_MIISTAT_DPX BIT(3) |
45 | #define PHY_MIISTAT_LS BIT(10) |
46 | |
47 | #define PHY_MIISTAT_SPD_10 0 |
48 | #define PHY_MIISTAT_SPD_100 1 |
49 | #define PHY_MIISTAT_SPD_1000 2 |
50 | #define PHY_MIISTAT_SPD_2500 4 |
51 | |
52 | #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ |
53 | #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ |
54 | #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ |
55 | #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ |
56 | #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ |
57 | #define PHY_IMASK_LSTC BIT(0) /* Link state change */ |
58 | #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ |
59 | PHY_IMASK_LSPC | \ |
60 | PHY_IMASK_DXMC | \ |
61 | PHY_IMASK_ADSC | \ |
62 | PHY_IMASK_ANC) |
63 | |
64 | #define PHY_FWV_REL_MASK BIT(15) |
65 | #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) |
66 | #define PHY_FWV_MINOR_MASK GENMASK(7, 0) |
67 | |
68 | #define PHY_PMA_MGBT_POLARITY 0x82 |
69 | #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) |
70 | #define PHY_MDI_MDI_X_NORMAL 0x3 |
71 | #define PHY_MDI_MDI_X_AB 0x2 |
72 | #define PHY_MDI_MDI_X_CD 0x1 |
73 | #define PHY_MDI_MDI_X_CROSS 0x0 |
74 | |
75 | /* SGMII */ |
76 | #define VSPEC1_SGMII_CTRL 0x08 |
77 | #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ |
78 | #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ |
79 | #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ |
80 | VSPEC1_SGMII_CTRL_ANRS) |
81 | |
82 | /* Temperature sensor */ |
83 | #define VSPEC1_TEMP_STA 0x0E |
84 | #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) |
85 | |
86 | /* Mailbox */ |
87 | #define VSPEC1_MBOX_DATA 0x5 |
88 | #define VSPEC1_MBOX_ADDRLO 0x6 |
89 | #define VSPEC1_MBOX_CMD 0x7 |
90 | #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) |
91 | #define VSPEC1_MBOX_CMD_RD (0 << 8) |
92 | #define VSPEC1_MBOX_CMD_READY BIT(15) |
93 | |
94 | /* WoL */ |
95 | #define VPSPEC2_WOL_CTL 0x0E06 |
96 | #define VPSPEC2_WOL_AD01 0x0E08 |
97 | #define VPSPEC2_WOL_AD23 0x0E09 |
98 | #define VPSPEC2_WOL_AD45 0x0E0A |
99 | #define WOL_EN BIT(0) |
100 | |
101 | /* Internal registers, access via mbox */ |
102 | #define REG_GPIO0_OUT 0xd3ce00 |
103 | |
104 | struct gpy_priv { |
105 | /* serialize mailbox acesses */ |
106 | struct mutex mbox_lock; |
107 | |
108 | u8 fw_major; |
109 | u8 fw_minor; |
110 | |
111 | /* It takes 3 seconds to fully switch out of loopback mode before |
112 | * it can safely re-enter loopback mode. Record the time when |
113 | * loopback is disabled. Check and wait if necessary before loopback |
114 | * is enabled. |
115 | */ |
116 | u64 lb_dis_to; |
117 | }; |
118 | |
119 | static const struct { |
120 | int major; |
121 | int minor; |
122 | } ver_need_sgmii_reaneg[] = { |
123 | {7, 0x6D}, |
124 | {8, 0x6D}, |
125 | {9, 0x73}, |
126 | }; |
127 | |
128 | #if IS_ENABLED(CONFIG_HWMON) |
129 | /* The original translation formulae of the temperature (in degrees of Celsius) |
130 | * are as follows: |
131 | * |
132 | * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + |
133 | * 3.0762e-1*(N^1) + -5.2156e1 |
134 | * |
135 | * where [-52.156, 137.961]C and N = [0, 1023]. |
136 | * |
137 | * They must be accordingly altered to be suitable for the integer arithmetics. |
138 | * The technique is called 'factor redistribution', which just makes sure the |
139 | * multiplications and divisions are made so to have a result of the operations |
140 | * within the integer numbers limit. In addition we need to translate the |
141 | * formulae to accept millidegrees of Celsius. Here what it looks like after |
142 | * the alterations: |
143 | * |
144 | * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + |
145 | * 307620e-3*(N^1) + -52156 |
146 | * |
147 | * where T = [-52156, 137961]mC and N = [0, 1023]. |
148 | */ |
149 | static const struct polynomial poly_N_to_temp = { |
150 | .terms = { |
151 | {4, -25761, 1000, 1}, |
152 | {3, 97332, 1000, 1}, |
153 | {2, -191650, 1000, 1}, |
154 | {1, 307620, 1000, 1}, |
155 | {0, -52156, 1, 1} |
156 | } |
157 | }; |
158 | |
159 | static int gpy_hwmon_read(struct device *dev, |
160 | enum hwmon_sensor_types type, |
161 | u32 attr, int channel, long *value) |
162 | { |
163 | struct phy_device *phydev = dev_get_drvdata(dev); |
164 | int ret; |
165 | |
166 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); |
167 | if (ret < 0) |
168 | return ret; |
169 | if (!ret) |
170 | return -ENODATA; |
171 | |
172 | *value = polynomial_calc(poly: &poly_N_to_temp, |
173 | FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); |
174 | |
175 | return 0; |
176 | } |
177 | |
178 | static umode_t gpy_hwmon_is_visible(const void *data, |
179 | enum hwmon_sensor_types type, |
180 | u32 attr, int channel) |
181 | { |
182 | return 0444; |
183 | } |
184 | |
185 | static const struct hwmon_channel_info * const gpy_hwmon_info[] = { |
186 | HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), |
187 | NULL |
188 | }; |
189 | |
190 | static const struct hwmon_ops gpy_hwmon_hwmon_ops = { |
191 | .is_visible = gpy_hwmon_is_visible, |
192 | .read = gpy_hwmon_read, |
193 | }; |
194 | |
195 | static const struct hwmon_chip_info gpy_hwmon_chip_info = { |
196 | .ops = &gpy_hwmon_hwmon_ops, |
197 | .info = gpy_hwmon_info, |
198 | }; |
199 | |
200 | static int gpy_hwmon_register(struct phy_device *phydev) |
201 | { |
202 | struct device *dev = &phydev->mdio.dev; |
203 | struct device *hwmon_dev; |
204 | char *hwmon_name; |
205 | |
206 | hwmon_name = devm_hwmon_sanitize_name(dev, name: dev_name(dev)); |
207 | if (IS_ERR(ptr: hwmon_name)) |
208 | return PTR_ERR(ptr: hwmon_name); |
209 | |
210 | hwmon_dev = devm_hwmon_device_register_with_info(dev, name: hwmon_name, |
211 | drvdata: phydev, |
212 | info: &gpy_hwmon_chip_info, |
213 | NULL); |
214 | |
215 | return PTR_ERR_OR_ZERO(ptr: hwmon_dev); |
216 | } |
217 | #else |
218 | static int gpy_hwmon_register(struct phy_device *phydev) |
219 | { |
220 | return 0; |
221 | } |
222 | #endif |
223 | |
224 | static int gpy_mbox_read(struct phy_device *phydev, u32 addr) |
225 | { |
226 | struct gpy_priv *priv = phydev->priv; |
227 | int val, ret; |
228 | u16 cmd; |
229 | |
230 | mutex_lock(&priv->mbox_lock); |
231 | |
232 | ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, |
233 | val: addr); |
234 | if (ret) |
235 | goto out; |
236 | |
237 | cmd = VSPEC1_MBOX_CMD_RD; |
238 | cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); |
239 | |
240 | ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, val: cmd); |
241 | if (ret) |
242 | goto out; |
243 | |
244 | /* The mbox read is used in the interrupt workaround. It was observed |
245 | * that a read might take up to 2.5ms. This is also the time for which |
246 | * the interrupt line is stuck low. To be on the safe side, poll the |
247 | * ready bit for 10ms. |
248 | */ |
249 | ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, |
250 | VSPEC1_MBOX_CMD, val, |
251 | (val & VSPEC1_MBOX_CMD_READY), |
252 | 500, 10000, false); |
253 | if (ret) |
254 | goto out; |
255 | |
256 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); |
257 | |
258 | out: |
259 | mutex_unlock(lock: &priv->mbox_lock); |
260 | return ret; |
261 | } |
262 | |
263 | static int gpy_config_init(struct phy_device *phydev) |
264 | { |
265 | int ret; |
266 | |
267 | /* Mask all interrupts */ |
268 | ret = phy_write(phydev, PHY_IMASK, val: 0); |
269 | if (ret) |
270 | return ret; |
271 | |
272 | /* Clear all pending interrupts */ |
273 | ret = phy_read(phydev, PHY_ISTAT); |
274 | return ret < 0 ? ret : 0; |
275 | } |
276 | |
277 | static int gpy21x_config_init(struct phy_device *phydev) |
278 | { |
279 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces); |
280 | __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces); |
281 | |
282 | return gpy_config_init(phydev); |
283 | } |
284 | |
285 | static int gpy_probe(struct phy_device *phydev) |
286 | { |
287 | struct device *dev = &phydev->mdio.dev; |
288 | struct gpy_priv *priv; |
289 | int fw_version; |
290 | int ret; |
291 | |
292 | if (!phydev->is_c45) { |
293 | ret = phy_get_c45_ids(phydev); |
294 | if (ret < 0) |
295 | return ret; |
296 | } |
297 | |
298 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
299 | if (!priv) |
300 | return -ENOMEM; |
301 | phydev->priv = priv; |
302 | mutex_init(&priv->mbox_lock); |
303 | |
304 | if (!device_property_present(dev, propname: "maxlinear,use-broken-interrupts" )) |
305 | phydev->dev_flags |= PHY_F_NO_IRQ; |
306 | |
307 | fw_version = phy_read(phydev, PHY_FWV); |
308 | if (fw_version < 0) |
309 | return fw_version; |
310 | priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); |
311 | priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); |
312 | |
313 | ret = gpy_hwmon_register(phydev); |
314 | if (ret) |
315 | return ret; |
316 | |
317 | /* Show GPY PHY FW version in dmesg */ |
318 | phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n" , |
319 | priv->fw_major, priv->fw_minor, fw_version, |
320 | fw_version & PHY_FWV_REL_MASK ? "" : " test version" ); |
321 | |
322 | return 0; |
323 | } |
324 | |
325 | static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) |
326 | { |
327 | struct gpy_priv *priv = phydev->priv; |
328 | size_t i; |
329 | |
330 | for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { |
331 | if (priv->fw_major != ver_need_sgmii_reaneg[i].major) |
332 | continue; |
333 | if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) |
334 | return true; |
335 | break; |
336 | } |
337 | |
338 | return false; |
339 | } |
340 | |
341 | static bool gpy_2500basex_chk(struct phy_device *phydev) |
342 | { |
343 | int ret; |
344 | |
345 | ret = phy_read(phydev, PHY_MIISTAT); |
346 | if (ret < 0) { |
347 | phydev_err(phydev, "Error: MDIO register access failed: %d\n" , |
348 | ret); |
349 | return false; |
350 | } |
351 | |
352 | if (!(ret & PHY_MIISTAT_LS) || |
353 | FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) |
354 | return false; |
355 | |
356 | phydev->speed = SPEED_2500; |
357 | phydev->interface = PHY_INTERFACE_MODE_2500BASEX; |
358 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, |
359 | VSPEC1_SGMII_CTRL_ANEN, set: 0); |
360 | return true; |
361 | } |
362 | |
363 | static bool gpy_sgmii_aneg_en(struct phy_device *phydev) |
364 | { |
365 | int ret; |
366 | |
367 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); |
368 | if (ret < 0) { |
369 | phydev_err(phydev, "Error: MMD register access failed: %d\n" , |
370 | ret); |
371 | return true; |
372 | } |
373 | |
374 | return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; |
375 | } |
376 | |
377 | static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) |
378 | { |
379 | int ret; |
380 | u16 val; |
381 | |
382 | switch (ctrl) { |
383 | case ETH_TP_MDI_AUTO: |
384 | val = PHY_CTL1_AMDIX; |
385 | break; |
386 | case ETH_TP_MDI_X: |
387 | val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); |
388 | break; |
389 | case ETH_TP_MDI: |
390 | val = 0; |
391 | break; |
392 | default: |
393 | return 0; |
394 | } |
395 | |
396 | ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | |
397 | PHY_CTL1_MDICD, set: val); |
398 | if (ret < 0) |
399 | return ret; |
400 | |
401 | return genphy_c45_restart_aneg(phydev); |
402 | } |
403 | |
404 | static int gpy_config_aneg(struct phy_device *phydev) |
405 | { |
406 | bool changed = false; |
407 | u32 adv; |
408 | int ret; |
409 | |
410 | if (phydev->autoneg == AUTONEG_DISABLE) { |
411 | /* Configure half duplex with genphy_setup_forced, |
412 | * because genphy_c45_pma_setup_forced does not support. |
413 | */ |
414 | return phydev->duplex != DUPLEX_FULL |
415 | ? genphy_setup_forced(phydev) |
416 | : genphy_c45_pma_setup_forced(phydev); |
417 | } |
418 | |
419 | ret = gpy_config_mdix(phydev, ctrl: phydev->mdix_ctrl); |
420 | if (ret < 0) |
421 | return ret; |
422 | |
423 | ret = genphy_c45_an_config_aneg(phydev); |
424 | if (ret < 0) |
425 | return ret; |
426 | if (ret > 0) |
427 | changed = true; |
428 | |
429 | adv = linkmode_adv_to_mii_ctrl1000_t(advertising: phydev->advertising); |
430 | ret = phy_modify_changed(phydev, MII_CTRL1000, |
431 | ADVERTISE_1000FULL | ADVERTISE_1000HALF, |
432 | set: adv); |
433 | if (ret < 0) |
434 | return ret; |
435 | if (ret > 0) |
436 | changed = true; |
437 | |
438 | ret = genphy_c45_check_and_restart_aneg(phydev, restart: changed); |
439 | if (ret < 0) |
440 | return ret; |
441 | |
442 | if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || |
443 | phydev->interface == PHY_INTERFACE_MODE_INTERNAL) |
444 | return 0; |
445 | |
446 | /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is |
447 | * disabled. |
448 | */ |
449 | if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || |
450 | !gpy_sgmii_aneg_en(phydev)) |
451 | return 0; |
452 | |
453 | /* There is a design constraint in GPY2xx device where SGMII AN is |
454 | * only triggered when there is change of speed. If, PHY link |
455 | * partner`s speed is still same even after PHY TPI is down and up |
456 | * again, SGMII AN is not triggered and hence no new in-band message |
457 | * from GPY to MAC side SGMII. |
458 | * This could cause an issue during power up, when PHY is up prior to |
459 | * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII |
460 | * wouldn`t receive new in-band message from GPY with correct link |
461 | * status, speed and duplex info. |
462 | * |
463 | * 1) If PHY is already up and TPI link status is still down (such as |
464 | * hard reboot), TPI link status is polled for 4 seconds before |
465 | * retriggerring SGMII AN. |
466 | * 2) If PHY is already up and TPI link status is also up (such as soft |
467 | * reboot), polling of TPI link status is not needed and SGMII AN is |
468 | * immediately retriggered. |
469 | * 3) Other conditions such as PHY is down, speed change etc, skip |
470 | * retriggering SGMII AN. Note: in case of speed change, GPY FW will |
471 | * initiate SGMII AN. |
472 | */ |
473 | |
474 | if (phydev->state != PHY_UP) |
475 | return 0; |
476 | |
477 | ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, |
478 | 20000, 4000000, false); |
479 | if (ret == -ETIMEDOUT) |
480 | return 0; |
481 | else if (ret < 0) |
482 | return ret; |
483 | |
484 | /* Trigger SGMII AN. */ |
485 | return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, |
486 | VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); |
487 | } |
488 | |
489 | static int gpy_update_mdix(struct phy_device *phydev) |
490 | { |
491 | int ret; |
492 | |
493 | ret = phy_read(phydev, PHY_CTL1); |
494 | if (ret < 0) |
495 | return ret; |
496 | |
497 | if (ret & PHY_CTL1_AMDIX) |
498 | phydev->mdix_ctrl = ETH_TP_MDI_AUTO; |
499 | else |
500 | if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) |
501 | phydev->mdix_ctrl = ETH_TP_MDI_X; |
502 | else |
503 | phydev->mdix_ctrl = ETH_TP_MDI; |
504 | |
505 | ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); |
506 | if (ret < 0) |
507 | return ret; |
508 | |
509 | if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) |
510 | phydev->mdix = ETH_TP_MDI_X; |
511 | else |
512 | phydev->mdix = ETH_TP_MDI; |
513 | |
514 | return 0; |
515 | } |
516 | |
517 | static int gpy_update_interface(struct phy_device *phydev) |
518 | { |
519 | int ret; |
520 | |
521 | /* Interface mode is fixed for USXGMII and integrated PHY */ |
522 | if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || |
523 | phydev->interface == PHY_INTERFACE_MODE_INTERNAL) |
524 | return -EINVAL; |
525 | |
526 | /* Automatically switch SERDES interface between SGMII and 2500-BaseX |
527 | * according to speed. Disable ANEG in 2500-BaseX mode. |
528 | */ |
529 | switch (phydev->speed) { |
530 | case SPEED_2500: |
531 | phydev->interface = PHY_INTERFACE_MODE_2500BASEX; |
532 | ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, |
533 | VSPEC1_SGMII_CTRL_ANEN, set: 0); |
534 | if (ret < 0) { |
535 | phydev_err(phydev, |
536 | "Error: Disable of SGMII ANEG failed: %d\n" , |
537 | ret); |
538 | return ret; |
539 | } |
540 | break; |
541 | case SPEED_1000: |
542 | case SPEED_100: |
543 | case SPEED_10: |
544 | phydev->interface = PHY_INTERFACE_MODE_SGMII; |
545 | if (gpy_sgmii_aneg_en(phydev)) |
546 | break; |
547 | /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed |
548 | * if ANEG is disabled (in 2500-BaseX mode). |
549 | */ |
550 | ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, |
551 | VSPEC1_SGMII_ANEN_ANRS, |
552 | VSPEC1_SGMII_ANEN_ANRS); |
553 | if (ret < 0) { |
554 | phydev_err(phydev, |
555 | "Error: Enable of SGMII ANEG failed: %d\n" , |
556 | ret); |
557 | return ret; |
558 | } |
559 | break; |
560 | } |
561 | |
562 | if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { |
563 | ret = genphy_read_master_slave(phydev); |
564 | if (ret < 0) |
565 | return ret; |
566 | } |
567 | |
568 | return gpy_update_mdix(phydev); |
569 | } |
570 | |
571 | static int gpy_read_status(struct phy_device *phydev) |
572 | { |
573 | int ret; |
574 | |
575 | ret = genphy_update_link(phydev); |
576 | if (ret) |
577 | return ret; |
578 | |
579 | phydev->speed = SPEED_UNKNOWN; |
580 | phydev->duplex = DUPLEX_UNKNOWN; |
581 | phydev->pause = 0; |
582 | phydev->asym_pause = 0; |
583 | |
584 | if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { |
585 | ret = genphy_c45_read_lpa(phydev); |
586 | if (ret < 0) |
587 | return ret; |
588 | |
589 | /* Read the link partner's 1G advertisement */ |
590 | ret = phy_read(phydev, MII_STAT1000); |
591 | if (ret < 0) |
592 | return ret; |
593 | mii_stat1000_mod_linkmode_lpa_t(advertising: phydev->lp_advertising, lpa: ret); |
594 | } else if (phydev->autoneg == AUTONEG_DISABLE) { |
595 | linkmode_zero(dst: phydev->lp_advertising); |
596 | } |
597 | |
598 | ret = phy_read(phydev, PHY_MIISTAT); |
599 | if (ret < 0) |
600 | return ret; |
601 | |
602 | phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; |
603 | phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; |
604 | switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { |
605 | case PHY_MIISTAT_SPD_10: |
606 | phydev->speed = SPEED_10; |
607 | break; |
608 | case PHY_MIISTAT_SPD_100: |
609 | phydev->speed = SPEED_100; |
610 | break; |
611 | case PHY_MIISTAT_SPD_1000: |
612 | phydev->speed = SPEED_1000; |
613 | break; |
614 | case PHY_MIISTAT_SPD_2500: |
615 | phydev->speed = SPEED_2500; |
616 | break; |
617 | } |
618 | |
619 | if (phydev->link) { |
620 | ret = gpy_update_interface(phydev); |
621 | if (ret < 0) |
622 | return ret; |
623 | } |
624 | |
625 | return 0; |
626 | } |
627 | |
628 | static int gpy_config_intr(struct phy_device *phydev) |
629 | { |
630 | u16 mask = 0; |
631 | |
632 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
633 | mask = PHY_IMASK_MASK; |
634 | |
635 | return phy_write(phydev, PHY_IMASK, val: mask); |
636 | } |
637 | |
638 | static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) |
639 | { |
640 | int reg; |
641 | |
642 | reg = phy_read(phydev, PHY_ISTAT); |
643 | if (reg < 0) { |
644 | phy_error(phydev); |
645 | return IRQ_NONE; |
646 | } |
647 | |
648 | if (!(reg & PHY_IMASK_MASK)) |
649 | return IRQ_NONE; |
650 | |
651 | /* The PHY might leave the interrupt line asserted even after PHY_ISTAT |
652 | * is read. To avoid interrupt storms, delay the interrupt handling as |
653 | * long as the PHY drives the interrupt line. An internal bus read will |
654 | * stall as long as the interrupt line is asserted, thus just read a |
655 | * random register here. |
656 | * Because we cannot access the internal bus at all while the interrupt |
657 | * is driven by the PHY, there is no way to make the interrupt line |
658 | * unstuck (e.g. by changing the pinmux to GPIO input) during that time |
659 | * frame. Therefore, polling is the best we can do and won't do any more |
660 | * harm. |
661 | * It was observed that this bug happens on link state and link speed |
662 | * changes independent of the firmware version. |
663 | */ |
664 | if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) { |
665 | reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); |
666 | if (reg < 0) { |
667 | phy_error(phydev); |
668 | return IRQ_NONE; |
669 | } |
670 | } |
671 | |
672 | phy_trigger_machine(phydev); |
673 | |
674 | return IRQ_HANDLED; |
675 | } |
676 | |
677 | static int gpy_set_wol(struct phy_device *phydev, |
678 | struct ethtool_wolinfo *wol) |
679 | { |
680 | struct net_device *attach_dev = phydev->attached_dev; |
681 | int ret; |
682 | |
683 | if (wol->wolopts & WAKE_MAGIC) { |
684 | /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 |
685 | * VPSPEC2_WOL_AD45 = Byte0:Byte1 |
686 | * VPSPEC2_WOL_AD23 = Byte2:Byte3 |
687 | * VPSPEC2_WOL_AD01 = Byte4:Byte5 |
688 | */ |
689 | ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, |
690 | VPSPEC2_WOL_AD45, |
691 | val: ((attach_dev->dev_addr[0] << 8) | |
692 | attach_dev->dev_addr[1])); |
693 | if (ret < 0) |
694 | return ret; |
695 | |
696 | ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, |
697 | VPSPEC2_WOL_AD23, |
698 | val: ((attach_dev->dev_addr[2] << 8) | |
699 | attach_dev->dev_addr[3])); |
700 | if (ret < 0) |
701 | return ret; |
702 | |
703 | ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, |
704 | VPSPEC2_WOL_AD01, |
705 | val: ((attach_dev->dev_addr[4] << 8) | |
706 | attach_dev->dev_addr[5])); |
707 | if (ret < 0) |
708 | return ret; |
709 | |
710 | /* Enable the WOL interrupt */ |
711 | ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); |
712 | if (ret < 0) |
713 | return ret; |
714 | |
715 | /* Enable magic packet matching */ |
716 | ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, |
717 | VPSPEC2_WOL_CTL, |
718 | WOL_EN); |
719 | if (ret < 0) |
720 | return ret; |
721 | |
722 | /* Clear the interrupt status register. |
723 | * Only WoL is enabled so clear all. |
724 | */ |
725 | ret = phy_read(phydev, PHY_ISTAT); |
726 | if (ret < 0) |
727 | return ret; |
728 | } else { |
729 | /* Disable magic packet matching */ |
730 | ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, |
731 | VPSPEC2_WOL_CTL, |
732 | WOL_EN); |
733 | if (ret < 0) |
734 | return ret; |
735 | } |
736 | |
737 | if (wol->wolopts & WAKE_PHY) { |
738 | /* Enable the link state change interrupt */ |
739 | ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); |
740 | if (ret < 0) |
741 | return ret; |
742 | |
743 | /* Clear the interrupt status register */ |
744 | ret = phy_read(phydev, PHY_ISTAT); |
745 | if (ret < 0) |
746 | return ret; |
747 | |
748 | if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) |
749 | phy_trigger_machine(phydev); |
750 | |
751 | return 0; |
752 | } |
753 | |
754 | /* Disable the link state change interrupt */ |
755 | return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); |
756 | } |
757 | |
758 | static void gpy_get_wol(struct phy_device *phydev, |
759 | struct ethtool_wolinfo *wol) |
760 | { |
761 | int ret; |
762 | |
763 | wol->supported = WAKE_MAGIC | WAKE_PHY; |
764 | wol->wolopts = 0; |
765 | |
766 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); |
767 | if (ret & WOL_EN) |
768 | wol->wolopts |= WAKE_MAGIC; |
769 | |
770 | ret = phy_read(phydev, PHY_IMASK); |
771 | if (ret & PHY_IMASK_LSTC) |
772 | wol->wolopts |= WAKE_PHY; |
773 | } |
774 | |
775 | static int gpy_loopback(struct phy_device *phydev, bool enable) |
776 | { |
777 | struct gpy_priv *priv = phydev->priv; |
778 | u16 set = 0; |
779 | int ret; |
780 | |
781 | if (enable) { |
782 | u64 now = get_jiffies_64(); |
783 | |
784 | /* wait until 3 seconds from last disable */ |
785 | if (time_before64(now, priv->lb_dis_to)) |
786 | msleep(msecs: jiffies64_to_msecs(j: priv->lb_dis_to - now)); |
787 | |
788 | set = BMCR_LOOPBACK; |
789 | } |
790 | |
791 | ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set); |
792 | if (ret <= 0) |
793 | return ret; |
794 | |
795 | if (enable) { |
796 | /* It takes some time for PHY device to switch into |
797 | * loopback mode. |
798 | */ |
799 | msleep(msecs: 100); |
800 | } else { |
801 | priv->lb_dis_to = get_jiffies_64() + HZ * 3; |
802 | } |
803 | |
804 | return 0; |
805 | } |
806 | |
807 | static int gpy115_loopback(struct phy_device *phydev, bool enable) |
808 | { |
809 | struct gpy_priv *priv = phydev->priv; |
810 | |
811 | if (enable) |
812 | return gpy_loopback(phydev, enable); |
813 | |
814 | if (priv->fw_minor > 0x76) |
815 | return gpy_loopback(phydev, enable: 0); |
816 | |
817 | return genphy_soft_reset(phydev); |
818 | } |
819 | |
820 | static struct phy_driver gpy_drivers[] = { |
821 | { |
822 | PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), |
823 | .name = "Maxlinear Ethernet GPY2xx" , |
824 | .get_features = genphy_c45_pma_read_abilities, |
825 | .config_init = gpy_config_init, |
826 | .probe = gpy_probe, |
827 | .suspend = genphy_suspend, |
828 | .resume = genphy_resume, |
829 | .config_aneg = gpy_config_aneg, |
830 | .aneg_done = genphy_c45_aneg_done, |
831 | .read_status = gpy_read_status, |
832 | .config_intr = gpy_config_intr, |
833 | .handle_interrupt = gpy_handle_interrupt, |
834 | .set_wol = gpy_set_wol, |
835 | .get_wol = gpy_get_wol, |
836 | .set_loopback = gpy_loopback, |
837 | }, |
838 | { |
839 | .phy_id = PHY_ID_GPY115B, |
840 | .phy_id_mask = PHY_ID_GPYx15B_MASK, |
841 | .name = "Maxlinear Ethernet GPY115B" , |
842 | .get_features = genphy_c45_pma_read_abilities, |
843 | .config_init = gpy_config_init, |
844 | .probe = gpy_probe, |
845 | .suspend = genphy_suspend, |
846 | .resume = genphy_resume, |
847 | .config_aneg = gpy_config_aneg, |
848 | .aneg_done = genphy_c45_aneg_done, |
849 | .read_status = gpy_read_status, |
850 | .config_intr = gpy_config_intr, |
851 | .handle_interrupt = gpy_handle_interrupt, |
852 | .set_wol = gpy_set_wol, |
853 | .get_wol = gpy_get_wol, |
854 | .set_loopback = gpy115_loopback, |
855 | }, |
856 | { |
857 | PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), |
858 | .name = "Maxlinear Ethernet GPY115C" , |
859 | .get_features = genphy_c45_pma_read_abilities, |
860 | .config_init = gpy_config_init, |
861 | .probe = gpy_probe, |
862 | .suspend = genphy_suspend, |
863 | .resume = genphy_resume, |
864 | .config_aneg = gpy_config_aneg, |
865 | .aneg_done = genphy_c45_aneg_done, |
866 | .read_status = gpy_read_status, |
867 | .config_intr = gpy_config_intr, |
868 | .handle_interrupt = gpy_handle_interrupt, |
869 | .set_wol = gpy_set_wol, |
870 | .get_wol = gpy_get_wol, |
871 | .set_loopback = gpy115_loopback, |
872 | }, |
873 | { |
874 | .phy_id = PHY_ID_GPY211B, |
875 | .phy_id_mask = PHY_ID_GPY21xB_MASK, |
876 | .name = "Maxlinear Ethernet GPY211B" , |
877 | .get_features = genphy_c45_pma_read_abilities, |
878 | .config_init = gpy21x_config_init, |
879 | .probe = gpy_probe, |
880 | .suspend = genphy_suspend, |
881 | .resume = genphy_resume, |
882 | .config_aneg = gpy_config_aneg, |
883 | .aneg_done = genphy_c45_aneg_done, |
884 | .read_status = gpy_read_status, |
885 | .config_intr = gpy_config_intr, |
886 | .handle_interrupt = gpy_handle_interrupt, |
887 | .set_wol = gpy_set_wol, |
888 | .get_wol = gpy_get_wol, |
889 | .set_loopback = gpy_loopback, |
890 | }, |
891 | { |
892 | PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), |
893 | .name = "Maxlinear Ethernet GPY211C" , |
894 | .get_features = genphy_c45_pma_read_abilities, |
895 | .config_init = gpy21x_config_init, |
896 | .probe = gpy_probe, |
897 | .suspend = genphy_suspend, |
898 | .resume = genphy_resume, |
899 | .config_aneg = gpy_config_aneg, |
900 | .aneg_done = genphy_c45_aneg_done, |
901 | .read_status = gpy_read_status, |
902 | .config_intr = gpy_config_intr, |
903 | .handle_interrupt = gpy_handle_interrupt, |
904 | .set_wol = gpy_set_wol, |
905 | .get_wol = gpy_get_wol, |
906 | .set_loopback = gpy_loopback, |
907 | }, |
908 | { |
909 | .phy_id = PHY_ID_GPY212B, |
910 | .phy_id_mask = PHY_ID_GPY21xB_MASK, |
911 | .name = "Maxlinear Ethernet GPY212B" , |
912 | .get_features = genphy_c45_pma_read_abilities, |
913 | .config_init = gpy21x_config_init, |
914 | .probe = gpy_probe, |
915 | .suspend = genphy_suspend, |
916 | .resume = genphy_resume, |
917 | .config_aneg = gpy_config_aneg, |
918 | .aneg_done = genphy_c45_aneg_done, |
919 | .read_status = gpy_read_status, |
920 | .config_intr = gpy_config_intr, |
921 | .handle_interrupt = gpy_handle_interrupt, |
922 | .set_wol = gpy_set_wol, |
923 | .get_wol = gpy_get_wol, |
924 | .set_loopback = gpy_loopback, |
925 | }, |
926 | { |
927 | PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), |
928 | .name = "Maxlinear Ethernet GPY212C" , |
929 | .get_features = genphy_c45_pma_read_abilities, |
930 | .config_init = gpy21x_config_init, |
931 | .probe = gpy_probe, |
932 | .suspend = genphy_suspend, |
933 | .resume = genphy_resume, |
934 | .config_aneg = gpy_config_aneg, |
935 | .aneg_done = genphy_c45_aneg_done, |
936 | .read_status = gpy_read_status, |
937 | .config_intr = gpy_config_intr, |
938 | .handle_interrupt = gpy_handle_interrupt, |
939 | .set_wol = gpy_set_wol, |
940 | .get_wol = gpy_get_wol, |
941 | .set_loopback = gpy_loopback, |
942 | }, |
943 | { |
944 | .phy_id = PHY_ID_GPY215B, |
945 | .phy_id_mask = PHY_ID_GPYx15B_MASK, |
946 | .name = "Maxlinear Ethernet GPY215B" , |
947 | .get_features = genphy_c45_pma_read_abilities, |
948 | .config_init = gpy21x_config_init, |
949 | .probe = gpy_probe, |
950 | .suspend = genphy_suspend, |
951 | .resume = genphy_resume, |
952 | .config_aneg = gpy_config_aneg, |
953 | .aneg_done = genphy_c45_aneg_done, |
954 | .read_status = gpy_read_status, |
955 | .config_intr = gpy_config_intr, |
956 | .handle_interrupt = gpy_handle_interrupt, |
957 | .set_wol = gpy_set_wol, |
958 | .get_wol = gpy_get_wol, |
959 | .set_loopback = gpy_loopback, |
960 | }, |
961 | { |
962 | PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), |
963 | .name = "Maxlinear Ethernet GPY215C" , |
964 | .get_features = genphy_c45_pma_read_abilities, |
965 | .config_init = gpy21x_config_init, |
966 | .probe = gpy_probe, |
967 | .suspend = genphy_suspend, |
968 | .resume = genphy_resume, |
969 | .config_aneg = gpy_config_aneg, |
970 | .aneg_done = genphy_c45_aneg_done, |
971 | .read_status = gpy_read_status, |
972 | .config_intr = gpy_config_intr, |
973 | .handle_interrupt = gpy_handle_interrupt, |
974 | .set_wol = gpy_set_wol, |
975 | .get_wol = gpy_get_wol, |
976 | .set_loopback = gpy_loopback, |
977 | }, |
978 | { |
979 | PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), |
980 | .name = "Maxlinear Ethernet GPY241B" , |
981 | .get_features = genphy_c45_pma_read_abilities, |
982 | .config_init = gpy_config_init, |
983 | .probe = gpy_probe, |
984 | .suspend = genphy_suspend, |
985 | .resume = genphy_resume, |
986 | .config_aneg = gpy_config_aneg, |
987 | .aneg_done = genphy_c45_aneg_done, |
988 | .read_status = gpy_read_status, |
989 | .config_intr = gpy_config_intr, |
990 | .handle_interrupt = gpy_handle_interrupt, |
991 | .set_wol = gpy_set_wol, |
992 | .get_wol = gpy_get_wol, |
993 | .set_loopback = gpy_loopback, |
994 | }, |
995 | { |
996 | PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), |
997 | .name = "Maxlinear Ethernet GPY241BM" , |
998 | .get_features = genphy_c45_pma_read_abilities, |
999 | .config_init = gpy_config_init, |
1000 | .probe = gpy_probe, |
1001 | .suspend = genphy_suspend, |
1002 | .resume = genphy_resume, |
1003 | .config_aneg = gpy_config_aneg, |
1004 | .aneg_done = genphy_c45_aneg_done, |
1005 | .read_status = gpy_read_status, |
1006 | .config_intr = gpy_config_intr, |
1007 | .handle_interrupt = gpy_handle_interrupt, |
1008 | .set_wol = gpy_set_wol, |
1009 | .get_wol = gpy_get_wol, |
1010 | .set_loopback = gpy_loopback, |
1011 | }, |
1012 | { |
1013 | PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), |
1014 | .name = "Maxlinear Ethernet GPY245B" , |
1015 | .get_features = genphy_c45_pma_read_abilities, |
1016 | .config_init = gpy_config_init, |
1017 | .probe = gpy_probe, |
1018 | .suspend = genphy_suspend, |
1019 | .resume = genphy_resume, |
1020 | .config_aneg = gpy_config_aneg, |
1021 | .aneg_done = genphy_c45_aneg_done, |
1022 | .read_status = gpy_read_status, |
1023 | .config_intr = gpy_config_intr, |
1024 | .handle_interrupt = gpy_handle_interrupt, |
1025 | .set_wol = gpy_set_wol, |
1026 | .get_wol = gpy_get_wol, |
1027 | .set_loopback = gpy_loopback, |
1028 | }, |
1029 | }; |
1030 | module_phy_driver(gpy_drivers); |
1031 | |
1032 | static struct mdio_device_id __maybe_unused gpy_tbl[] = { |
1033 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, |
1034 | {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, |
1035 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, |
1036 | {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, |
1037 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, |
1038 | {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, |
1039 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, |
1040 | {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, |
1041 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, |
1042 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, |
1043 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, |
1044 | {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, |
1045 | { } |
1046 | }; |
1047 | MODULE_DEVICE_TABLE(mdio, gpy_tbl); |
1048 | |
1049 | MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver" ); |
1050 | MODULE_AUTHOR("Xu Liang" ); |
1051 | MODULE_LICENSE("GPL" ); |
1052 | |