1 | /* SPDX-License-Identifier: BSD-3-Clause-Clear */ |
2 | /* |
3 | * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2021-2022,2024 Qualcomm Innovation Center, Inc. All rights reserved. |
5 | */ |
6 | #ifndef _ATH11K_PCI_H |
7 | #define _ATH11K_PCI_H |
8 | |
9 | #include <linux/mhi.h> |
10 | |
11 | #include "core.h" |
12 | |
13 | #define PCIE_SOC_GLOBAL_RESET 0x3008 |
14 | #define PCIE_SOC_GLOBAL_RESET_V 1 |
15 | |
16 | #define WLAON_WARM_SW_ENTRY 0x1f80504 |
17 | #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c |
18 | |
19 | #define PCIE_Q6_COOKIE_ADDR 0x01f80500 |
20 | #define PCIE_Q6_COOKIE_DATA 0xc0000000 |
21 | |
22 | /* register to wake the UMAC from power collapse */ |
23 | #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 |
24 | |
25 | /* register used for handshake mechanism to validate UMAC is awake */ |
26 | #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 |
27 | |
28 | #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 |
29 | #define PARM_LTSSM_VALUE 0x111 |
30 | |
31 | #define GCC_GCC_PCIE_HOT_RST 0x1e402bc |
32 | #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 |
33 | |
34 | #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 |
35 | #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 |
36 | #define PCIE_INT_CLEAR_ALL 0xffffffff |
37 | |
38 | #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \ |
39 | (ab->hw_params.regs->pcie_qserdes_sysclk_en_sel) |
40 | #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 |
41 | #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff |
42 | #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \ |
43 | (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base) |
44 | #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 |
45 | #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \ |
46 | (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4) |
47 | #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 |
48 | #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \ |
49 | (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc) |
50 | #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff |
51 | #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff |
52 | |
53 | #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c |
54 | #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 |
55 | |
56 | enum ath11k_pci_flags { |
57 | ATH11K_PCI_ASPM_RESTORE, |
58 | }; |
59 | |
60 | struct ath11k_pci { |
61 | struct pci_dev *pdev; |
62 | struct ath11k_base *ab; |
63 | u16 dev_id; |
64 | char amss_path[100]; |
65 | struct mhi_controller *mhi_ctrl; |
66 | const struct ath11k_msi_config *msi_config; |
67 | u32 register_window; |
68 | |
69 | /* protects register_window above */ |
70 | spinlock_t window_lock; |
71 | |
72 | /* enum ath11k_pci_flags */ |
73 | unsigned long flags; |
74 | u16 link_ctl; |
75 | u64 dma_mask; |
76 | }; |
77 | |
78 | static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) |
79 | { |
80 | return (struct ath11k_pci *)ab->drv_priv; |
81 | } |
82 | |
83 | int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector); |
84 | #endif |
85 | |