1	/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2	/*
3	* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4	* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5	*/
6
7	#ifndef ATH12K_DP_H
8	#define ATH12K_DP_H
9
10	#include "hal_rx.h"
11	#include "hw.h"
12
13	#define MAX_RXDMA_PER_PDEV 2
14
15	struct ath12k_base;
16	struct ath12k_peer;
17	struct ath12k_dp;
18	struct ath12k_vif;
19	struct hal_tcl_status_ring;
20	struct ath12k_ext_irq_grp;
21
22	#define DP_MON_PURGE_TIMEOUT_MS 100
23	#define DP_MON_SERVICE_BUDGET 128
24
25	struct dp_srng {
26	u32 *vaddr_unaligned;
27	u32 *vaddr;
28	dma_addr_t paddr_unaligned;
29	dma_addr_t paddr;
30	int size;
31	u32 ring_id;
32	};
33
34	struct dp_rxdma_mon_ring {
35	struct dp_srng refill_buf_ring;
36	struct idr bufs_idr;
37	/* Protects bufs_idr */
38	spinlock_t idr_lock;
39	int bufs_max;
40	};
41
42	struct dp_rxdma_ring {
43	struct dp_srng refill_buf_ring;
44	int bufs_max;
45	};
46
47	#define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
48
49	struct dp_tx_ring {
50	u8 tcl_data_ring_id;
51	struct dp_srng tcl_data_ring;
52	struct dp_srng tcl_comp_ring;
53	struct hal_wbm_completion_ring_tx *tx_status;
54	int tx_status_head;
55	int tx_status_tail;
56	};
57
58	struct ath12k_pdev_mon_stats {
59	u32 status_ppdu_state;
60	u32 status_ppdu_start;
61	u32 status_ppdu_end;
62	u32 status_ppdu_compl;
63	u32 status_ppdu_start_mis;
64	u32 status_ppdu_end_mis;
65	u32 status_ppdu_done;
66	u32 dest_ppdu_done;
67	u32 dest_mpdu_done;
68	u32 dest_mpdu_drop;
69	u32 dup_mon_linkdesc_cnt;
70	u32 dup_mon_buf_cnt;
71	};
72
73	struct dp_link_desc_bank {
74	void *vaddr_unaligned;
75	void *vaddr;
76	dma_addr_t paddr_unaligned;
77	dma_addr_t paddr;
78	u32 size;
79	};
80
81	/* Size to enforce scatter idle list mode */
82	#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
83	#define DP_LINK_DESC_BANKS_MAX 8
84
85	#define DP_LINK_DESC_START 0x4000
86	#define DP_LINK_DESC_SHIFT 3
87
88	#define DP_LINK_DESC_COOKIE_SET(id, page) \
89	((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
90
91	#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
92
93	#define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
94	#define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
95	#define DP_RX_DESC_COOKIE_MAX \
96	(DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
97	#define DP_NOT_PPDU_ID_WRAP_AROUND 20000
98
99	enum ath12k_dp_ppdu_state {
100	DP_PPDU_STATUS_START,
101	DP_PPDU_STATUS_DONE,
102	};
103
104	struct dp_mon_mpdu {
105	struct list_head list;
106	struct sk_buff *head;
107	struct sk_buff *tail;
108	};
109
110	#define DP_MON_MAX_STATUS_BUF 32
111
112	struct ath12k_mon_data {
113	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
114	struct hal_rx_mon_ppdu_info mon_ppdu_info;
115
116	u32 mon_ppdu_status;
117	u32 mon_last_buf_cookie;
118	u64 mon_last_linkdesc_paddr;
119	u16 chan_noise_floor;
120
121	struct ath12k_pdev_mon_stats rx_mon_stats;
122	/* lock for monitor data */
123	spinlock_t mon_lock;
124	struct sk_buff_head rx_status_q;
125	struct dp_mon_mpdu *mon_mpdu;
126	struct list_head dp_rx_mon_mpdu_list;
127	struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF];
128	struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;
129	struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;
130	};
131
132	struct ath12k_pdev_dp {
133	u32 mac_id;
134	atomic_t num_tx_pending;
135	wait_queue_head_t tx_empty_waitq;
136	struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
137	struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
138
139	struct ieee80211_rx_status rx_status;
140	struct ath12k_mon_data mon_data;
141	};
142
143	#define DP_NUM_CLIENTS_MAX 64
144	#define DP_AVG_TIDS_PER_CLIENT 2
145	#define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
146	#define DP_AVG_MSDUS_PER_FLOW 128
147	#define DP_AVG_FLOWS_PER_TID 2
148	#define DP_AVG_MPDUS_PER_TID_MAX 128
149	#define DP_AVG_MSDUS_PER_MPDU 4
150
151	#define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
152
153	#define DP_BA_WIN_SZ_MAX 1024
154
155	#define DP_TCL_NUM_RING_MAX 4
156
157	#define DP_IDLE_SCATTER_BUFS_MAX 16
158
159	#define DP_WBM_RELEASE_RING_SIZE 64
160	#define DP_TCL_DATA_RING_SIZE 512
161	#define DP_TX_COMP_RING_SIZE 32768
162	#define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
163	#define DP_TCL_CMD_RING_SIZE 32
164	#define DP_TCL_STATUS_RING_SIZE 32
165	#define DP_REO_DST_RING_MAX 8
166	#define DP_REO_DST_RING_SIZE 2048
167	#define DP_REO_REINJECT_RING_SIZE 32
168	#define DP_RX_RELEASE_RING_SIZE 1024
169	#define DP_REO_EXCEPTION_RING_SIZE 128
170	#define DP_REO_CMD_RING_SIZE 128
171	#define DP_REO_STATUS_RING_SIZE 2048
172	#define DP_RXDMA_BUF_RING_SIZE 4096
173	#define DP_RX_MAC_BUF_RING_SIZE 2048
174	#define DP_RXDMA_REFILL_RING_SIZE 2048
175	#define DP_RXDMA_ERR_DST_RING_SIZE 1024
176	#define DP_RXDMA_MON_STATUS_RING_SIZE 1024
177	#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
178	#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
179	#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
180	#define DP_TX_MONITOR_BUF_RING_SIZE 4096
181	#define DP_TX_MONITOR_DEST_RING_SIZE 2048
182
183	#define DP_TX_MONITOR_BUF_SIZE 2048
184	#define DP_TX_MONITOR_BUF_SIZE_MIN 48
185	#define DP_TX_MONITOR_BUF_SIZE_MAX 8192
186
187	#define DP_RX_BUFFER_SIZE 2048
188	#define DP_RX_BUFFER_SIZE_LITE 1024
189	#define DP_RX_BUFFER_ALIGN_SIZE 128
190
191	#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
192	#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18)
193
194	#define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
195	#define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
196
197	#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
198	#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
199	#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
200
201	#define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
202	#define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10
203
204	#define ATH12K_NUM_POOL_TX_DESC 32768
205
206	/* TODO: revisit this count during testing */
207	#define ATH12K_RX_DESC_COUNT (12288)
208
209	#define ATH12K_PAGE_SIZE PAGE_SIZE
210
211	/* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
212	* SPT pages which makes lower 12bits 0
213	*/
214	#define ATH12K_MAX_PPT_ENTRIES 1024
215
216	/* Total 512 entries in a SPT, i.e 4K Page/8 */
217	#define ATH12K_MAX_SPT_ENTRIES 512
218
219	#define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)
220
221	#define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \
222	ATH12K_MAX_SPT_ENTRIES)
223	#define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)
224	#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)
225
226	/* The SPT pages are divided for RX and TX, first block for RX
227	* and remaining for TX
228	*/
229	#define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES
230
231	#define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA
232
233	/* 4K aligned address have last 12 bits set to 0, this check is done
234	* so that two spt pages address can be stored per 8bytes
235	* of CMEM (PPT)
236	*/
237	#define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
238	#define ATH12K_SPT_4K_ALIGN_OFFSET 12
239	#define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
240
241	/* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
242	#define ATH12K_CMEM_ADDR_MSB 0x10
243
244	/* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
245	#define ATH12K_CC_SPT_MSB 8
246	#define ATH12K_CC_PPT_MSB 19
247	#define ATH12K_CC_PPT_SHIFT 9
248	#define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0)
249	#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
250
251	#define DP_REO_QREF_NUM GENMASK(31, 16)
252	#define DP_MAX_PEER_ID 2047
253
254	/* Total size of the LUT is based on 2K peers, each having reference
255	* for 17tids, note each entry is of type ath12k_reo_queue_ref
256	* hence total size is 2048 * 17 * 8 = 278528
257	*/
258	#define DP_REOQ_LUT_SIZE 278528
259
260	/* Invalid TX Bank ID value */
261	#define DP_INVALID_BANK_ID -1
262
263	struct ath12k_dp_tx_bank_profile {
264	u8 is_configured;
265	u32 num_users;
266	u32 bank_config;
267	};
268
269	struct ath12k_hp_update_timer {
270	struct timer_list timer;
271	bool started;
272	bool init;
273	u32 tx_num;
274	u32 timer_tx_num;
275	u32 ring_id;
276	u32 interval;
277	struct ath12k_base *ab;
278	};
279
280	struct ath12k_rx_desc_info {
281	struct list_head list;
282	struct sk_buff *skb;
283	u32 cookie;
284	u32 magic;
285	};
286
287	struct ath12k_tx_desc_info {
288	struct list_head list;
289	struct sk_buff *skb;
290	u32 desc_id; /* Cookie */
291	u8 mac_id;
292	u8 pool_id;
293	};
294
295	struct ath12k_spt_info {
296	dma_addr_t paddr;
297	u64 *vaddr;
298	struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];
299	struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];
300	};
301
302	struct ath12k_reo_queue_ref {
303	u32 info0;
304	u32 info1;
305	} __packed;
306
307	struct ath12k_reo_q_addr_lut {
308	dma_addr_t paddr;
309	u32 *vaddr;
310	};
311
312	struct ath12k_dp {
313	struct ath12k_base *ab;
314	u8 num_bank_profiles;
315	/* protects the access and update of bank_profiles */
316	spinlock_t tx_bank_lock;
317	struct ath12k_dp_tx_bank_profile *bank_profiles;
318	enum ath12k_htc_ep_id eid;
319	struct completion htt_tgt_version_received;
320	u8 htt_tgt_ver_major;
321	u8 htt_tgt_ver_minor;
322	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
323	struct dp_srng wbm_idle_ring;
324	struct dp_srng wbm_desc_rel_ring;
325	struct dp_srng tcl_cmd_ring;
326	struct dp_srng tcl_status_ring;
327	struct dp_srng reo_reinject_ring;
328	struct dp_srng rx_rel_ring;
329	struct dp_srng reo_except_ring;
330	struct dp_srng reo_cmd_ring;
331	struct dp_srng reo_status_ring;
332	struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
333	struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
334	struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
335	struct list_head reo_cmd_list;
336	struct list_head reo_cmd_cache_flush_list;
337	u32 reo_cmd_cache_flush_count;
338
339	/* protects access to below fields,
340	* - reo_cmd_list
341	* - reo_cmd_cache_flush_list
342	* - reo_cmd_cache_flush_count
343	*/
344	spinlock_t reo_cmd_lock;
345	struct ath12k_hp_update_timer reo_cmd_timer;
346	struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
347	struct ath12k_spt_info *spt_info;
348	u32 num_spt_pages;
349	struct list_head rx_desc_free_list;
350	struct list_head rx_desc_used_list;
351	/* protects the free and used desc list */
352	spinlock_t rx_desc_lock;
353
354	struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
355	struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
356	/* protects the free and used desc lists */
357	spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
358
359	struct dp_rxdma_ring rx_refill_buf_ring;
360	struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
361	struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
362	struct dp_rxdma_mon_ring rxdma_mon_buf_ring;
363	struct dp_rxdma_mon_ring tx_mon_buf_ring;
364	struct ath12k_reo_q_addr_lut reoq_lut;
365	};
366
367	/* HTT definitions */
368
369	#define HTT_TCL_META_DATA_TYPE BIT(0)
370	#define HTT_TCL_META_DATA_VALID_HTT BIT(1)
371
372	/* vdev meta data */
373	#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
374	#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
375	#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
376
377	/* peer meta data */
378	#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
379
380	#define HTT_TX_WBM_COMP_STATUS_OFFSET 8
381
382	/* HTT tx completion is overlaid in wbm_release_ring */
383	#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13)
384	#define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)
385	#define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)
386
387	#define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24)
388
389	struct htt_tx_wbm_completion {
390	__le32 rsvd0[2];
391	__le32 info0;
392	__le32 info1;
393	__le32 info2;
394	__le32 info3;
395	__le32 info4;
396	__le32 rsvd1;
397
398	} __packed;
399
400	enum htt_h2t_msg_type {
401	HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
402	HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
403	HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
404	HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
405	HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
406	HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a,
407	HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
408	};
409
410	#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
411
412	struct htt_ver_req_cmd {
413	__le32 ver_reg_info;
414	} __packed;
415
416	enum htt_srng_ring_type {
417	HTT_HW_TO_SW_RING,
418	HTT_SW_TO_HW_RING,
419	HTT_SW_TO_SW_RING,
420	};
421
422	enum htt_srng_ring_id {
423	HTT_RXDMA_HOST_BUF_RING,
424	HTT_RXDMA_MONITOR_STATUS_RING,
425	HTT_RXDMA_MONITOR_BUF_RING,
426	HTT_RXDMA_MONITOR_DESC_RING,
427	HTT_RXDMA_MONITOR_DEST_RING,
428	HTT_HOST1_TO_FW_RXBUF_RING,
429	HTT_HOST2_TO_FW_RXBUF_RING,
430	HTT_RXDMA_NON_MONITOR_DEST_RING,
431	HTT_TX_MON_HOST2MON_BUF_RING,
432	HTT_TX_MON_MON2HOST_DEST_RING,
433	};
434
435	/* host -> target HTT_SRING_SETUP message
436	*
437	* After target is booted up, Host can send SRING setup message for
438	* each host facing LMAC SRING. Target setups up HW registers based
439	* on setup message and confirms back to Host if response_required is set.
440	* Host should wait for confirmation message before sending new SRING
441	* setup message
442	*
443	* The message would appear as follows:
444	*
445	* |31 24|23 20|19|18 16|15|14 8|7 0|
446	* |--------------- +-----------------+----------------+------------------|
447	* | ring_type | ring_id | pdev_id | msg_type |
448	* |----------------------------------------------------------------------|
449	* | ring_base_addr_lo |
450	* |----------------------------------------------------------------------|
451	* | ring_base_addr_hi |
452	* |----------------------------------------------------------------------|
453	* |ring_misc_cfg_flag|ring_entry_size| ring_size |
454	* |----------------------------------------------------------------------|
455	* | ring_head_offset32_remote_addr_lo |
456	* |----------------------------------------------------------------------|
457	* | ring_head_offset32_remote_addr_hi |
458	* |----------------------------------------------------------------------|
459	* | ring_tail_offset32_remote_addr_lo |
460	* |----------------------------------------------------------------------|
461	* | ring_tail_offset32_remote_addr_hi |
462	* |----------------------------------------------------------------------|
463	* | ring_msi_addr_lo |
464	* |----------------------------------------------------------------------|
465	* | ring_msi_addr_hi |
466	* |----------------------------------------------------------------------|
467	* | ring_msi_data |
468	* |----------------------------------------------------------------------|
469	* | intr_timer_th |IM| intr_batch_counter_th |
470	* |----------------------------------------------------------------------|
471	* | reserved |RR|PTCF| intr_low_threshold |
472	* |----------------------------------------------------------------------|
473	* Where
474	* IM = sw_intr_mode
475	* RR = response_required
476	* PTCF = prefetch_timer_cfg
477	*
478	* The message is interpreted as follows:
479	* dword0 - b'0:7 - msg_type: This will be set to
480	* HTT_H2T_MSG_TYPE_SRING_SETUP
481	* b'8:15 - pdev_id:
482	* 0 (for rings at SOC/UMAC level),
483	* 1/2/3 mac id (for rings at LMAC level)
484	* b'16:23 - ring_id: identify which ring is to setup,
485	* more details can be got from enum htt_srng_ring_id
486	* b'24:31 - ring_type: identify type of host rings,
487	* more details can be got from enum htt_srng_ring_type
488	* dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
489	* dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
490	* dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
491	* b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
492	* b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
493	* SW_TO_HW_RING.
494	* Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
495	* dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
496	* Lower 32 bits of memory address of the remote variable
497	* storing the 4-byte word offset that identifies the head
498	* element within the ring.
499	* (The head offset variable has type u32.)
500	* Valid for HW_TO_SW and SW_TO_SW rings.
501	* dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
502	* Upper 32 bits of memory address of the remote variable
503	* storing the 4-byte word offset that identifies the head
504	* element within the ring.
505	* (The head offset variable has type u32.)
506	* Valid for HW_TO_SW and SW_TO_SW rings.
507	* dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
508	* Lower 32 bits of memory address of the remote variable
509	* storing the 4-byte word offset that identifies the tail
510	* element within the ring.
511	* (The tail offset variable has type u32.)
512	* Valid for HW_TO_SW and SW_TO_SW rings.
513	* dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
514	* Upper 32 bits of memory address of the remote variable
515	* storing the 4-byte word offset that identifies the tail
516	* element within the ring.
517	* (The tail offset variable has type u32.)
518	* Valid for HW_TO_SW and SW_TO_SW rings.
519	* dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
520	* valid only for HW_TO_SW_RING and SW_TO_HW_RING
521	* dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
522	* valid only for HW_TO_SW_RING and SW_TO_HW_RING
523	* dword10 - b'0:31 - ring_msi_data: MSI data
524	* Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
525	* valid only for HW_TO_SW_RING and SW_TO_HW_RING
526	* dword11 - b'0:14 - intr_batch_counter_th:
527	* batch counter threshold is in units of 4-byte words.
528	* HW internally maintains and increments batch count.
529	* (see SRING spec for detail description).
530	* When batch count reaches threshold value, an interrupt
531	* is generated by HW.
532	* b'15 - sw_intr_mode:
533	* This configuration shall be static.
534	* Only programmed at power up.
535	* 0: generate pulse style sw interrupts
536	* 1: generate level style sw interrupts
537	* b'16:31 - intr_timer_th:
538	* The timer init value when timer is idle or is
539	* initialized to start downcounting.
540	* In 8us units (to cover a range of 0 to 524 ms)
541	* dword12 - b'0:15 - intr_low_threshold:
542	* Used only by Consumer ring to generate ring_sw_int_p.
543	* Ring entries low threshold water mark, that is used
544	* in combination with the interrupt timer as well as
545	* the clearing of the level interrupt.
546	* b'16:18 - prefetch_timer_cfg:
547	* Used only by Consumer ring to set timer mode to
548	* support Application prefetch handling.
549	* The external tail offset/pointer will be updated
550	* at following intervals:
551	* 3'b000: (Prefetch feature disabled; used only for debug)
552	* 3'b001: 1 usec
553	* 3'b010: 4 usec
554	* 3'b011: 8 usec (default)
555	* 3'b100: 16 usec
556	* Others: Reserved
557	* b'19 - response_required:
558	* Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
559	* b'20:31 - reserved: reserved for future use
560	*/
561
562	#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
563	#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
564	#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
565	#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
566
567	#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
568	#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
569	#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
570	#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
571	#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
572	#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
573
574	#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
575	#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
576	#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
577
578	#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
579	#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16)
580	#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
581
582	struct htt_srng_setup_cmd {
583	__le32 info0;
584	__le32 ring_base_addr_lo;
585	__le32 ring_base_addr_hi;
586	__le32 info1;
587	__le32 ring_head_off32_remote_addr_lo;
588	__le32 ring_head_off32_remote_addr_hi;
589	__le32 ring_tail_off32_remote_addr_lo;
590	__le32 ring_tail_off32_remote_addr_hi;
591	__le32 ring_msi_addr_lo;
592	__le32 ring_msi_addr_hi;
593	__le32 msi_data;
594	__le32 intr_info;
595	__le32 info2;
596	} __packed;
597
598	/* host -> target FW PPDU_STATS config message
599	*
600	* @details
601	* The following field definitions describe the format of the HTT host
602	* to target FW for PPDU_STATS_CFG msg.
603	* The message allows the host to configure the PPDU_STATS_IND messages
604	* produced by the target.
605	*
606	* |31 24|23 16|15 8|7 0|
607	* |-----------------------------------------------------------|
608	* | REQ bit mask | pdev_mask | msg type |
609	* |-----------------------------------------------------------|
610	* Header fields:
611	* - MSG_TYPE
612	* Bits 7:0
613	* Purpose: identifies this is a req to configure ppdu_stats_ind from target
614	* Value: 0x11
615	* - PDEV_MASK
616	* Bits 8:15
617	* Purpose: identifies which pdevs this PPDU stats configuration applies to
618	* Value: This is a overloaded field, refer to usage and interpretation of
619	* PDEV in interface document.
620	* Bit 8 : Reserved for SOC stats
621	* Bit 9 - 15 : Indicates PDEV_MASK in DBDC
622	* Indicates MACID_MASK in DBS
623	* - REQ_TLV_BIT_MASK
624	* Bits 16:31
625	* Purpose: each set bit indicates the corresponding PPDU stats TLV type
626	* needs to be included in the target's PPDU_STATS_IND messages.
627	* Value: refer htt_ppdu_stats_tlv_tag_t <<<???
628	*
629	*/
630
631	struct htt_ppdu_stats_cfg_cmd {
632	__le32 msg;
633	} __packed;
634
635	#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
636	#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8)
637	#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
638
639	enum htt_ppdu_stats_tag_type {
640	HTT_PPDU_STATS_TAG_COMMON,
641	HTT_PPDU_STATS_TAG_USR_COMMON,
642	HTT_PPDU_STATS_TAG_USR_RATE,
643	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
644	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
645	HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
646	HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
647	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
648	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
649	HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
650	HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
651	HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
652	HTT_PPDU_STATS_TAG_INFO,
653	HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
654
655	/* New TLV's are added above to this line */
656	HTT_PPDU_STATS_TAG_MAX,
657	};
658
659	#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
660	| BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
661	| BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
662	| BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
663	| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
664	| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
665	| BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
666	| BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
667
668	#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
669	BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
670	BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
671	BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
672	BIT(HTT_PPDU_STATS_TAG_INFO) | \
673	BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
674	HTT_PPDU_STATS_TAG_DEFAULT)
675
676	enum htt_stats_internal_ppdu_frametype {
677	HTT_STATS_PPDU_FTYPE_CTRL,
678	HTT_STATS_PPDU_FTYPE_DATA,
679	HTT_STATS_PPDU_FTYPE_BAR,
680	HTT_STATS_PPDU_FTYPE_MAX
681	};
682
683	/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
684	*
685	* details:
686	* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
687	* configure RXDMA rings.
688	* The configuration is per ring based and includes both packet subtypes
689	* and PPDU/MPDU TLVs.
690	*
691	* The message would appear as follows:
692	*
693	* |31 26|25|24|23 16|15 8|7 0|
694	* |-----------------+----------------+----------------+---------------|
695	* | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
696	* |-------------------------------------------------------------------|
697	* | rsvd2 | ring_buffer_size |
698	* |-------------------------------------------------------------------|
699	* | packet_type_enable_flags_0 |
700	* |-------------------------------------------------------------------|
701	* | packet_type_enable_flags_1 |
702	* |-------------------------------------------------------------------|
703	* | packet_type_enable_flags_2 |
704	* |-------------------------------------------------------------------|
705	* | packet_type_enable_flags_3 |
706	* |-------------------------------------------------------------------|
707	* | tlv_filter_in_flags |
708	* |-------------------------------------------------------------------|
709	* Where:
710	* PS = pkt_swap
711	* SS = status_swap
712	* The message is interpreted as follows:
713	* dword0 - b'0:7 - msg_type: This will be set to
714	* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
715	* b'8:15 - pdev_id:
716	* 0 (for rings at SOC/UMAC level),
717	* 1/2/3 mac id (for rings at LMAC level)
718	* b'16:23 - ring_id : Identify the ring to configure.
719	* More details can be got from enum htt_srng_ring_id
720	* b'24 - status_swap: 1 is to swap status TLV
721	* b'25 - pkt_swap: 1 is to swap packet TLV
722	* b'26:31 - rsvd1: reserved for future use
723	* dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring,
724	* in byte units.
725	* Valid only for HW_TO_SW_RING and SW_TO_HW_RING
726	* - b'16:31 - rsvd2: Reserved for future use
727	* dword2 - b'0:31 - packet_type_enable_flags_0:
728	* Enable MGMT packet from 0b0000 to 0b1001
729	* bits from low to high: FP, MD, MO - 3 bits
730	* FP: Filter_Pass
731	* MD: Monitor_Direct
732	* MO: Monitor_Other
733	* 10 mgmt subtypes * 3 bits -> 30 bits
734	* Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
735	* dword3 - b'0:31 - packet_type_enable_flags_1:
736	* Enable MGMT packet from 0b1010 to 0b1111
737	* bits from low to high: FP, MD, MO - 3 bits
738	* Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
739	* dword4 - b'0:31 - packet_type_enable_flags_2:
740	* Enable CTRL packet from 0b0000 to 0b1001
741	* bits from low to high: FP, MD, MO - 3 bits
742	* Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
743	* dword5 - b'0:31 - packet_type_enable_flags_3:
744	* Enable CTRL packet from 0b1010 to 0b1111,
745	* MCAST_DATA, UCAST_DATA, NULL_DATA
746	* bits from low to high: FP, MD, MO - 3 bits
747	* Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
748	* dword6 - b'0:31 - tlv_filter_in_flags:
749	* Filter in Attention/MPDU/PPDU/Header/User tlvs
750	* Refer to CFG_TLV_FILTER_IN_FLAG defs
751	*/
752
753	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
754	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
755	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
756	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
757	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
758	#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
759	#define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26)
760
761	#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0)
762	#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16)
763	#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0)
764	#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16)
765	#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0)
766	#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16)
767	#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0)
768
769	#define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23)
770	#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0)
771	#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16)
772	#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0)
773
774	enum htt_rx_filter_tlv_flags {
775	HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
776	HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
777	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
778	HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
779	HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
780	HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
781	HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
782	HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
783	HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
784	HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
785	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
786	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
787	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
788	};
789
790	enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
791	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
792	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
793	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
794	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
795	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
796	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
797	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
798	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
799	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
800	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
801	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
802	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
803	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
804	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
805	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
806	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
807	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
808	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
809	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
810	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
811	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
812	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
813	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
814	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
815	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
816	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
817	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
818	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
819	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
820	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
821	};
822
823	enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
824	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
825	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
826	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
827	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
828	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
829	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
830	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
831	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
832	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
833	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
834	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
835	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
836	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
837	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
838	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
839	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
840	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
841	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
842	};
843
844	enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
845	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
846	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
847	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
848	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
849	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
850	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
851	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
852	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
853	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
854	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
855	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
856	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
857	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
858	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
859	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
860	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
861	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
862	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
863	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
864	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
865	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
866	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
867	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
868	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
869	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
870	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
871	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
872	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
873	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
874	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
875	};
876
877	enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
878	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
879	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
880	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
881	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
882	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
883	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
884	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
885	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
886	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
887	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
888	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
889	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
890	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
891	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
892	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
893	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
894	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
895	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
896	};
897
898	enum htt_rx_data_pkt_filter_tlv_flasg3 {
899	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
900	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
901	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
902	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
903	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
904	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
905	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
906	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
907	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
908	};
909
910	#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
911	(HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
912	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
913	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
914	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
915	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
916	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
917	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
918	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
919	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
920
921	#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
922	(HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
923	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
924	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
925	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
926	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
927	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
928	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
929	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
930	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
931
932	#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
933	(HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
934	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
935	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
936	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
937	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
938	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
939	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
940	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
941	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
942
943	#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
944	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
945	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
946	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
947	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
948
949	#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
950	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
951	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
952	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
953	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
954
955	#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
956	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
957	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
958	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
959	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
960
961	#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
962	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
963	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
964
965	#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
966	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
967	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
968
969	#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
970	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
971	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
972
973	#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
974	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
975	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
976	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
977	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
978	| HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
979
980	#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
981	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
982	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
983	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
984	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
985	| HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
986
987	#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
988	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
989	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
990	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
991	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
992	| HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
993
994	#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
995	| HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
996	| HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
997
998	#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
999	| HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1000	| HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1001
1002	#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
1003	| HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
1004	| HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
1005
1006	#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
1007	(HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
1008	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1009
1010	#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
1011	(HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
1012	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1013
1014	#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
1015	(HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
1016	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1017
1018	#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
1019	(HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
1020	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1021
1022	#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
1023	(HTT_RX_FP_CTRL_FILTER_FLASG2 | \
1024	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1025	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1026	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1027	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1028	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1029	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1030	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1031
1032	#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
1033	(HTT_RX_MO_CTRL_FILTER_FLASG2 | \
1034	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1035	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1036	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1037	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1038	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1039	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1040	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1041
1042	#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
1043
1044	#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
1045
1046	#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
1047
1048	#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
1049
1050	#define HTT_RX_MON_FILTER_TLV_FLAGS \
1051	(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1052	HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1053	HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1054	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1055	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1056	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1057
1058	#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
1059	(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1060	HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1061	HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1062	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1063	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1064	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1065
1066	#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
1067	(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1068	HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1069	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1070	HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1071	HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1072	HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1073	HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1074	HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
1075
1076	/* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
1077	#define HTT_RX_TLV_FLAGS_RXDMA_RING \
1078	(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1079	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1080	HTT_RX_FILTER_TLV_FLAGS_MSDU_END)
1081
1082	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1083	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1084
1085	struct htt_rx_ring_selection_cfg_cmd {
1086	__le32 info0;
1087	__le32 info1;
1088	__le32 pkt_type_en_flags0;
1089	__le32 pkt_type_en_flags1;
1090	__le32 pkt_type_en_flags2;
1091	__le32 pkt_type_en_flags3;
1092	__le32 rx_filter_tlv;
1093	__le32 rx_packet_offset;
1094	__le32 rx_mpdu_offset;
1095	__le32 rx_msdu_offset;
1096	__le32 rx_attn_offset;
1097	__le32 info2;
1098	__le32 reserved[2];
1099	__le32 rx_mpdu_start_end_mask;
1100	__le32 rx_msdu_end_word_mask;
1101	__le32 info3;
1102	} __packed;
1103
1104	struct htt_rx_ring_tlv_filter {
1105	u32 rx_filter; /* see htt_rx_filter_tlv_flags */
1106	u32 pkt_filter_flags0; /* MGMT */
1107	u32 pkt_filter_flags1; /* MGMT */
1108	u32 pkt_filter_flags2; /* CTRL */
1109	u32 pkt_filter_flags3; /* DATA */
1110	bool offset_valid;
1111	u16 rx_packet_offset;
1112	u16 rx_header_offset;
1113	u16 rx_mpdu_end_offset;
1114	u16 rx_mpdu_start_offset;
1115	u16 rx_msdu_end_offset;
1116	u16 rx_msdu_start_offset;
1117	u16 rx_attn_offset;
1118	u16 rx_mpdu_start_wmask;
1119	u16 rx_mpdu_end_wmask;
1120	u32 rx_msdu_end_wmask;
1121	};
1122
1123	#define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0
1124	#define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1
1125	#define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2
1126	#define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3
1127
1128	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
1129	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
1130	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
1131	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
1132	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
1133
1134	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0)
1135	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16)
1136	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19)
1137	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22)
1138	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25)
1139
1140	#define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0)
1141
1142	struct htt_tx_ring_selection_cfg_cmd {
1143	__le32 info0;
1144	__le32 info1;
1145	__le32 info2;
1146	__le32 tlv_filter_mask_in0;
1147	__le32 tlv_filter_mask_in1;
1148	__le32 tlv_filter_mask_in2;
1149	__le32 tlv_filter_mask_in3;
1150	__le32 reserved[3];
1151	} __packed;
1152
1153	#define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)
1154	#define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4)
1155	#define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8)
1156
1157	#define HTT_TX_MON_FILTER_HYBRID_MODE \
1158	(HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \
1159	HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \
1160	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \
1161	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \
1162	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \
1163	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \
1164	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \
1165	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \
1166	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \
1167	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \
1168	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \
1169	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \
1170	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)
1171
1172	struct htt_tx_ring_tlv_filter {
1173	u32 tx_mon_downstream_tlv_flags;
1174	u32 tx_mon_upstream_tlv_flags0;
1175	u32 tx_mon_upstream_tlv_flags1;
1176	u32 tx_mon_upstream_tlv_flags2;
1177	bool tx_mon_mgmt_filter;
1178	bool tx_mon_data_filter;
1179	bool tx_mon_ctrl_filter;
1180	u16 tx_mon_pkt_dma_len;
1181	} __packed;
1182
1183	enum htt_tx_mon_upstream_tlv_flags0 {
1184	HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),
1185	HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),
1186	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),
1187	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),
1188	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),
1189	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),
1190	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),
1191	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),
1192	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),
1193	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),
1194	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),
1195	HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),
1196	HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),
1197	HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),
1198	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),
1199	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),
1200	};
1201
1202	#define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)
1203
1204	/* HTT message target->host */
1205
1206	enum htt_t2h_msg_type {
1207	HTT_T2H_MSG_TYPE_VERSION_CONF,
1208	HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
1209	HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
1210	HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
1211	HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
1212	HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
1213	HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
1214	HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
1215	HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1216	HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1217	HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1218	HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
1219	HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b,
1220	HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,
1221	};
1222
1223	#define HTT_TARGET_VERSION_MAJOR 3
1224
1225	#define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1226	#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
1227	#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
1228
1229	struct htt_t2h_version_conf_msg {
1230	__le32 version;
1231	} __packed;
1232
1233	#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
1234	#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
1235	#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
1236	#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
1237	#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
1238	#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1239	#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
1240
1241	struct htt_t2h_peer_map_event {
1242	__le32 info;
1243	__le32 mac_addr_l32;
1244	__le32 info1;
1245	__le32 info2;
1246	} __packed;
1247
1248	#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
1249	#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
1250	#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1251	HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1252	#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1253	#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1254
1255	struct htt_t2h_peer_unmap_event {
1256	__le32 info;
1257	__le32 mac_addr_l32;
1258	__le32 info1;
1259	} __packed;
1260
1261	struct htt_resp_msg {
1262	union {
1263	struct htt_t2h_version_conf_msg version_msg;
1264	struct htt_t2h_peer_map_event peer_map_ev;
1265	struct htt_t2h_peer_unmap_event peer_unmap_ev;
1266	};
1267	} __packed;
1268
1269	#define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\
1270	(((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))
1271	#define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0)
1272	#define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8)
1273	#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16)
1274	#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0)
1275	#define HTT_VDEV_TXRX_STATS_COMMON_TLV 0
1276	#define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1
1277
1278	struct htt_t2h_vdev_txrx_stats_ind {
1279	__le32 vdev_id;
1280	__le32 rx_msdu_byte_cnt_lo;
1281	__le32 rx_msdu_byte_cnt_hi;
1282	__le32 rx_msdu_cnt_lo;
1283	__le32 rx_msdu_cnt_hi;
1284	__le32 tx_msdu_byte_cnt_lo;
1285	__le32 tx_msdu_byte_cnt_hi;
1286	__le32 tx_msdu_cnt_lo;
1287	__le32 tx_msdu_cnt_hi;
1288	__le32 tx_retry_cnt_lo;
1289	__le32 tx_retry_cnt_hi;
1290	__le32 tx_retry_byte_cnt_lo;
1291	__le32 tx_retry_byte_cnt_hi;
1292	__le32 tx_drop_cnt_lo;
1293	__le32 tx_drop_cnt_hi;
1294	__le32 tx_drop_byte_cnt_lo;
1295	__le32 tx_drop_byte_cnt_hi;
1296	__le32 msdu_ttl_cnt_lo;
1297	__le32 msdu_ttl_cnt_hi;
1298	__le32 msdu_ttl_byte_cnt_lo;
1299	__le32 msdu_ttl_byte_cnt_hi;
1300	} __packed;
1301
1302	struct htt_t2h_vdev_common_stats_tlv {
1303	__le32 soc_drop_count_lo;
1304	__le32 soc_drop_count_hi;
1305	} __packed;
1306
1307	/* ppdu stats
1308	*
1309	* @details
1310	* The following field definitions describe the format of the HTT target
1311	* to host ppdu stats indication message.
1312	*
1313	*
1314	* |31 16|15 12|11 10|9 8|7 0 |
1315	* |----------------------------------------------------------------------|
1316	* | payload_size | rsvd |pdev_id|mac_id | msg type |
1317	* |----------------------------------------------------------------------|
1318	* | ppdu_id |
1319	* |----------------------------------------------------------------------|
1320	* | Timestamp in us |
1321	* |----------------------------------------------------------------------|
1322	* | reserved |
1323	* |----------------------------------------------------------------------|
1324	* | type-specific stats info |
1325	* | (see htt_ppdu_stats.h) |
1326	* |----------------------------------------------------------------------|
1327	* Header fields:
1328	* - MSG_TYPE
1329	* Bits 7:0
1330	* Purpose: Identifies this is a PPDU STATS indication
1331	* message.
1332	* Value: 0x1d
1333	* - mac_id
1334	* Bits 9:8
1335	* Purpose: mac_id of this ppdu_id
1336	* Value: 0-3
1337	* - pdev_id
1338	* Bits 11:10
1339	* Purpose: pdev_id of this ppdu_id
1340	* Value: 0-3
1341	* 0 (for rings at SOC level),
1342	* 1/2/3 PDEV -> 0/1/2
1343	* - payload_size
1344	* Bits 31:16
1345	* Purpose: total tlv size
1346	* Value: payload_size in bytes
1347	*/
1348
1349	#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1350	#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1351
1352	struct ath12k_htt_ppdu_stats_msg {
1353	__le32 info;
1354	__le32 ppdu_id;
1355	__le32 timestamp;
1356	__le32 rsvd;
1357	u8 data[];
1358	} __packed;
1359
1360	struct htt_tlv {
1361	__le32 header;
1362	u8 value[];
1363	} __packed;
1364
1365	#define HTT_TLV_TAG GENMASK(11, 0)
1366	#define HTT_TLV_LEN GENMASK(23, 12)
1367
1368	enum HTT_PPDU_STATS_BW {
1369	HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1370	HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1371	HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1372	HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1373	HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1374	HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1375	HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1376	};
1377
1378	#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1379	#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1380	/* bw - HTT_PPDU_STATS_BW */
1381	#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1382
1383	struct htt_ppdu_stats_common {
1384	__le32 ppdu_id;
1385	__le16 sched_cmdid;
1386	u8 ring_id;
1387	u8 num_users;
1388	__le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1389	__le32 chain_mask;
1390	__le32 fes_duration_us; /* frame exchange sequence */
1391	__le32 ppdu_sch_eval_start_tstmp_us;
1392	__le32 ppdu_sch_end_tstmp_us;
1393	__le32 ppdu_start_tstmp_us;
1394	/* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1395	* BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1396	*/
1397	__le16 phy_mode;
1398	__le16 bw_mhz;
1399	} __packed;
1400
1401	enum htt_ppdu_stats_gi {
1402	HTT_PPDU_STATS_SGI_0_8_US,
1403	HTT_PPDU_STATS_SGI_0_4_US,
1404	HTT_PPDU_STATS_SGI_1_6_US,
1405	HTT_PPDU_STATS_SGI_3_2_US,
1406	};
1407
1408	#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1409	#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1410
1411	enum HTT_PPDU_STATS_PPDU_TYPE {
1412	HTT_PPDU_STATS_PPDU_TYPE_SU,
1413	HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
1414	HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,
1415	HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,
1416	HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,
1417	HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,
1418	HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,
1419	HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,
1420	HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,
1421	HTT_PPDU_STATS_PPDU_TYPE_MAX
1422	};
1423
1424	#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1425	#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1426
1427	#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1428	#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1429	#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1430	#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1431	#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1432	#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1433	#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1434	#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1435	#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1436	#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1437	#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1438
1439	#define HTT_USR_RATE_PREAMBLE(_val) \
1440	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)
1441	#define HTT_USR_RATE_BW(_val) \
1442	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)
1443	#define HTT_USR_RATE_NSS(_val) \
1444	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)
1445	#define HTT_USR_RATE_MCS(_val) \
1446	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)
1447	#define HTT_USR_RATE_GI(_val) \
1448	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)
1449	#define HTT_USR_RATE_DCM(_val) \
1450	le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)
1451
1452	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1453	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1454	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1455	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1456	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1457	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1458	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1459	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1460	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1461	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1462	#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1463
1464	struct htt_ppdu_stats_user_rate {
1465	u8 tid_num;
1466	u8 reserved0;
1467	__le16 sw_peer_id;
1468	__le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1469	__le16 ru_end;
1470	__le16 ru_start;
1471	__le16 resp_ru_end;
1472	__le16 resp_ru_start;
1473	__le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1474	__le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1475	/* Note: resp_rate_info is only valid for if resp_type is UL */
1476	__le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1477	} __packed;
1478
1479	#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1480	#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1481	#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1482	#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1483	#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1484	#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1485
1486	#define HTT_TX_INFO_IS_AMSDU(_flags) \
1487	u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)
1488	#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1489	u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)
1490	#define HTT_TX_INFO_RATECODE(_flags) \
1491	u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)
1492	#define HTT_TX_INFO_PEERID(_flags) \
1493	u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)
1494
1495	struct htt_tx_ppdu_stats_info {
1496	struct htt_tlv tlv_hdr;
1497	__le32 tx_success_bytes;
1498	__le32 tx_retry_bytes;
1499	__le32 tx_failed_bytes;
1500	__le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1501	__le16 tx_success_msdus;
1502	__le16 tx_retry_msdus;
1503	__le16 tx_failed_msdus;
1504	__le16 tx_duration; /* united in us */
1505	} __packed;
1506
1507	enum htt_ppdu_stats_usr_compln_status {
1508	HTT_PPDU_STATS_USER_STATUS_OK,
1509	HTT_PPDU_STATS_USER_STATUS_FILTERED,
1510	HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1511	HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1512	HTT_PPDU_STATS_USER_STATUS_ABORT,
1513	};
1514
1515	#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1516	#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1517	#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1518	#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1519
1520	#define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1521	le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)
1522	#define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1523	le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)
1524	#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1525	le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)
1526
1527	struct htt_ppdu_stats_usr_cmpltn_cmn {
1528	u8 status;
1529	u8 tid_num;
1530	__le16 sw_peer_id;
1531	/* RSSI value of last ack packet (units = dB above noise floor) */
1532	__le32 ack_rssi;
1533	__le16 mpdu_tried;
1534	__le16 mpdu_success;
1535	__le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1536	} __packed;
1537
1538	#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1539	#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1540	#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1541
1542	#define HTT_PPDU_STATS_NON_QOS_TID 16
1543
1544	struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1545	__le32 ppdu_id;
1546	__le16 sw_peer_id;
1547	__le16 reserved0;
1548	__le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1549	__le16 current_seq;
1550	__le16 start_seq;
1551	__le32 success_bytes;
1552	} __packed;
1553
1554	struct htt_ppdu_user_stats {
1555	u16 peer_id;
1556	u16 delay_ba;
1557	u32 tlv_flags;
1558	bool is_valid_peer_id;
1559	struct htt_ppdu_stats_user_rate rate;
1560	struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1561	struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1562	};
1563
1564	#define HTT_PPDU_STATS_MAX_USERS 8
1565	#define HTT_PPDU_DESC_MAX_DEPTH 16
1566
1567	struct htt_ppdu_stats {
1568	struct htt_ppdu_stats_common common;
1569	struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1570	};
1571
1572	struct htt_ppdu_stats_info {
1573	u32 tlv_bitmap;
1574	u32 ppdu_id;
1575	u32 frame_type;
1576	u32 frame_ctrl;
1577	u32 delay_ba;
1578	u32 bar_num_users;
1579	struct htt_ppdu_stats ppdu_stats;
1580	struct list_head list;
1581	};
1582
1583	/* @brief target -> host MLO offset indiciation message
1584	*
1585	* @details
1586	* The following field definitions describe the format of the HTT target
1587	* to host mlo offset indication message.
1588	*
1589	*
1590	* |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0|
1591	* |---------------------------------------------------------------------|
1592	* | rsvd1 | mac_freq |chip_id |pdev_id|msgtype|
1593	* |---------------------------------------------------------------------|
1594	* | sync_timestamp_lo_us |
1595	* |---------------------------------------------------------------------|
1596	* | sync_timestamp_hi_us |
1597	* |---------------------------------------------------------------------|
1598	* | mlo_offset_lo |
1599	* |---------------------------------------------------------------------|
1600	* | mlo_offset_hi |
1601	* |---------------------------------------------------------------------|
1602	* | mlo_offset_clcks |
1603	* |---------------------------------------------------------------------|
1604	* | rsvd2 | mlo_comp_clks |mlo_comp_us |
1605	* |---------------------------------------------------------------------|
1606	* | rsvd3 |mlo_comp_timer |
1607	* |---------------------------------------------------------------------|
1608	* Header fields
1609	* - MSG_TYPE
1610	* Bits 7:0
1611	* Purpose: Identifies this is a MLO offset indication msg
1612	* - PDEV_ID
1613	* Bits 9:8
1614	* Purpose: Pdev of this MLO offset
1615	* - CHIP_ID
1616	* Bits 12:10
1617	* Purpose: chip_id of this MLO offset
1618	* - MAC_FREQ
1619	* Bits 28:13
1620	* - SYNC_TIMESTAMP_LO_US
1621	* Purpose: clock frequency of the mac HW block in MHz
1622	* Bits: 31:0
1623	* Purpose: lower 32 bits of the WLAN global time stamp at which
1624	* last sync interrupt was received
1625	* - SYNC_TIMESTAMP_HI_US
1626	* Bits: 31:0
1627	* Purpose: upper 32 bits of WLAN global time stamp at which
1628	* last sync interrupt was received
1629	* - MLO_OFFSET_LO
1630	* Bits: 31:0
1631	* Purpose: lower 32 bits of the MLO offset in us
1632	* - MLO_OFFSET_HI
1633	* Bits: 31:0
1634	* Purpose: upper 32 bits of the MLO offset in us
1635	* - MLO_COMP_US
1636	* Bits: 15:0
1637	* Purpose: MLO time stamp compensation applied in us
1638	* - MLO_COMP_CLCKS
1639	* Bits: 25:16
1640	* Purpose: MLO time stamp compensation applied in clock ticks
1641	* - MLO_COMP_TIMER
1642	* Bits: 21:0
1643	* Purpose: Periodic timer at which compensation is applied
1644	*/
1645
1646	#define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0)
1647	#define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8)
1648
1649	struct ath12k_htt_mlo_offset_msg {
1650	__le32 info;
1651	__le32 sync_timestamp_lo_us;
1652	__le32 sync_timestamp_hi_us;
1653	__le32 mlo_offset_hi;
1654	__le32 mlo_offset_lo;
1655	__le32 mlo_offset_clks;
1656	__le32 mlo_comp_clks;
1657	__le32 mlo_comp_timer;
1658	} __packed;
1659
1660	/* @brief host -> target FW extended statistics retrieve
1661	*
1662	* @details
1663	* The following field definitions describe the format of the HTT host
1664	* to target FW extended stats retrieve message.
1665	* The message specifies the type of stats the host wants to retrieve.
1666	*
1667	* |31 24|23 16|15 8|7 0|
1668	* |-----------------------------------------------------------|
1669	* | reserved | stats type | pdev_mask | msg type |
1670	* |-----------------------------------------------------------|
1671	* | config param [0] |
1672	* |-----------------------------------------------------------|
1673	* | config param [1] |
1674	* |-----------------------------------------------------------|
1675	* | config param [2] |
1676	* |-----------------------------------------------------------|
1677	* | config param [3] |
1678	* |-----------------------------------------------------------|
1679	* | reserved |
1680	* |-----------------------------------------------------------|
1681	* | cookie LSBs |
1682	* |-----------------------------------------------------------|
1683	* | cookie MSBs |
1684	* |-----------------------------------------------------------|
1685	* Header fields:
1686	* - MSG_TYPE
1687	* Bits 7:0
1688	* Purpose: identifies this is a extended stats upload request message
1689	* Value: 0x10
1690	* - PDEV_MASK
1691	* Bits 8:15
1692	* Purpose: identifies the mask of PDEVs to retrieve stats from
1693	* Value: This is a overloaded field, refer to usage and interpretation of
1694	* PDEV in interface document.
1695	* Bit 8 : Reserved for SOC stats
1696	* Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1697	* Indicates MACID_MASK in DBS
1698	* - STATS_TYPE
1699	* Bits 23:16
1700	* Purpose: identifies which FW statistics to upload
1701	* Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1702	* - Reserved
1703	* Bits 31:24
1704	* - CONFIG_PARAM [0]
1705	* Bits 31:0
1706	* Purpose: give an opaque configuration value to the specified stats type
1707	* Value: stats-type specific configuration value
1708	* Refer to htt_stats.h for interpretation for each stats sub_type
1709	* - CONFIG_PARAM [1]
1710	* Bits 31:0
1711	* Purpose: give an opaque configuration value to the specified stats type
1712	* Value: stats-type specific configuration value
1713	* Refer to htt_stats.h for interpretation for each stats sub_type
1714	* - CONFIG_PARAM [2]
1715	* Bits 31:0
1716	* Purpose: give an opaque configuration value to the specified stats type
1717	* Value: stats-type specific configuration value
1718	* Refer to htt_stats.h for interpretation for each stats sub_type
1719	* - CONFIG_PARAM [3]
1720	* Bits 31:0
1721	* Purpose: give an opaque configuration value to the specified stats type
1722	* Value: stats-type specific configuration value
1723	* Refer to htt_stats.h for interpretation for each stats sub_type
1724	* - Reserved [31:0] for future use.
1725	* - COOKIE_LSBS
1726	* Bits 31:0
1727	* Purpose: Provide a mechanism to match a target->host stats confirmation
1728	* message with its preceding host->target stats request message.
1729	* Value: LSBs of the opaque cookie specified by the host-side requestor
1730	* - COOKIE_MSBS
1731	* Bits 31:0
1732	* Purpose: Provide a mechanism to match a target->host stats confirmation
1733	* message with its preceding host->target stats request message.
1734	* Value: MSBs of the opaque cookie specified by the host-side requestor
1735	*/
1736
1737	struct htt_ext_stats_cfg_hdr {
1738	u8 msg_type;
1739	u8 pdev_mask;
1740	u8 stats_type;
1741	u8 reserved;
1742	} __packed;
1743
1744	struct htt_ext_stats_cfg_cmd {
1745	struct htt_ext_stats_cfg_hdr hdr;
1746	__le32 cfg_param0;
1747	__le32 cfg_param1;
1748	__le32 cfg_param2;
1749	__le32 cfg_param3;
1750	__le32 reserved;
1751	__le32 cookie_lsb;
1752	__le32 cookie_msb;
1753	} __packed;
1754
1755	/* htt stats config default params */
1756	#define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1757	#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1758	#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1759	#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1760	#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1761	#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1762	#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1763	#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1764
1765	/* HTT_DBG_EXT_STATS_PEER_INFO
1766	* PARAMS:
1767	* @config_param0:
1768	* [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1769	* [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1770	* [Bit31 : Bit16] sw_peer_id
1771	* @config_param1:
1772	* peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1773	* 0 bit htt_peer_stats_cmn_tlv
1774	* 1 bit htt_peer_details_tlv
1775	* 2 bit htt_tx_peer_rate_stats_tlv
1776	* 3 bit htt_rx_peer_rate_stats_tlv
1777	* 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1778	* 5 bit htt_rx_tid_stats_tlv
1779	* 6 bit htt_msdu_flow_stats_tlv
1780	* @config_param2: [Bit31 : Bit0] mac_addr31to0
1781	* @config_param3: [Bit15 : Bit0] mac_addr47to32
1782	* [Bit31 : Bit16] reserved
1783	*/
1784	#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1785	#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1786
1787	/* Used to set different configs to the specified stats type.*/
1788	struct htt_ext_stats_cfg_params {
1789	u32 cfg0;
1790	u32 cfg1;
1791	u32 cfg2;
1792	u32 cfg3;
1793	};
1794
1795	enum vdev_stats_offload_timer_duration {
1796	ATH12K_STATS_TIMER_DUR_500MS = 1,
1797	ATH12K_STATS_TIMER_DUR_1SEC = 2,
1798	ATH12K_STATS_TIMER_DUR_2SEC = 3,
1799	};
1800
1801	static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1802	{
1803	memcpy(addr, &addr_l32, 4);
1804	memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1805	}
1806
1807	int ath12k_dp_service_srng(struct ath12k_base *ab,
1808	struct ath12k_ext_irq_grp *irq_grp,
1809	int budget);
1810	int ath12k_dp_htt_connect(struct ath12k_dp *dp);
1811	void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif);
1812	void ath12k_dp_free(struct ath12k_base *ab);
1813	int ath12k_dp_alloc(struct ath12k_base *ab);
1814	void ath12k_dp_cc_config(struct ath12k_base *ab);
1815	int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
1816	void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab);
1817	void ath12k_dp_pdev_free(struct ath12k_base *ab);
1818	int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
1819	int mac_id, enum hal_ring_type ring_type);
1820	int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
1821	void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
1822	void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
1823	int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
1824	enum hal_ring_type type, int ring_num,
1825	int mac_id, int num_entries);
1826	void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
1827	struct dp_link_desc_bank *desc_bank,
1828	u32 ring_type, struct dp_srng *ring);
1829	int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
1830	struct dp_link_desc_bank *link_desc_banks,
1831	u32 ring_type, struct hal_srng *srng,
1832	u32 n_link_desc);
1833	struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1834	u32 cookie);
1835	struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1836	u32 desc_id);
1837	bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab);
1838	void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab);
1839	#endif
1840