1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any |
5 | * purpose with or without fee is hereby granted, provided that the above |
6 | * copyright notice and this permission notice appear in all copies. |
7 | * |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
15 | */ |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | |
19 | #include <linux/nl80211.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/etherdevice.h> |
22 | #include <linux/module.h> |
23 | #include "../ath.h" |
24 | #include "ath5k.h" |
25 | #include "debug.h" |
26 | #include "base.h" |
27 | #include "reg.h" |
28 | |
29 | /* Known PCI ids */ |
30 | static const struct pci_device_id ath5k_pci_id_table[] = { |
31 | { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ |
32 | { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ |
33 | { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ |
34 | { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ |
35 | { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ |
36 | { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ |
37 | { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ |
38 | { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ |
39 | { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */ |
40 | { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */ |
41 | { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */ |
42 | { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */ |
43 | { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */ |
44 | { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */ |
45 | { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ |
46 | { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ |
47 | { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ |
48 | { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ |
49 | { PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */ |
50 | { 0 } |
51 | }; |
52 | MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); |
53 | |
54 | /* return bus cachesize in 4B word units */ |
55 | static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) |
56 | { |
57 | struct ath5k_hw *ah = common->priv; |
58 | u8 u8tmp; |
59 | |
60 | pci_read_config_byte(dev: ah->pdev, PCI_CACHE_LINE_SIZE, val: &u8tmp); |
61 | *csz = (int)u8tmp; |
62 | |
63 | /* |
64 | * This check was put in to avoid "unpleasant" consequences if |
65 | * the bootrom has not fully initialized all PCI devices. |
66 | * Sometimes the cache line size register is not set |
67 | */ |
68 | |
69 | if (*csz == 0) |
70 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ |
71 | } |
72 | |
73 | /* |
74 | * Read from eeprom |
75 | */ |
76 | static bool |
77 | ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) |
78 | { |
79 | struct ath5k_hw *ah = common->ah; |
80 | u32 status, timeout; |
81 | |
82 | /* |
83 | * Initialize EEPROM access |
84 | */ |
85 | if (ah->ah_version == AR5K_AR5210) { |
86 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); |
87 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); |
88 | } else { |
89 | ath5k_hw_reg_write(ah, val: offset, AR5K_EEPROM_BASE); |
90 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, |
91 | AR5K_EEPROM_CMD_READ); |
92 | } |
93 | |
94 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { |
95 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); |
96 | if (status & AR5K_EEPROM_STAT_RDDONE) { |
97 | if (status & AR5K_EEPROM_STAT_RDERR) |
98 | return false; |
99 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & |
100 | 0xffff); |
101 | return true; |
102 | } |
103 | usleep_range(min: 15, max: 20); |
104 | } |
105 | |
106 | return false; |
107 | } |
108 | |
109 | int ath5k_hw_read_srev(struct ath5k_hw *ah) |
110 | { |
111 | ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); |
112 | return 0; |
113 | } |
114 | |
115 | /* |
116 | * Read the MAC address from eeprom or platform_data |
117 | */ |
118 | static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) |
119 | { |
120 | u8 mac_d[ETH_ALEN] = {}; |
121 | u32 total, offset; |
122 | u16 data; |
123 | int octet; |
124 | |
125 | AR5K_EEPROM_READ(0x20, data); |
126 | |
127 | for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { |
128 | AR5K_EEPROM_READ(offset, data); |
129 | |
130 | total += data; |
131 | mac_d[octet + 1] = data & 0xff; |
132 | mac_d[octet] = data >> 8; |
133 | octet += 2; |
134 | } |
135 | |
136 | if (!total || total == 3 * 0xffff) |
137 | return -EINVAL; |
138 | |
139 | memcpy(mac, mac_d, ETH_ALEN); |
140 | |
141 | return 0; |
142 | } |
143 | |
144 | |
145 | /* Common ath_bus_opts structure */ |
146 | static const struct ath_bus_ops ath_pci_bus_ops = { |
147 | .ath_bus_type = ATH_PCI, |
148 | .read_cachesize = ath5k_pci_read_cachesize, |
149 | .eeprom_read = ath5k_pci_eeprom_read, |
150 | .eeprom_read_mac = ath5k_pci_eeprom_read_mac, |
151 | }; |
152 | |
153 | /********************\ |
154 | * PCI Initialization * |
155 | \********************/ |
156 | |
157 | static int |
158 | ath5k_pci_probe(struct pci_dev *pdev, |
159 | const struct pci_device_id *id) |
160 | { |
161 | void __iomem *mem; |
162 | struct ath5k_hw *ah; |
163 | struct ieee80211_hw *hw; |
164 | int ret; |
165 | u8 csz; |
166 | |
167 | /* |
168 | * L0s needs to be disabled on all ath5k cards. |
169 | * |
170 | * For distributions shipping with CONFIG_PCIEASPM (this will be enabled |
171 | * by default in the future in 2.6.36) this will also mean both L1 and |
172 | * L0s will be disabled when a pre 1.1 PCIe device is detected. We do |
173 | * know L1 works correctly even for all ath5k pre 1.1 PCIe devices |
174 | * though but cannot currently undue the effect of a blacklist, for |
175 | * details you can read pcie_aspm_sanity_check() and see how it adjusts |
176 | * the device link capability. |
177 | * |
178 | * It may be possible in the future to implement some PCI API to allow |
179 | * drivers to override blacklists for pre 1.1 PCIe but for now it is |
180 | * best to accept that both L0s and L1 will be disabled completely for |
181 | * distributions shipping with CONFIG_PCIEASPM rather than having this |
182 | * issue present. Motivation for adding this new API will be to help |
183 | * with power consumption for some of these devices. |
184 | */ |
185 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); |
186 | |
187 | ret = pci_enable_device(dev: pdev); |
188 | if (ret) { |
189 | dev_err(&pdev->dev, "can't enable device\n" ); |
190 | goto err; |
191 | } |
192 | |
193 | /* XXX 32-bit addressing only */ |
194 | ret = dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(32)); |
195 | if (ret) { |
196 | dev_err(&pdev->dev, "32-bit DMA not available\n" ); |
197 | goto err_dis; |
198 | } |
199 | |
200 | /* |
201 | * Cache line size is used to size and align various |
202 | * structures used to communicate with the hardware. |
203 | */ |
204 | pci_read_config_byte(dev: pdev, PCI_CACHE_LINE_SIZE, val: &csz); |
205 | if (csz == 0) { |
206 | /* |
207 | * Linux 2.4.18 (at least) writes the cache line size |
208 | * register as a 16-bit wide register which is wrong. |
209 | * We must have this setup properly for rx buffer |
210 | * DMA to work so force a reasonable value here if it |
211 | * comes up zero. |
212 | */ |
213 | csz = L1_CACHE_BYTES >> 2; |
214 | pci_write_config_byte(dev: pdev, PCI_CACHE_LINE_SIZE, val: csz); |
215 | } |
216 | /* |
217 | * The default setting of latency timer yields poor results, |
218 | * set it to the value used by other systems. It may be worth |
219 | * tweaking this setting more. |
220 | */ |
221 | pci_write_config_byte(dev: pdev, PCI_LATENCY_TIMER, val: 0xa8); |
222 | |
223 | /* Enable bus mastering */ |
224 | pci_set_master(dev: pdev); |
225 | |
226 | /* |
227 | * Disable the RETRY_TIMEOUT register (0x41) to keep |
228 | * PCI Tx retries from interfering with C3 CPU state. |
229 | */ |
230 | pci_write_config_byte(dev: pdev, where: 0x41, val: 0); |
231 | |
232 | ret = pci_request_region(pdev, 0, "ath5k" ); |
233 | if (ret) { |
234 | dev_err(&pdev->dev, "cannot reserve PCI memory region\n" ); |
235 | goto err_dis; |
236 | } |
237 | |
238 | mem = pci_iomap(dev: pdev, bar: 0, max: 0); |
239 | if (!mem) { |
240 | dev_err(&pdev->dev, "cannot remap PCI memory region\n" ); |
241 | ret = -EIO; |
242 | goto err_reg; |
243 | } |
244 | |
245 | /* |
246 | * Allocate hw (mac80211 main struct) |
247 | * and hw->priv (driver private data) |
248 | */ |
249 | hw = ieee80211_alloc_hw(priv_data_len: sizeof(*ah), ops: &ath5k_hw_ops); |
250 | if (hw == NULL) { |
251 | dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n" ); |
252 | ret = -ENOMEM; |
253 | goto err_map; |
254 | } |
255 | |
256 | dev_info(&pdev->dev, "registered as '%s'\n" , wiphy_name(hw->wiphy)); |
257 | |
258 | ah = hw->priv; |
259 | ah->hw = hw; |
260 | ah->pdev = pdev; |
261 | ah->dev = &pdev->dev; |
262 | ah->irq = pdev->irq; |
263 | ah->devid = id->device; |
264 | ah->iobase = mem; /* So we can unmap it on detach */ |
265 | |
266 | /* Initialize */ |
267 | ret = ath5k_init_ah(ah, bus_ops: &ath_pci_bus_ops); |
268 | if (ret) |
269 | goto err_free; |
270 | |
271 | /* Set private data */ |
272 | pci_set_drvdata(pdev, data: hw); |
273 | |
274 | return 0; |
275 | err_free: |
276 | ieee80211_free_hw(hw); |
277 | err_map: |
278 | pci_iounmap(dev: pdev, mem); |
279 | err_reg: |
280 | pci_release_region(pdev, 0); |
281 | err_dis: |
282 | pci_disable_device(dev: pdev); |
283 | err: |
284 | return ret; |
285 | } |
286 | |
287 | static void |
288 | ath5k_pci_remove(struct pci_dev *pdev) |
289 | { |
290 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
291 | struct ath5k_hw *ah = hw->priv; |
292 | |
293 | ath5k_deinit_ah(ah); |
294 | pci_iounmap(dev: pdev, ah->iobase); |
295 | pci_release_region(pdev, 0); |
296 | pci_disable_device(dev: pdev); |
297 | ieee80211_free_hw(hw); |
298 | } |
299 | |
300 | #ifdef CONFIG_PM_SLEEP |
301 | static int ath5k_pci_suspend(struct device *dev) |
302 | { |
303 | struct ieee80211_hw *hw = dev_get_drvdata(dev); |
304 | struct ath5k_hw *ah = hw->priv; |
305 | |
306 | ath5k_led_off(ah); |
307 | return 0; |
308 | } |
309 | |
310 | static int ath5k_pci_resume(struct device *dev) |
311 | { |
312 | struct pci_dev *pdev = to_pci_dev(dev); |
313 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
314 | struct ath5k_hw *ah = hw->priv; |
315 | |
316 | /* |
317 | * Suspend/Resume resets the PCI configuration space, so we have to |
318 | * re-disable the RETRY_TIMEOUT register (0x41) to keep |
319 | * PCI Tx retries from interfering with C3 CPU state |
320 | */ |
321 | pci_write_config_byte(dev: pdev, where: 0x41, val: 0); |
322 | |
323 | ath5k_led_enable(ah); |
324 | return 0; |
325 | } |
326 | |
327 | static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); |
328 | #define ATH5K_PM_OPS (&ath5k_pm_ops) |
329 | #else |
330 | #define ATH5K_PM_OPS NULL |
331 | #endif /* CONFIG_PM_SLEEP */ |
332 | |
333 | static struct pci_driver ath5k_pci_driver = { |
334 | .name = KBUILD_MODNAME, |
335 | .id_table = ath5k_pci_id_table, |
336 | .probe = ath5k_pci_probe, |
337 | .remove = ath5k_pci_remove, |
338 | .driver.pm = ATH5K_PM_OPS, |
339 | }; |
340 | |
341 | module_pci_driver(ath5k_pci_driver); |
342 | |