1	// SPDX-License-Identifier: ISC
2	/*
3	* Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/etherdevice.h>
7	#include <linux/moduleparam.h>
8	#include <linux/prefetch.h>
9	#include <linux/types.h>
10	#include <linux/list.h>
11	#include <linux/ip.h>
12	#include <linux/ipv6.h>
13	#include "wil6210.h"
14	#include "txrx_edma.h"
15	#include "txrx.h"
16	#include "trace.h"
17
18	/* Max number of entries (packets to complete) to update the hwtail of tx
19	* status ring. Should be power of 2
20	*/
21	#define WIL_EDMA_TX_SRING_UPDATE_HW_TAIL 128
22	#define WIL_EDMA_MAX_DATA_OFFSET (2)
23	/* RX buffer size must be aligned to 4 bytes */
24	#define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
25	#define MAX_INVALID_BUFF_ID_RETRY (3)
26
27	static void wil_tx_desc_unmap_edma(struct device *dev,
28	union wil_tx_desc *desc,
29	struct wil_ctx *ctx)
30	{
31	struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc;
32	dma_addr_t pa = wil_tx_desc_get_addr_edma(dma: &d->dma);
33	u16 dmalen = le16_to_cpu(d->dma.length);
34
35	switch (ctx->mapped_as) {
36	case wil_mapped_as_single:
37	dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
38	break;
39	case wil_mapped_as_page:
40	dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
41	break;
42	default:
43	break;
44	}
45	}
46
47	static int wil_find_free_sring(struct wil6210_priv *wil)
48	{
49	int i;
50
51	for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) {
52	if (!wil->srings[i].va)
53	return i;
54	}
55
56	return -EINVAL;
57	}
58
59	static void wil_sring_free(struct wil6210_priv *wil,
60	struct wil_status_ring *sring)
61	{
62	struct device *dev = wil_to_dev(wil);
63	size_t sz;
64
65	if (!sring || !sring->va)
66	return;
67
68	sz = sring->elem_size * sring->size;
69
70	wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n",
71	sz, sring->va, &sring->pa);
72
73	dma_free_coherent(dev, size: sz, cpu_addr: (void *)sring->va, dma_handle: sring->pa);
74	sring->pa = 0;
75	sring->va = NULL;
76	}
77
78	static int wil_sring_alloc(struct wil6210_priv *wil,
79	struct wil_status_ring *sring)
80	{
81	struct device *dev = wil_to_dev(wil);
82	size_t sz = sring->elem_size * sring->size;
83
84	wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz);
85
86	if (sz == 0) {
87	wil_err(wil, "Cannot allocate a zero size status ring\n");
88	return -EINVAL;
89	}
90
91	sring->swhead = 0;
92
93	/* Status messages are allocated and initialized to 0. This is necessary
94	* since DR bit should be initialized to 0.
95	*/
96	sring->va = dma_alloc_coherent(dev, size: sz, dma_handle: &sring->pa, GFP_KERNEL);
97	if (!sring->va)
98	return -ENOMEM;
99
100	wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va,
101	&sring->pa);
102
103	return 0;
104	}
105
106	static int wil_tx_init_edma(struct wil6210_priv *wil)
107	{
108	int ring_id = wil_find_free_sring(wil);
109	struct wil_status_ring *sring;
110	int rc;
111	u16 status_ring_size;
112
113	if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
114	wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
115	wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
116
117	status_ring_size = 1 << wil->tx_status_ring_order;
118
119	wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n",
120	status_ring_size, ring_id);
121
122	if (ring_id < 0)
123	return ring_id;
124
125	/* Allocate Tx status ring. Tx descriptor rings will be
126	* allocated on WMI connect event
127	*/
128	sring = &wil->srings[ring_id];
129
130	sring->is_rx = false;
131	sring->size = status_ring_size;
132	sring->elem_size = sizeof(struct wil_ring_tx_status);
133	rc = wil_sring_alloc(wil, sring);
134	if (rc)
135	return rc;
136
137	rc = wil_wmi_tx_sring_cfg(wil, ring_id);
138	if (rc)
139	goto out_free;
140
141	sring->desc_rdy_pol = 1;
142	wil->tx_sring_idx = ring_id;
143
144	return 0;
145	out_free:
146	wil_sring_free(wil, sring);
147	return rc;
148	}
149
150	/* Allocate one skb for Rx descriptor RING */
151	static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
152	struct wil_ring *ring, u32 i)
153	{
154	struct device *dev = wil_to_dev(wil);
155	unsigned int sz = wil->rx_buf_len;
156	dma_addr_t pa;
157	u16 buff_id;
158	struct list_head *active = &wil->rx_buff_mgmt.active;
159	struct list_head *free = &wil->rx_buff_mgmt.free;
160	struct wil_rx_buff *rx_buff;
161	struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr;
162	struct sk_buff *skb;
163	struct wil_rx_enhanced_desc dd, *d = &dd;
164	struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *)
165	&ring->va[i].rx.enhanced;
166
167	if (unlikely(list_empty(free))) {
168	wil->rx_buff_mgmt.free_list_empty_cnt++;
169	return -EAGAIN;
170	}
171
172	skb = dev_alloc_skb(length: sz);
173	if (unlikely(!skb))
174	return -ENOMEM;
175
176	skb_put(skb, len: sz);
177
178	/**
179	* Make sure that the network stack calculates checksum for packets
180	* which failed the HW checksum calculation
181	*/
182	skb->ip_summed = CHECKSUM_NONE;
183
184	pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
185	if (unlikely(dma_mapping_error(dev, pa))) {
186	kfree_skb(skb);
187	return -ENOMEM;
188	}
189
190	/* Get the buffer ID - the index of the rx buffer in the buff_arr */
191	rx_buff = list_first_entry(free, struct wil_rx_buff, list);
192	buff_id = rx_buff->id;
193
194	/* Move a buffer from the free list to the active list */
195	list_move(list: &rx_buff->list, head: active);
196
197	buff_arr[buff_id].skb = skb;
198
199	wil_desc_set_addr_edma(addr: &d->dma.addr, addr_high_high: &d->dma.addr_high_high, pa);
200	d->dma.length = cpu_to_le16(sz);
201	d->mac.buff_id = cpu_to_le16(buff_id);
202	*_d = *d;
203
204	/* Save the physical address in skb->cb for later use in dma_unmap */
205	memcpy(skb->cb, &pa, sizeof(pa));
206
207	return 0;
208	}
209
210	static inline
211	void wil_get_next_rx_status_msg(struct wil_status_ring *sring, u8 *dr_bit,
212	void *msg)
213	{
214	struct wil_rx_status_compressed *_msg;
215
216	_msg = (struct wil_rx_status_compressed *)
217	(sring->va + (sring->elem_size * sring->swhead));
218	*dr_bit = WIL_GET_BITS(x: _msg->d0, b0: 31, b1: 31);
219	/* make sure dr_bit is read before the rest of status msg */
220	rmb();
221	memcpy(msg, (void *)_msg, sring->elem_size);
222	}
223
224	static inline void wil_sring_advance_swhead(struct wil_status_ring *sring)
225	{
226	sring->swhead = (sring->swhead + 1) % sring->size;
227	if (sring->swhead == 0)
228	sring->desc_rdy_pol = 1 - sring->desc_rdy_pol;
229	}
230
231	static int wil_rx_refill_edma(struct wil6210_priv *wil)
232	{
233	struct wil_ring *ring = &wil->ring_rx;
234	u32 next_head;
235	int rc = 0;
236	ring->swtail = *ring->edma_rx_swtail.va;
237
238	for (; next_head = wil_ring_next_head(ring),
239	(next_head != ring->swtail);
240	ring->swhead = next_head) {
241	rc = wil_ring_alloc_skb_edma(wil, ring, i: ring->swhead);
242	if (unlikely(rc)) {
243	if (rc == -EAGAIN)
244	wil_dbg_txrx(wil, "No free buffer ID found\n");
245	else
246	wil_err_ratelimited(wil,
247	"Error %d in refill desc[%d]\n",
248	rc, ring->swhead);
249	break;
250	}
251	}
252
253	/* make sure all writes to descriptors (shared memory) are done before
254	* committing them to HW
255	*/
256	wmb();
257
258	wil_w(wil, reg: ring->hwtail, val: ring->swhead);
259
260	return rc;
261	}
262
263	static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil,
264	struct wil_ring *ring)
265	{
266	struct device *dev = wil_to_dev(wil);
267	struct list_head *active = &wil->rx_buff_mgmt.active;
268	dma_addr_t pa;
269
270	if (!wil->rx_buff_mgmt.buff_arr)
271	return;
272
273	while (!list_empty(head: active)) {
274	struct wil_rx_buff *rx_buff =
275	list_first_entry(active, struct wil_rx_buff, list);
276	struct sk_buff *skb = rx_buff->skb;
277
278	if (unlikely(!skb)) {
279	wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id);
280	} else {
281	rx_buff->skb = NULL;
282	memcpy(&pa, skb->cb, sizeof(pa));
283	dma_unmap_single(dev, pa, wil->rx_buf_len,
284	DMA_FROM_DEVICE);
285	kfree_skb(skb);
286	}
287
288	/* Move the buffer from the active to the free list */
289	list_move(list: &rx_buff->list, head: &wil->rx_buff_mgmt.free);
290	}
291	}
292
293	static void wil_free_rx_buff_arr(struct wil6210_priv *wil)
294	{
295	struct wil_ring *ring = &wil->ring_rx;
296
297	if (!wil->rx_buff_mgmt.buff_arr)
298	return;
299
300	/* Move all the buffers to the free list in case active list is
301	* not empty in order to release all SKBs before deleting the array
302	*/
303	wil_move_all_rx_buff_to_free_list(wil, ring);
304
305	kfree(objp: wil->rx_buff_mgmt.buff_arr);
306	wil->rx_buff_mgmt.buff_arr = NULL;
307	}
308
309	static int wil_init_rx_buff_arr(struct wil6210_priv *wil,
310	size_t size)
311	{
312	struct wil_rx_buff *buff_arr;
313	struct list_head *active = &wil->rx_buff_mgmt.active;
314	struct list_head *free = &wil->rx_buff_mgmt.free;
315	int i;
316
317	wil->rx_buff_mgmt.buff_arr = kcalloc(n: size + 1,
318	size: sizeof(struct wil_rx_buff),
319	GFP_KERNEL);
320	if (!wil->rx_buff_mgmt.buff_arr)
321	return -ENOMEM;
322
323	/* Set list heads */
324	INIT_LIST_HEAD(list: active);
325	INIT_LIST_HEAD(list: free);
326
327	/* Linkify the list.
328	* buffer id 0 should not be used (marks invalid id).
329	*/
330	buff_arr = wil->rx_buff_mgmt.buff_arr;
331	for (i = 1; i <= size; i++) {
332	list_add(new: &buff_arr[i].list, head: free);
333	buff_arr[i].id = i;
334	}
335
336	wil->rx_buff_mgmt.size = size + 1;
337
338	return 0;
339	}
340
341	static int wil_init_rx_sring(struct wil6210_priv *wil,
342	u16 status_ring_size,
343	size_t elem_size,
344	u16 ring_id)
345	{
346	struct wil_status_ring *sring = &wil->srings[ring_id];
347	int rc;
348
349	wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n",
350	status_ring_size, ring_id);
351
352	memset(&sring->rx_data, 0, sizeof(sring->rx_data));
353
354	sring->is_rx = true;
355	sring->size = status_ring_size;
356	sring->elem_size = elem_size;
357	rc = wil_sring_alloc(wil, sring);
358	if (rc)
359	return rc;
360
361	rc = wil_wmi_rx_sring_add(wil, ring_id);
362	if (rc)
363	goto out_free;
364
365	sring->desc_rdy_pol = 1;
366
367	return 0;
368	out_free:
369	wil_sring_free(wil, sring);
370	return rc;
371	}
372
373	static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil,
374	struct wil_ring *ring)
375	{
376	struct device *dev = wil_to_dev(wil);
377	size_t sz = ring->size * sizeof(ring->va[0]);
378
379	wil_dbg_misc(wil, "alloc_desc_ring:\n");
380
381	BUILD_BUG_ON(sizeof(ring->va[0]) != 32);
382
383	ring->swhead = 0;
384	ring->swtail = 0;
385	ring->ctx = kcalloc(n: ring->size, size: sizeof(ring->ctx[0]), GFP_KERNEL);
386	if (!ring->ctx)
387	goto err;
388
389	ring->va = dma_alloc_coherent(dev, size: sz, dma_handle: &ring->pa, GFP_KERNEL);
390	if (!ring->va)
391	goto err_free_ctx;
392
393	if (ring->is_rx) {
394	sz = sizeof(*ring->edma_rx_swtail.va);
395	ring->edma_rx_swtail.va =
396	dma_alloc_coherent(dev, size: sz, dma_handle: &ring->edma_rx_swtail.pa,
397	GFP_KERNEL);
398	if (!ring->edma_rx_swtail.va)
399	goto err_free_va;
400	}
401
402	wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n",
403	ring->is_rx ? "RX" : "TX",
404	ring->size, ring->va, &ring->pa, ring->ctx);
405
406	return 0;
407	err_free_va:
408	dma_free_coherent(dev, size: ring->size * sizeof(ring->va[0]),
409	cpu_addr: (void *)ring->va, dma_handle: ring->pa);
410	ring->va = NULL;
411	err_free_ctx:
412	kfree(objp: ring->ctx);
413	ring->ctx = NULL;
414	err:
415	return -ENOMEM;
416	}
417
418	static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring)
419	{
420	struct device *dev = wil_to_dev(wil);
421	size_t sz;
422	int ring_index = 0;
423
424	if (!ring->va)
425	return;
426
427	sz = ring->size * sizeof(ring->va[0]);
428
429	lockdep_assert_held(&wil->mutex);
430	if (ring->is_rx) {
431	wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n",
432	ring->size, ring->va,
433	&ring->pa, ring->ctx);
434
435	wil_move_all_rx_buff_to_free_list(wil, ring);
436	dma_free_coherent(dev, size: sizeof(*ring->edma_rx_swtail.va),
437	cpu_addr: ring->edma_rx_swtail.va,
438	dma_handle: ring->edma_rx_swtail.pa);
439	goto out;
440	}
441
442	/* TX ring */
443	ring_index = ring - wil->ring_tx;
444
445	wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n",
446	ring_index, ring->size, ring->va,
447	&ring->pa, ring->ctx);
448
449	while (!wil_ring_is_empty(ring)) {
450	struct wil_ctx *ctx;
451
452	struct wil_tx_enhanced_desc dd, *d = &dd;
453	struct wil_tx_enhanced_desc *_d =
454	(struct wil_tx_enhanced_desc *)
455	&ring->va[ring->swtail].tx.enhanced;
456
457	ctx = &ring->ctx[ring->swtail];
458	if (!ctx) {
459	wil_dbg_txrx(wil,
460	"ctx(%d) was already completed\n",
461	ring->swtail);
462	ring->swtail = wil_ring_next_tail(ring);
463	continue;
464	}
465	*d = *_d;
466	wil_tx_desc_unmap_edma(dev, desc: (union wil_tx_desc *)d, ctx);
467	if (ctx->skb)
468	dev_kfree_skb_any(skb: ctx->skb);
469	ring->swtail = wil_ring_next_tail(ring);
470	}
471
472	out:
473	dma_free_coherent(dev, size: sz, cpu_addr: (void *)ring->va, dma_handle: ring->pa);
474	kfree(objp: ring->ctx);
475	ring->pa = 0;
476	ring->va = NULL;
477	ring->ctx = NULL;
478	}
479
480	static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size,
481	int status_ring_id)
482	{
483	struct wil_ring *ring = &wil->ring_rx;
484	int rc;
485
486	wil_dbg_misc(wil, "init RX desc ring\n");
487
488	ring->size = desc_ring_size;
489	ring->is_rx = true;
490	rc = wil_ring_alloc_desc_ring(wil, ring);
491	if (rc)
492	return rc;
493
494	rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id);
495	if (rc)
496	goto out_free;
497
498	return 0;
499	out_free:
500	wil_ring_free_edma(wil, ring);
501	return rc;
502	}
503
504	static void wil_get_reorder_params_edma(struct wil6210_priv *wil,
505	struct sk_buff *skb, int *tid,
506	int *cid, int *mid, u16 *seq,
507	int *mcast, int *retry)
508	{
509	struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
510
511	*tid = wil_rx_status_get_tid(msg: s);
512	*cid = wil_rx_status_get_cid(msg: s);
513	*mid = wil_rx_status_get_mid(msg: s);
514	*seq = le16_to_cpu(wil_rx_status_get_seq(wil, s));
515	*mcast = wil_rx_status_get_mcast(msg: s);
516	*retry = wil_rx_status_get_retry(msg: s);
517	}
518
519	static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid,
520	int *security)
521	{
522	struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
523
524	*cid = wil_rx_status_get_cid(msg: s);
525	*security = wil_rx_status_get_security(msg: s);
526	}
527
528	static int wil_rx_crypto_check_edma(struct wil6210_priv *wil,
529	struct sk_buff *skb)
530	{
531	struct wil_rx_status_extended *st;
532	int cid, tid, key_id, mc;
533	struct wil_sta_info *s;
534	struct wil_tid_crypto_rx *c;
535	struct wil_tid_crypto_rx_single *cc;
536	const u8 *pn;
537
538	/* In HW reorder, HW is responsible for crypto check */
539	if (wil->use_rx_hw_reordering)
540	return 0;
541
542	st = wil_skb_rxstatus(skb);
543
544	cid = wil_rx_status_get_cid(msg: st);
545	tid = wil_rx_status_get_tid(msg: st);
546	key_id = wil_rx_status_get_key_id(msg: st);
547	mc = wil_rx_status_get_mcast(msg: st);
548	s = &wil->sta[cid];
549	c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid];
550	cc = &c->key_id[key_id];
551	pn = (u8 *)&st->ext.pn;
552
553	if (!cc->key_set) {
554	wil_err_ratelimited(wil,
555	"Key missing. CID %d TID %d MCast %d KEY_ID %d\n",
556	cid, tid, mc, key_id);
557	return -EINVAL;
558	}
559
560	if (reverse_memcmp(cs: pn, ct: cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) {
561	wil_err_ratelimited(wil,
562	"Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n",
563	cid, tid, mc, key_id, pn, cc->pn);
564	return -EINVAL;
565	}
566	memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN);
567
568	return 0;
569	}
570
571	static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
572	{
573	struct wil_status_ring *sring;
574	struct wil_rx_status_extended msg1;
575	void *msg = &msg1;
576	u8 dr_bit;
577	int i;
578
579	for (i = 0; i < wil->num_rx_status_rings; i++) {
580	sring = &wil->srings[i];
581	if (!sring->va)
582	continue;
583
584	wil_get_next_rx_status_msg(sring, dr_bit: &dr_bit, msg);
585
586	/* Check if there are unhandled RX status messages */
587	if (dr_bit == sring->desc_rdy_pol)
588	return false;
589	}
590
591	return true;
592	}
593
594	static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
595	{
596	/* RX buffer size must be aligned to 4 bytes */
597	wil->rx_buf_len = rx_large_buf ?
598	WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
599	}
600
601	static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order)
602	{
603	u16 status_ring_size, desc_ring_size = 1 << desc_ring_order;
604	struct wil_ring *ring = &wil->ring_rx;
605	int rc;
606	size_t elem_size = wil->use_compressed_rx_status ?
607	sizeof(struct wil_rx_status_compressed) :
608	sizeof(struct wil_rx_status_extended);
609	int i;
610
611	/* In SW reorder one must use extended status messages */
612	if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) {
613	wil_err(wil,
614	"compressed RX status cannot be used with SW reorder\n");
615	return -EINVAL;
616	}
617	if (wil->rx_status_ring_order <= desc_ring_order)
618	/* make sure sring is larger than desc ring */
619	wil->rx_status_ring_order = desc_ring_order + 1;
620	if (wil->rx_buff_id_count <= desc_ring_size)
621	/* make sure we will not run out of buff_ids */
622	wil->rx_buff_id_count = desc_ring_size + 512;
623	if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
624	wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
625	wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
626
627	status_ring_size = 1 << wil->rx_status_ring_order;
628
629	wil_dbg_misc(wil,
630	"rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n",
631	desc_ring_size, status_ring_size, elem_size);
632
633	wil_rx_buf_len_init_edma(wil);
634
635	/* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
636	if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
637	wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1;
638
639	wil_dbg_misc(wil, "rx_init: allocate %d status rings\n",
640	wil->num_rx_status_rings);
641
642	rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc: wil->rx_buf_len);
643	if (rc)
644	return rc;
645
646	/* Allocate status ring */
647	for (i = 0; i < wil->num_rx_status_rings; i++) {
648	int sring_id = wil_find_free_sring(wil);
649
650	if (sring_id < 0) {
651	rc = -EFAULT;
652	goto err_free_status;
653	}
654	rc = wil_init_rx_sring(wil, status_ring_size, elem_size,
655	ring_id: sring_id);
656	if (rc)
657	goto err_free_status;
658	}
659
660	/* Allocate descriptor ring */
661	rc = wil_init_rx_desc_ring(wil, desc_ring_size,
662	WIL_DEFAULT_RX_STATUS_RING_ID);
663	if (rc)
664	goto err_free_status;
665
666	if (wil->rx_buff_id_count >= status_ring_size) {
667	wil_info(wil,
668	"rx_buff_id_count %d exceeds sring_size %d. set it to %d\n",
669	wil->rx_buff_id_count, status_ring_size,
670	status_ring_size - 1);
671	wil->rx_buff_id_count = status_ring_size - 1;
672	}
673
674	/* Allocate Rx buffer array */
675	rc = wil_init_rx_buff_arr(wil, size: wil->rx_buff_id_count);
676	if (rc)
677	goto err_free_desc;
678
679	/* Fill descriptor ring with credits */
680	rc = wil_rx_refill_edma(wil);
681	if (rc)
682	goto err_free_rx_buff_arr;
683
684	return 0;
685	err_free_rx_buff_arr:
686	wil_free_rx_buff_arr(wil);
687	err_free_desc:
688	wil_ring_free_edma(wil, ring);
689	err_free_status:
690	for (i = 0; i < wil->num_rx_status_rings; i++)
691	wil_sring_free(wil, sring: &wil->srings[i]);
692
693	return rc;
694	}
695
696	static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id,
697	int size, int cid, int tid)
698	{
699	struct wil6210_priv *wil = vif_to_wil(vif);
700	int rc;
701	struct wil_ring *ring = &wil->ring_tx[ring_id];
702	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
703
704	lockdep_assert_held(&wil->mutex);
705
706	wil_dbg_misc(wil,
707	"init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n",
708	ring_id, cid, tid, wil->tx_sring_idx);
709
710	wil_tx_data_init(txdata);
711	ring->size = size;
712	rc = wil_ring_alloc_desc_ring(wil, ring);
713	if (rc)
714	goto out;
715
716	wil->ring2cid_tid[ring_id][0] = cid;
717	wil->ring2cid_tid[ring_id][1] = tid;
718	if (!vif->privacy)
719	txdata->dot1x_open = true;
720
721	rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid);
722	if (rc) {
723	wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n");
724	goto out_free;
725	}
726
727	if (txdata->dot1x_open && agg_wsize >= 0)
728	wil_addba_tx_request(wil, ringid: ring_id, wsize: agg_wsize);
729
730	return 0;
731	out_free:
732	spin_lock_bh(lock: &txdata->lock);
733	txdata->dot1x_open = false;
734	txdata->enabled = 0;
735	spin_unlock_bh(lock: &txdata->lock);
736	wil_ring_free_edma(wil, ring);
737	wil->ring2cid_tid[ring_id][0] = wil->max_assoc_sta;
738	wil->ring2cid_tid[ring_id][1] = 0;
739
740	out:
741	return rc;
742	}
743
744	static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id,
745	int cid, int tid)
746	{
747	struct wil6210_priv *wil = vif_to_wil(vif);
748
749	wil_err(wil, "ring modify is not supported for EDMA\n");
750
751	return -EOPNOTSUPP;
752	}
753
754	/* This function is used only for RX SW reorder */
755	static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid,
756	struct sk_buff *skb, struct wil_net_stats *stats)
757	{
758	u8 ftype;
759	u8 fc1;
760	int mid;
761	int tid;
762	u16 seq;
763	struct wil6210_vif *vif;
764
765	ftype = wil_rx_status_get_frame_type(wil, msg);
766	if (ftype == IEEE80211_FTYPE_DATA)
767	return 0;
768
769	fc1 = wil_rx_status_get_fc1(wil, msg);
770	mid = wil_rx_status_get_mid(msg);
771	tid = wil_rx_status_get_tid(msg);
772	seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg));
773	vif = wil->vifs[mid];
774
775	if (unlikely(!vif)) {
776	wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid);
777	return -EAGAIN;
778	}
779
780	wil_dbg_txrx(wil,
781	"Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
782	fc1, mid, cid, tid, seq);
783	if (stats)
784	stats->rx_non_data_frame++;
785	if (wil_is_back_req(fc: fc1)) {
786	wil_dbg_txrx(wil,
787	"BAR: MID %d CID %d TID %d Seq 0x%03x\n",
788	mid, cid, tid, seq);
789	wil_rx_bar(wil, vif, cid, tid, seq);
790	} else {
791	u32 sz = wil->use_compressed_rx_status ?
792	sizeof(struct wil_rx_status_compressed) :
793	sizeof(struct wil_rx_status_extended);
794
795	/* print again all info. One can enable only this
796	* without overhead for printing every Rx frame
797	*/
798	wil_dbg_txrx(wil,
799	"Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
800	fc1, mid, cid, tid, seq);
801	wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
802	(const void *)msg, sz, false);
803	wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
804	skb->data, skb_headlen(skb), false);
805	}
806
807	return -EAGAIN;
808	}
809
810	static int wil_rx_error_check_edma(struct wil6210_priv *wil,
811	struct sk_buff *skb,
812	struct wil_net_stats *stats)
813	{
814	int l2_rx_status;
815	void *msg = wil_skb_rxstatus(skb);
816
817	l2_rx_status = wil_rx_status_get_l2_rx_status(msg);
818	if (l2_rx_status != 0) {
819	wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n",
820	l2_rx_status);
821	/* Due to HW issue, KEY error will trigger a MIC error */
822	if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) {
823	wil_err_ratelimited(wil,
824	"L2 MIC/KEY error, dropping packet\n");
825	stats->rx_mic_error++;
826	}
827	if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) {
828	wil_err_ratelimited(wil,
829	"L2 KEY error, dropping packet\n");
830	stats->rx_key_error++;
831	}
832	if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) {
833	wil_err_ratelimited(wil,
834	"L2 REPLAY error, dropping packet\n");
835	stats->rx_replay++;
836	}
837	if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) {
838	wil_err_ratelimited(wil,
839	"L2 AMSDU error, dropping packet\n");
840	stats->rx_amsdu_error++;
841	}
842	return -EFAULT;
843	}
844
845	skb->ip_summed = wil_rx_status_get_checksum(msg, stats);
846
847	return 0;
848	}
849
850	static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
851	struct wil_status_ring *sring)
852	{
853	struct device *dev = wil_to_dev(wil);
854	struct wil_rx_status_extended msg1;
855	void *msg = &msg1;
856	u16 buff_id;
857	struct sk_buff *skb;
858	dma_addr_t pa;
859	struct wil_ring_rx_data *rxdata = &sring->rx_data;
860	unsigned int sz = wil->rx_buf_len;
861	struct wil_net_stats *stats = NULL;
862	u16 dmalen;
863	int cid;
864	bool eop, headstolen;
865	int delta;
866	u8 dr_bit;
867	u8 data_offset;
868	struct wil_rx_status_extended *s;
869	u16 sring_idx = sring - wil->srings;
870	int invalid_buff_id_retry;
871
872	BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb));
873
874	again:
875	wil_get_next_rx_status_msg(sring, dr_bit: &dr_bit, msg);
876
877	/* Completed handling all the ready status messages */
878	if (dr_bit != sring->desc_rdy_pol)
879	return NULL;
880
881	/* Extract the buffer ID from the status message */
882	buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg));
883
884	invalid_buff_id_retry = 0;
885	while (!buff_id) {
886	struct wil_rx_status_extended *s;
887
888	wil_dbg_txrx(wil,
889	"buff_id is not updated yet by HW, (swhead 0x%x)\n",
890	sring->swhead);
891	if (++invalid_buff_id_retry > MAX_INVALID_BUFF_ID_RETRY)
892	break;
893
894	/* Read the status message again */
895	s = (struct wil_rx_status_extended *)
896	(sring->va + (sring->elem_size * sring->swhead));
897	*(struct wil_rx_status_extended *)msg = *s;
898	buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg));
899	}
900
901	if (unlikely(!wil_val_in_range(buff_id, 1, wil->rx_buff_mgmt.size))) {
902	wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n",
903	buff_id, sring->swhead);
904	print_hex_dump(KERN_ERR, prefix_str: "RxS ", prefix_type: DUMP_PREFIX_OFFSET, rowsize: 16, groupsize: 1,
905	buf: msg, len: wil->use_compressed_rx_status ?
906	sizeof(struct wil_rx_status_compressed) :
907	sizeof(struct wil_rx_status_extended), ascii: false);
908
909	wil_rx_status_reset_buff_id(s: sring);
910	wil_sring_advance_swhead(sring);
911	sring->invalid_buff_id_cnt++;
912	goto again;
913	}
914
915	/* Extract the SKB from the rx_buff management array */
916	skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb;
917	wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL;
918	if (!skb) {
919	wil_err(wil, "No Rx skb at buff_id %d\n", buff_id);
920	wil_rx_status_reset_buff_id(s: sring);
921	/* Move the buffer from the active list to the free list */
922	list_move_tail(list: &wil->rx_buff_mgmt.buff_arr[buff_id].list,
923	head: &wil->rx_buff_mgmt.free);
924	wil_sring_advance_swhead(sring);
925	sring->invalid_buff_id_cnt++;
926	goto again;
927	}
928
929	wil_rx_status_reset_buff_id(s: sring);
930	wil_sring_advance_swhead(sring);
931
932	memcpy(&pa, skb->cb, sizeof(pa));
933	dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
934	dmalen = le16_to_cpu(wil_rx_status_get_length(msg));
935
936	trace_wil6210_rx_status(wil, use_compressed: wil->use_compressed_rx_status, buff_id,
937	msg);
938	wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n",
939	buff_id, sring_idx, dmalen);
940	wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
941	(const void *)msg, wil->use_compressed_rx_status ?
942	sizeof(struct wil_rx_status_compressed) :
943	sizeof(struct wil_rx_status_extended), false);
944
945	/* Move the buffer from the active list to the free list */
946	list_move_tail(list: &wil->rx_buff_mgmt.buff_arr[buff_id].list,
947	head: &wil->rx_buff_mgmt.free);
948
949	eop = wil_rx_status_get_eop(msg);
950
951	cid = wil_rx_status_get_cid(msg);
952	if (unlikely(!wil_val_in_range(cid, 0, wil->max_assoc_sta))) {
953	wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n",
954	cid, sring->swhead);
955	rxdata->skipping = true;
956	goto skipping;
957	}
958	stats = &wil->sta[cid].stats;
959
960	if (unlikely(dmalen < ETH_HLEN)) {
961	wil_dbg_txrx(wil, "Short frame, len = %d\n", dmalen);
962	stats->rx_short_frame++;
963	rxdata->skipping = true;
964	goto skipping;
965	}
966
967	if (unlikely(dmalen > sz)) {
968	wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
969	print_hex_dump(KERN_ERR, prefix_str: "RxS ", prefix_type: DUMP_PREFIX_OFFSET, rowsize: 16, groupsize: 1,
970	buf: msg, len: wil->use_compressed_rx_status ?
971	sizeof(struct wil_rx_status_compressed) :
972	sizeof(struct wil_rx_status_extended), ascii: false);
973
974	stats->rx_large_frame++;
975	rxdata->skipping = true;
976	}
977
978	skipping:
979	/* skipping indicates if a certain SKB should be dropped.
980	* It is set in case there is an error on the current SKB or in case
981	* of RX chaining: as long as we manage to merge the SKBs it will
982	* be false. once we have a bad SKB or we don't manage to merge SKBs
983	* it will be set to the !EOP value of the current SKB.
984	* This guarantees that all the following SKBs until EOP will also
985	* get dropped.
986	*/
987	if (unlikely(rxdata->skipping)) {
988	kfree_skb(skb);
989	if (rxdata->skb) {
990	kfree_skb(skb: rxdata->skb);
991	rxdata->skb = NULL;
992	}
993	rxdata->skipping = !eop;
994	goto again;
995	}
996
997	skb_trim(skb, len: dmalen);
998
999	prefetch(skb->data);
1000
1001	if (!rxdata->skb) {
1002	rxdata->skb = skb;
1003	} else {
1004	if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen,
1005	&delta))) {
1006	kfree_skb_partial(skb, head_stolen: headstolen);
1007	} else {
1008	wil_err(wil, "failed to merge skbs!\n");
1009	kfree_skb(skb);
1010	kfree_skb(skb: rxdata->skb);
1011	rxdata->skb = NULL;
1012	rxdata->skipping = !eop;
1013	goto again;
1014	}
1015	}
1016
1017	if (!eop)
1018	goto again;
1019
1020	/* reaching here rxdata->skb always contains a full packet */
1021	skb = rxdata->skb;
1022	rxdata->skb = NULL;
1023	rxdata->skipping = false;
1024
1025	if (stats) {
1026	stats->last_mcs_rx = wil_rx_status_get_mcs(msg);
1027	if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs))
1028	stats->rx_per_mcs[stats->last_mcs_rx]++;
1029	else if (stats->last_mcs_rx == WIL_EXTENDED_MCS_26)
1030	stats->rx_per_mcs[WIL_BASE_MCS_FOR_EXTENDED_26]++;
1031
1032	stats->last_cb_mode_rx = wil_rx_status_get_cb_mode(msg);
1033	}
1034
1035	if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status &&
1036	wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) {
1037	kfree_skb(skb);
1038	goto again;
1039	}
1040
1041	/* Compensate for the HW data alignment according to the status
1042	* message
1043	*/
1044	data_offset = wil_rx_status_get_data_offset(msg);
1045	if (data_offset == 0xFF ||
1046	data_offset > WIL_EDMA_MAX_DATA_OFFSET) {
1047	wil_err(wil, "Unexpected data offset %d\n", data_offset);
1048	kfree_skb(skb);
1049	goto again;
1050	}
1051
1052	skb_pull(skb, len: data_offset);
1053
1054	wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
1055	skb->data, skb_headlen(skb), false);
1056
1057	/* Has to be done after dma_unmap_single as skb->cb is also
1058	* used for holding the pa
1059	*/
1060	s = wil_skb_rxstatus(skb);
1061	memcpy(s, msg, sring->elem_size);
1062
1063	return skb;
1064	}
1065
1066	void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota)
1067	{
1068	struct net_device *ndev;
1069	struct wil_ring *ring = &wil->ring_rx;
1070	struct wil_status_ring *sring;
1071	struct sk_buff *skb;
1072	int i;
1073
1074	if (unlikely(!ring->va)) {
1075	wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
1076	return;
1077	}
1078	wil_dbg_txrx(wil, "rx_handle\n");
1079
1080	for (i = 0; i < wil->num_rx_status_rings; i++) {
1081	sring = &wil->srings[i];
1082	if (unlikely(!sring->va)) {
1083	wil_err(wil,
1084	"Rx IRQ while Rx status ring %d not yet initialized\n",
1085	i);
1086	continue;
1087	}
1088
1089	while ((*quota > 0) &&
1090	(NULL != (skb =
1091	wil_sring_reap_rx_edma(wil, sring)))) {
1092	(*quota)--;
1093	if (wil->use_rx_hw_reordering) {
1094	void *msg = wil_skb_rxstatus(skb);
1095	int mid = wil_rx_status_get_mid(msg);
1096	struct wil6210_vif *vif = wil->vifs[mid];
1097
1098	if (unlikely(!vif)) {
1099	wil_dbg_txrx(wil,
1100	"RX desc invalid mid %d",
1101	mid);
1102	kfree_skb(skb);
1103	continue;
1104	}
1105	ndev = vif_to_ndev(vif);
1106	wil_netif_rx_any(skb, ndev);
1107	} else {
1108	wil_rx_reorder(wil, skb);
1109	}
1110	}
1111
1112	wil_w(wil, reg: sring->hwtail, val: (sring->swhead - 1) % sring->size);
1113	}
1114
1115	wil_rx_refill_edma(wil);
1116	}
1117
1118	static int wil_tx_desc_map_edma(union wil_tx_desc *desc,
1119	dma_addr_t pa,
1120	u32 len,
1121	int ring_index)
1122	{
1123	struct wil_tx_enhanced_desc *d =
1124	(struct wil_tx_enhanced_desc *)&desc->enhanced;
1125
1126	memset(d, 0, sizeof(struct wil_tx_enhanced_desc));
1127
1128	wil_desc_set_addr_edma(addr: &d->dma.addr, addr_high_high: &d->dma.addr_high_high, pa);
1129
1130	/* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
1131	d->dma.length = cpu_to_le16((u16)len);
1132	d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS);
1133	/* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi;
1134	* 3 - eth mode
1135	*/
1136	d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
1137	(0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
1138
1139	return 0;
1140	}
1141
1142	static inline void
1143	wil_get_next_tx_status_msg(struct wil_status_ring *sring, u8 *dr_bit,
1144	struct wil_ring_tx_status *msg)
1145	{
1146	struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *)
1147	(sring->va + (sring->elem_size * sring->swhead));
1148
1149	*dr_bit = _msg->desc_ready >> TX_STATUS_DESC_READY_POS;
1150	/* make sure dr_bit is read before the rest of status msg */
1151	rmb();
1152	*msg = *_msg;
1153	}
1154
1155	/* Clean up transmitted skb's from the Tx descriptor RING.
1156	* Return number of descriptors cleared.
1157	*/
1158	int wil_tx_sring_handler(struct wil6210_priv *wil,
1159	struct wil_status_ring *sring)
1160	{
1161	struct net_device *ndev;
1162	struct device *dev = wil_to_dev(wil);
1163	struct wil_ring *ring = NULL;
1164	struct wil_ring_tx_data *txdata;
1165	/* Total number of completed descriptors in all descriptor rings */
1166	int desc_cnt = 0;
1167	int cid;
1168	struct wil_net_stats *stats;
1169	struct wil_tx_enhanced_desc *_d;
1170	unsigned int ring_id;
1171	unsigned int num_descs, num_statuses = 0;
1172	int i;
1173	u8 dr_bit; /* Descriptor Ready bit */
1174	struct wil_ring_tx_status msg;
1175	struct wil6210_vif *vif;
1176	int used_before_complete;
1177	int used_new;
1178
1179	wil_get_next_tx_status_msg(sring, dr_bit: &dr_bit, msg: &msg);
1180
1181	/* Process completion messages while DR bit has the expected polarity */
1182	while (dr_bit == sring->desc_rdy_pol) {
1183	num_descs = msg.num_descriptors;
1184	if (!num_descs) {
1185	wil_err(wil, "invalid num_descs 0\n");
1186	goto again;
1187	}
1188
1189	/* Find the corresponding descriptor ring */
1190	ring_id = msg.ring_id;
1191
1192	if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) {
1193	wil_err(wil, "invalid ring id %d\n", ring_id);
1194	goto again;
1195	}
1196	ring = &wil->ring_tx[ring_id];
1197	if (unlikely(!ring->va)) {
1198	wil_err(wil, "Tx irq[%d]: ring not initialized\n",
1199	ring_id);
1200	goto again;
1201	}
1202	txdata = &wil->ring_tx_data[ring_id];
1203	if (unlikely(!txdata->enabled)) {
1204	wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id);
1205	goto again;
1206	}
1207	vif = wil->vifs[txdata->mid];
1208	if (unlikely(!vif)) {
1209	wil_dbg_txrx(wil, "invalid MID %d for ring %d\n",
1210	txdata->mid, ring_id);
1211	goto again;
1212	}
1213
1214	ndev = vif_to_ndev(vif);
1215
1216	cid = wil->ring2cid_tid[ring_id][0];
1217	stats = (cid < wil->max_assoc_sta) ? &wil->sta[cid].stats :
1218	NULL;
1219
1220	wil_dbg_txrx(wil,
1221	"tx_status: completed desc_ring (%d), num_descs (%d)\n",
1222	ring_id, num_descs);
1223
1224	used_before_complete = wil_ring_used_tx(ring);
1225
1226	for (i = 0 ; i < num_descs; ++i) {
1227	struct wil_ctx *ctx = &ring->ctx[ring->swtail];
1228	struct wil_tx_enhanced_desc dd, *d = &dd;
1229	u16 dmalen;
1230	struct sk_buff *skb = ctx->skb;
1231
1232	_d = (struct wil_tx_enhanced_desc *)
1233	&ring->va[ring->swtail].tx.enhanced;
1234	*d = *_d;
1235
1236	dmalen = le16_to_cpu(d->dma.length);
1237	trace_wil6210_tx_status(msg: &msg, index: ring->swtail, len: dmalen);
1238	wil_dbg_txrx(wil,
1239	"TxC[%2d][%3d] : %d bytes, status 0x%02x\n",
1240	ring_id, ring->swtail, dmalen,
1241	msg.status);
1242	wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4,
1243	(const void *)&msg, sizeof(msg),
1244	false);
1245
1246	wil_tx_desc_unmap_edma(dev,
1247	desc: (union wil_tx_desc *)d,
1248	ctx);
1249
1250	if (skb) {
1251	if (likely(msg.status == 0)) {
1252	ndev->stats.tx_packets++;
1253	ndev->stats.tx_bytes += skb->len;
1254	if (stats) {
1255	stats->tx_packets++;
1256	stats->tx_bytes += skb->len;
1257
1258	wil_tx_latency_calc(wil, skb,
1259	sta: &wil->sta[cid]);
1260	}
1261	} else {
1262	ndev->stats.tx_errors++;
1263	if (stats)
1264	stats->tx_errors++;
1265	}
1266
1267	if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1268	wil_tx_complete_handle_eapol(vif, skb);
1269
1270	wil_consume_skb(skb, acked: msg.status == 0);
1271	}
1272	memset(ctx, 0, sizeof(*ctx));
1273	/* Make sure the ctx is zeroed before updating the tail
1274	* to prevent a case where wil_tx_ring will see
1275	* this descriptor as used and handle it before ctx zero
1276	* is completed.
1277	*/
1278	wmb();
1279
1280	ring->swtail = wil_ring_next_tail(ring);
1281
1282	desc_cnt++;
1283	}
1284
1285	/* performance monitoring */
1286	used_new = wil_ring_used_tx(ring);
1287	if (wil_val_in_range(val: wil->ring_idle_trsh,
1288	min: used_new, max: used_before_complete)) {
1289	wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n",
1290	ring_id, used_before_complete, used_new);
1291	txdata->last_idle = get_cycles();
1292	}
1293
1294	again:
1295	num_statuses++;
1296	if (num_statuses % WIL_EDMA_TX_SRING_UPDATE_HW_TAIL == 0)
1297	/* update HW tail to allow HW to push new statuses */
1298	wil_w(wil, reg: sring->hwtail, val: sring->swhead);
1299
1300	wil_sring_advance_swhead(sring);
1301
1302	wil_get_next_tx_status_msg(sring, dr_bit: &dr_bit, msg: &msg);
1303	}
1304
1305	/* shall we wake net queues? */
1306	if (desc_cnt)
1307	wil_update_net_queues(wil, vif, NULL, should_stop: false);
1308
1309	if (num_statuses % WIL_EDMA_TX_SRING_UPDATE_HW_TAIL != 0)
1310	/* Update the HW tail ptr (RD ptr) */
1311	wil_w(wil, reg: sring->hwtail, val: (sring->swhead - 1) % sring->size);
1312
1313	return desc_cnt;
1314	}
1315
1316	/* Sets the descriptor @d up for csum and/or TSO offloading. The corresponding
1317	* @skb is used to obtain the protocol and headers length.
1318	* @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data,
1319	* 2 - middle, 3 - last descriptor.
1320	*/
1321	static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d,
1322	int tso_desc_type, bool is_ipv4,
1323	int tcp_hdr_len,
1324	int skb_net_hdr_len,
1325	int mss)
1326	{
1327	/* Number of descriptors */
1328	d->mac.d[2] |= 1;
1329	/* Maximum Segment Size */
1330	d->mac.tso_mss |= cpu_to_le16(mss >> 2);
1331	/* L4 header len: TCP header length */
1332	d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK;
1333	/* EOP, TSO desc type, Segmentation enable,
1334	* Insert IPv4 and TCP / UDP Checksum
1335	*/
1336	d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) |
1337	tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS |
1338	BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) |
1339	BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) |
1340	BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS);
1341	/* Calculate pseudo-header */
1342	d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) |
1343	BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS);
1344	/* IP Header Length */
1345	d->dma.ip_length |= skb_net_hdr_len;
1346	/* MAC header length and IP address family*/
1347	d->dma.b11 |= ETH_HLEN |
1348	is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS;
1349	}
1350
1351	static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr,
1352	int len, uint i, int tso_desc_type,
1353	skb_frag_t *frag, struct wil_ring *ring,
1354	struct sk_buff *skb, bool is_ipv4,
1355	int tcp_hdr_len, int skb_net_hdr_len,
1356	int mss, int *descs_used)
1357	{
1358	struct device *dev = wil_to_dev(wil);
1359	struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *)
1360	&ring->va[i].tx.enhanced;
1361	struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem;
1362	int ring_index = ring - wil->ring_tx;
1363	dma_addr_t pa;
1364
1365	if (len == 0)
1366	return 0;
1367
1368	if (!frag) {
1369	pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE);
1370	ring->ctx[i].mapped_as = wil_mapped_as_single;
1371	} else {
1372	pa = skb_frag_dma_map(dev, frag, offset: 0, size: len, dir: DMA_TO_DEVICE);
1373	ring->ctx[i].mapped_as = wil_mapped_as_page;
1374	}
1375	if (unlikely(dma_mapping_error(dev, pa))) {
1376	wil_err(wil, "TSO: Skb DMA map error\n");
1377	return -EINVAL;
1378	}
1379
1380	wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa,
1381	len, ring_index);
1382	wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4,
1383	tcp_hdr_len,
1384	skb_net_hdr_len, mss);
1385
1386	/* hold reference to skb
1387	* to prevent skb release before accounting
1388	* in case of immediate "tx done"
1389	*/
1390	if (tso_desc_type == wil_tso_type_lst)
1391	ring->ctx[i].skb = skb_get(skb);
1392
1393	wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1394	(const void *)d, sizeof(*d), false);
1395
1396	*_desc = *d;
1397	(*descs_used)++;
1398
1399	return 0;
1400	}
1401
1402	static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil,
1403	struct wil6210_vif *vif,
1404	struct wil_ring *ring,
1405	struct sk_buff *skb)
1406	{
1407	int ring_index = ring - wil->ring_tx;
1408	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1409	int nr_frags = skb_shinfo(skb)->nr_frags;
1410	int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */
1411	int used, avail = wil_ring_avail_tx(ring);
1412	int f, hdrlen, headlen;
1413	int gso_type;
1414	bool is_ipv4;
1415	u32 swhead = ring->swhead;
1416	int descs_used = 0; /* total number of used descriptors */
1417	int rc = -EINVAL;
1418	int tcp_hdr_len;
1419	int skb_net_hdr_len;
1420	int mss = skb_shinfo(skb)->gso_size;
1421
1422	wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len,
1423	ring_index);
1424
1425	if (unlikely(!txdata->enabled))
1426	return -EINVAL;
1427
1428	if (unlikely(avail < min_desc_required)) {
1429	wil_err_ratelimited(wil,
1430	"TSO: Tx ring[%2d] full. No space for %d fragments\n",
1431	ring_index, min_desc_required);
1432	return -ENOMEM;
1433	}
1434
1435	gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4);
1436	switch (gso_type) {
1437	case SKB_GSO_TCPV4:
1438	is_ipv4 = true;
1439	break;
1440	case SKB_GSO_TCPV6:
1441	is_ipv4 = false;
1442	break;
1443	default:
1444	return -EINVAL;
1445	}
1446
1447	if (skb->ip_summed != CHECKSUM_PARTIAL)
1448	return -EINVAL;
1449
1450	/* tcp header length and skb network header length are fixed for all
1451	* packet's descriptors - read them once here
1452	*/
1453	tcp_hdr_len = tcp_hdrlen(skb);
1454	skb_net_hdr_len = skb_network_header_len(skb);
1455
1456	/* First descriptor must contain the header only
1457	* Header Length = MAC header len + IP header len + TCP header len
1458	*/
1459	hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len;
1460	wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n",
1461	hdrlen);
1462	rc = wil_tx_tso_gen_desc(wil, buff_addr: skb->data, len: hdrlen, i: swhead,
1463	tso_desc_type: wil_tso_type_hdr, NULL, ring, skb,
1464	is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1465	mss, descs_used: &descs_used);
1466	if (rc)
1467	return -EINVAL;
1468
1469	/* Second descriptor contains the head */
1470	headlen = skb_headlen(skb) - hdrlen;
1471	wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen);
1472	rc = wil_tx_tso_gen_desc(wil, buff_addr: skb->data + hdrlen, len: headlen,
1473	i: (swhead + descs_used) % ring->size,
1474	tso_desc_type: (nr_frags != 0) ? wil_tso_type_first :
1475	wil_tso_type_lst, NULL, ring, skb,
1476	is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1477	mss, descs_used: &descs_used);
1478	if (rc)
1479	goto mem_error;
1480
1481	/* Rest of the descriptors are from the SKB fragments */
1482	for (f = 0; f < nr_frags; f++) {
1483	skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1484	int len = skb_frag_size(frag);
1485
1486	wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f,
1487	len, descs_used);
1488
1489	rc = wil_tx_tso_gen_desc(wil, NULL, len,
1490	i: (swhead + descs_used) % ring->size,
1491	tso_desc_type: (f != nr_frags - 1) ?
1492	wil_tso_type_mid : wil_tso_type_lst,
1493	frag, ring, skb, is_ipv4,
1494	tcp_hdr_len, skb_net_hdr_len,
1495	mss, descs_used: &descs_used);
1496	if (rc)
1497	goto mem_error;
1498	}
1499
1500	/* performance monitoring */
1501	used = wil_ring_used_tx(ring);
1502	if (wil_val_in_range(val: wil->ring_idle_trsh,
1503	min: used, max: used + descs_used)) {
1504	txdata->idle += get_cycles() - txdata->last_idle;
1505	wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n",
1506	ring_index, used, used + descs_used);
1507	}
1508
1509	/* advance swhead */
1510	wil_ring_advance_head(ring, n: descs_used);
1511	wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead);
1512
1513	/* make sure all writes to descriptors (shared memory) are done before
1514	* committing them to HW
1515	*/
1516	wmb();
1517
1518	if (wil->tx_latency)
1519	*(ktime_t *)&skb->cb = ktime_get();
1520	else
1521	memset(skb->cb, 0, sizeof(ktime_t));
1522
1523	wil_w(wil, reg: ring->hwtail, val: ring->swhead);
1524
1525	return 0;
1526
1527	mem_error:
1528	while (descs_used > 0) {
1529	struct device *dev = wil_to_dev(wil);
1530	struct wil_ctx *ctx;
1531	int i = (swhead + descs_used - 1) % ring->size;
1532	struct wil_tx_enhanced_desc dd, *d = &dd;
1533	struct wil_tx_enhanced_desc *_desc =
1534	(struct wil_tx_enhanced_desc *)
1535	&ring->va[i].tx.enhanced;
1536
1537	*d = *_desc;
1538	ctx = &ring->ctx[i];
1539	wil_tx_desc_unmap_edma(dev, desc: (union wil_tx_desc *)d, ctx);
1540	memset(ctx, 0, sizeof(*ctx));
1541	descs_used--;
1542	}
1543	return rc;
1544	}
1545
1546	static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id,
1547	int size)
1548	{
1549	struct wil6210_priv *wil = vif_to_wil(vif);
1550	struct wil_ring *ring = &wil->ring_tx[ring_id];
1551	int rc;
1552	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
1553
1554	wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n",
1555	ring_id, wil->tx_sring_idx);
1556
1557	lockdep_assert_held(&wil->mutex);
1558
1559	wil_tx_data_init(txdata);
1560	ring->size = size;
1561	ring->is_rx = false;
1562	rc = wil_ring_alloc_desc_ring(wil, ring);
1563	if (rc)
1564	goto out;
1565
1566	wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */
1567	wil->ring2cid_tid[ring_id][1] = 0; /* TID */
1568	if (!vif->privacy)
1569	txdata->dot1x_open = true;
1570
1571	rc = wil_wmi_bcast_desc_ring_add(vif, ring_id);
1572	if (rc)
1573	goto out_free;
1574
1575	return 0;
1576
1577	out_free:
1578	spin_lock_bh(lock: &txdata->lock);
1579	txdata->enabled = 0;
1580	txdata->dot1x_open = false;
1581	spin_unlock_bh(lock: &txdata->lock);
1582	wil_ring_free_edma(wil, ring);
1583
1584	out:
1585	return rc;
1586	}
1587
1588	static void wil_tx_fini_edma(struct wil6210_priv *wil)
1589	{
1590	struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx];
1591
1592	wil_dbg_misc(wil, "free TX sring\n");
1593
1594	wil_sring_free(wil, sring);
1595	}
1596
1597	static void wil_rx_data_free(struct wil_status_ring *sring)
1598	{
1599	if (!sring)
1600	return;
1601
1602	kfree_skb(skb: sring->rx_data.skb);
1603	sring->rx_data.skb = NULL;
1604	}
1605
1606	static void wil_rx_fini_edma(struct wil6210_priv *wil)
1607	{
1608	struct wil_ring *ring = &wil->ring_rx;
1609	int i;
1610
1611	wil_dbg_misc(wil, "rx_fini_edma\n");
1612
1613	wil_ring_free_edma(wil, ring);
1614
1615	for (i = 0; i < wil->num_rx_status_rings; i++) {
1616	wil_rx_data_free(sring: &wil->srings[i]);
1617	wil_sring_free(wil, sring: &wil->srings[i]);
1618	}
1619
1620	wil_free_rx_buff_arr(wil);
1621	}
1622
1623	void wil_init_txrx_ops_edma(struct wil6210_priv *wil)
1624	{
1625	wil->txrx_ops.configure_interrupt_moderation =
1626	wil_configure_interrupt_moderation_edma;
1627	/* TX ops */
1628	wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma;
1629	wil->txrx_ops.ring_fini_tx = wil_ring_free_edma;
1630	wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma;
1631	wil->txrx_ops.tx_init = wil_tx_init_edma;
1632	wil->txrx_ops.tx_fini = wil_tx_fini_edma;
1633	wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma;
1634	wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma;
1635	wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma;
1636	wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma;
1637	/* RX ops */
1638	wil->txrx_ops.rx_init = wil_rx_init_edma;
1639	wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma;
1640	wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma;
1641	wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma;
1642	wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma;
1643	wil->txrx_ops.rx_error_check = wil_rx_error_check_edma;
1644	wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma;
1645	wil->txrx_ops.rx_fini = wil_rx_fini_edma;
1646	}
1647
1648