| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef B43_RADIO_2057_H_ |
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| 3 | #define B43_RADIO_2057_H_ |
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| 4 | |
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| 5 | #include <linux/types.h> |
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| 6 | |
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| 7 | #include "tables_nphy.h" |
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| 8 | |
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| 9 | #define R2057_DACBUF_VINCM_CORE0 0x000 |
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| 10 | #define R2057_IDCODE 0x001 |
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| 11 | #define R2057_RCCAL_MASTER 0x002 |
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| 12 | #define R2057_RCCAL_CAP_SIZE 0x003 |
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| 13 | #define R2057_RCAL_CONFIG 0x004 |
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| 14 | #define R2057_GPAIO_CONFIG 0x005 |
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| 15 | #define R2057_GPAIO_SEL1 0x006 |
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| 16 | #define R2057_GPAIO_SEL0 0x007 |
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| 17 | #define R2057_CLPO_CONFIG 0x008 |
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| 18 | #define R2057_BANDGAP_CONFIG 0x009 |
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| 19 | #define R2057_BANDGAP_RCAL_TRIM 0x00a |
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| 20 | #define R2057_AFEREG_CONFIG 0x00b |
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| 21 | #define R2057_TEMPSENSE_CONFIG 0x00c |
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| 22 | #define R2057_XTAL_CONFIG1 0x00d |
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| 23 | #define R2057_XTAL_ICORE_SIZE 0x00e |
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| 24 | #define R2057_XTAL_BUF_SIZE 0x00f |
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| 25 | #define R2057_XTAL_PULLCAP_SIZE 0x010 |
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| 26 | #define R2057_RFPLL_MASTER 0x011 |
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| 27 | #define R2057_VCOMONITOR_VTH_L 0x012 |
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| 28 | #define R2057_VCOMONITOR_VTH_H 0x013 |
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| 29 | #define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014 |
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| 30 | #define R2057_VCO_VARCSIZE_IDAC 0x015 |
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| 31 | #define R2057_VCOCAL_COUNTVAL0 0x016 |
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| 32 | #define R2057_VCOCAL_COUNTVAL1 0x017 |
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| 33 | #define R2057_VCOCAL_INTCLK_COUNT 0x018 |
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| 34 | #define R2057_VCOCAL_MASTER 0x019 |
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| 35 | #define R2057_VCOCAL_NUMCAPCHANGE 0x01a |
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| 36 | #define R2057_VCOCAL_WINSIZE 0x01b |
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| 37 | #define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c |
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| 38 | #define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d |
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| 39 | #define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e |
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| 40 | #define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f |
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| 41 | #define R2057_VCO_FORCECAPEN_FORCECAP1 0x020 |
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| 42 | #define R2057_VCO_FORCECAP0 0x021 |
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| 43 | #define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022 |
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| 44 | #define R2057_RFPLL_PFD_RESET_PW 0x023 |
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| 45 | #define R2057_RFPLL_LOOPFILTER_R2 0x024 |
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| 46 | #define R2057_RFPLL_LOOPFILTER_R1 0x025 |
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| 47 | #define R2057_RFPLL_LOOPFILTER_C3 0x026 |
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| 48 | #define R2057_RFPLL_LOOPFILTER_C2 0x027 |
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| 49 | #define R2057_RFPLL_LOOPFILTER_C1 0x028 |
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| 50 | #define R2057_CP_KPD_IDAC 0x029 |
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| 51 | #define R2057_RFPLL_IDACS 0x02a |
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| 52 | #define R2057_RFPLL_MISC_EN 0x02b |
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| 53 | #define R2057_RFPLL_MMD0 0x02c |
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| 54 | #define R2057_RFPLL_MMD1 0x02d |
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| 55 | #define R2057_RFPLL_MISC_CAL_RESETN 0x02e |
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| 56 | #define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f |
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| 57 | #define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030 |
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| 58 | #define R2057_VCOCAL_READCAP0 0x031 |
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| 59 | #define R2057_VCOCAL_READCAP1 0x032 |
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| 60 | #define R2057_VCOCAL_STATUS 0x033 |
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| 61 | #define R2057_LOGEN_PUS 0x034 |
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| 62 | #define R2057_LOGEN_PTAT_RESETS 0x035 |
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| 63 | #define R2057_VCOBUF_IDACS 0x036 |
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| 64 | #define R2057_VCOBUF_TUNE 0x037 |
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| 65 | #define R2057_CMOSBUF_TX2GQ_IDACS 0x038 |
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| 66 | #define R2057_CMOSBUF_TX2GI_IDACS 0x039 |
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| 67 | #define R2057_CMOSBUF_TX5GQ_IDACS 0x03a |
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| 68 | #define R2057_CMOSBUF_TX5GI_IDACS 0x03b |
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| 69 | #define R2057_CMOSBUF_RX2GQ_IDACS 0x03c |
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| 70 | #define R2057_CMOSBUF_RX2GI_IDACS 0x03d |
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| 71 | #define R2057_CMOSBUF_RX5GQ_IDACS 0x03e |
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| 72 | #define R2057_CMOSBUF_RX5GI_IDACS 0x03f |
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| 73 | #define R2057_LOGEN_MX2G_IDACS 0x040 |
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| 74 | #define R2057_LOGEN_MX2G_TUNE 0x041 |
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| 75 | #define R2057_LOGEN_MX5G_IDACS 0x042 |
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| 76 | #define R2057_LOGEN_MX5G_TUNE 0x043 |
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| 77 | #define R2057_LOGEN_MX5G_RCCR 0x044 |
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| 78 | #define R2057_LOGEN_INDBUF2G_IDAC 0x045 |
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| 79 | #define R2057_LOGEN_INDBUF2G_IBOOST 0x046 |
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| 80 | #define R2057_LOGEN_INDBUF2G_TUNE 0x047 |
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| 81 | #define R2057_LOGEN_INDBUF5G_IDAC 0x048 |
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| 82 | #define R2057_LOGEN_INDBUF5G_IBOOST 0x049 |
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| 83 | #define R2057_LOGEN_INDBUF5G_TUNE 0x04a |
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| 84 | #define R2057_CMOSBUF_TX_RCCR 0x04b |
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| 85 | #define R2057_CMOSBUF_RX_RCCR 0x04c |
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| 86 | #define R2057_LOGEN_SEL_PKDET 0x04d |
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| 87 | #define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e |
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| 88 | |
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| 89 | /* MISC core 0 */ |
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| 90 | #define R2057_RXTXBIAS_CONFIG_CORE0 0x04f |
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| 91 | #define R2057_TXGM_TXRF_PUS_CORE0 0x050 |
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| 92 | #define R2057_TXGM_IDAC_BLEED_CORE0 0x051 |
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| 93 | #define R2057_TXGM_GAIN_CORE0 0x056 |
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| 94 | #define R2057_TXGM2G_PKDET_PUS_CORE0 0x057 |
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| 95 | #define R2057_PAD2G_PTATS_CORE0 0x058 |
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| 96 | #define R2057_PAD2G_IDACS_CORE0 0x059 |
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| 97 | #define R2057_PAD2G_BOOST_PU_CORE0 0x05a |
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| 98 | #define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b |
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| 99 | #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c |
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| 100 | #define R2057_TXMIX2G_LODC_CORE0 0x05d |
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| 101 | #define R2057_PAD2G_TUNE_PUS_CORE0 0x05e |
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| 102 | #define R2057_IPA2G_GAIN_CORE0 0x05f |
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| 103 | #define R2057_TSSI2G_SPARE1_CORE0 0x060 |
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| 104 | #define R2057_TSSI2G_SPARE2_CORE0 0x061 |
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| 105 | #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062 |
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| 106 | #define R2057_IPA2G_IMAIN_CORE0 0x063 |
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| 107 | #define R2057_IPA2G_CASCONV_CORE0 0x064 |
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| 108 | #define R2057_IPA2G_CASCOFFV_CORE0 0x065 |
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| 109 | #define R2057_IPA2G_BIAS_FILTER_CORE0 0x066 |
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| 110 | #define R2057_TX5G_PKDET_CORE0 0x069 |
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| 111 | #define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a |
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| 112 | #define R2057_PAD5G_PTATS1_CORE0 0x06b |
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| 113 | #define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c |
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| 114 | #define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d |
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| 115 | #define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e |
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| 116 | #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f |
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| 117 | #define R2057_PGA_BOOST_TUNE_CORE0 0x070 |
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| 118 | #define R2057_PGA_GAIN_CORE0 0x071 |
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| 119 | #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072 |
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| 120 | #define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073 |
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| 121 | #define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074 |
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| 122 | #define R2057_IPA5G_IAUX_CORE0 0x075 |
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| 123 | #define R2057_IPA5G_GAIN_CORE0 0x076 |
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| 124 | #define R2057_TSSI5G_SPARE1_CORE0 0x077 |
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| 125 | #define R2057_TSSI5G_SPARE2_CORE0 0x078 |
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| 126 | #define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079 |
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| 127 | #define R2057_IPA5G_PTAT_CORE0 0x07a |
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| 128 | #define R2057_IPA5G_IMAIN_CORE0 0x07b |
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| 129 | #define R2057_IPA5G_CASCONV_CORE0 0x07c |
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| 130 | #define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d |
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| 131 | #define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080 |
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| 132 | #define R2057_TR2G_CONFIG1_CORE0_NU 0x081 |
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| 133 | #define R2057_TR2G_CONFIG2_CORE0_NU 0x082 |
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| 134 | #define R2057_LNA5G_RFEN_CORE0 0x083 |
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| 135 | #define R2057_TR5G_CONFIG2_CORE0_NU 0x084 |
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| 136 | #define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085 |
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| 137 | #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086 |
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| 138 | #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087 |
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| 139 | #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088 |
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| 140 | #define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089 |
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| 141 | #define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a |
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| 142 | #define R2057_LNA2_IAUX_PTAT_CORE0 0x08b |
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| 143 | #define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c |
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| 144 | #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d |
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| 145 | #define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e |
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| 146 | #define R2057_TIA_CONFIG_CORE0 0x08f |
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| 147 | #define R2057_TIA_IQGAIN_CORE0 0x090 |
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| 148 | #define R2057_TIA_IBIAS2_CORE0 0x091 |
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| 149 | #define R2057_TIA_IBIAS1_CORE0 0x092 |
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| 150 | #define R2057_TIA_SPARE_Q_CORE0 0x093 |
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| 151 | #define R2057_TIA_SPARE_I_CORE0 0x094 |
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| 152 | #define R2057_RXMIX2G_PUS_CORE0 0x095 |
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| 153 | #define R2057_RXMIX2G_VCMREFS_CORE0 0x096 |
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| 154 | #define R2057_RXMIX2G_LODC_QI_CORE0 0x097 |
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| 155 | #define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098 |
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| 156 | #define R2057_LNA2G_GAIN_CORE0 0x099 |
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| 157 | #define R2057_LNA2G_TUNE_CORE0 0x09a |
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| 158 | #define R2057_RXMIX5G_PUS_CORE0 0x09b |
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| 159 | #define R2057_RXMIX5G_VCMREFS_CORE0 0x09c |
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| 160 | #define R2057_RXMIX5G_LODC_QI_CORE0 0x09d |
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| 161 | #define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e |
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| 162 | #define R2057_LNA5G_GAIN_CORE0 0x09f |
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| 163 | #define R2057_LNA5G_TUNE_CORE0 0x0a0 |
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| 164 | #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1 |
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| 165 | #define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2 |
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| 166 | #define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3 |
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| 167 | #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4 |
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| 168 | #define R2057_TXBUF_VINCM_CORE0 0x0a5 |
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| 169 | #define R2057_TXBUF_IDACS_CORE0 0x0a6 |
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| 170 | #define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7 |
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| 171 | #define R2057_RXBB_CC_CORE0 0x0a8 |
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| 172 | #define R2057_RXBB_SPARE3_CORE0 0x0a9 |
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| 173 | #define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa |
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| 174 | #define R2057_LPF_IDACS_CORE0 0x0ab |
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| 175 | #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac |
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| 176 | #define R2057_TXBUF_GAIN_CORE0 0x0ad |
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| 177 | #define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae |
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| 178 | #define R2057_RXBUF_DEGEN_CORE0 0x0af |
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| 179 | #define R2057_RXBB_SPARE2_CORE0 0x0b0 |
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| 180 | #define R2057_RXBB_SPARE1_CORE0 0x0b1 |
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| 181 | #define 0x0b2 |
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| 182 | #define R2057_W2_MASTER_CORE0 0x0b3 |
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| 183 | #define R2057_NB_MASTER_CORE0 0x0b4 |
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| 184 | #define R2057_W2_IDACS0_Q_CORE0 0x0b5 |
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| 185 | #define R2057_W2_IDACS1_Q_CORE0 0x0b6 |
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| 186 | #define R2057_W2_IDACS0_I_CORE0 0x0b7 |
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| 187 | #define R2057_W2_IDACS1_I_CORE0 0x0b8 |
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| 188 | #define 0x0b9 |
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| 189 | #define R2057_NB_IDACS_Q_CORE0 0x0ba |
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| 190 | #define R2057_NB_IDACS_I_CORE0 0x0bb |
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| 191 | #define R2057_BACKUP4_CORE0 0x0c1 |
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| 192 | #define R2057_BACKUP3_CORE0 0x0c2 |
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| 193 | #define R2057_BACKUP2_CORE0 0x0c3 |
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| 194 | #define R2057_BACKUP1_CORE0 0x0c4 |
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| 195 | #define R2057_SPARE16_CORE0 0x0c5 |
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| 196 | #define R2057_SPARE15_CORE0 0x0c6 |
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| 197 | #define R2057_SPARE14_CORE0 0x0c7 |
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| 198 | #define R2057_SPARE13_CORE0 0x0c8 |
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| 199 | #define R2057_SPARE12_CORE0 0x0c9 |
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| 200 | #define R2057_SPARE11_CORE0 0x0ca |
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| 201 | #define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb |
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| 202 | #define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc |
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| 203 | #define R2057_IQTEST_SEL_PU 0x0cd |
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| 204 | #define R2057_XTAL_CONFIG2 0x0ce |
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| 205 | #define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf |
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| 206 | #define R2057_TXLPF_RCCAL_CORE0 0x0d0 |
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| 207 | #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 |
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| 208 | #define R2057_LPF_GAIN_CORE0 0x0d2 |
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| 209 | #define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 |
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| 210 | |
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| 211 | /* MISC core 1 */ |
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| 212 | #define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 |
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| 213 | #define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 |
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| 214 | #define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 |
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| 215 | #define R2057_TXGM_GAIN_CORE1 0x0db |
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| 216 | #define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc |
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| 217 | #define R2057_PAD2G_PTATS_CORE1 0x0dd |
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| 218 | #define R2057_PAD2G_IDACS_CORE1 0x0de |
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| 219 | #define R2057_PAD2G_BOOST_PU_CORE1 0x0df |
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| 220 | #define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0 |
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| 221 | #define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1 |
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| 222 | #define R2057_TXMIX2G_LODC_CORE1 0x0e2 |
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| 223 | #define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3 |
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| 224 | #define R2057_IPA2G_GAIN_CORE1 0x0e4 |
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| 225 | #define R2057_TSSI2G_SPARE1_CORE1 0x0e5 |
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| 226 | #define R2057_TSSI2G_SPARE2_CORE1 0x0e6 |
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| 227 | #define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7 |
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| 228 | #define R2057_IPA2G_IMAIN_CORE1 0x0e8 |
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| 229 | #define R2057_IPA2G_CASCONV_CORE1 0x0e9 |
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| 230 | #define R2057_IPA2G_CASCOFFV_CORE1 0x0ea |
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| 231 | #define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb |
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| 232 | #define R2057_TX5G_PKDET_CORE1 0x0ee |
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| 233 | #define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef |
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| 234 | #define R2057_PAD5G_PTATS1_CORE1 0x0f0 |
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| 235 | #define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1 |
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| 236 | #define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2 |
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| 237 | #define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3 |
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| 238 | #define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4 |
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| 239 | #define R2057_PGA_BOOST_TUNE_CORE1 0x0f5 |
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| 240 | #define R2057_PGA_GAIN_CORE1 0x0f6 |
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| 241 | #define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7 |
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| 242 | #define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8 |
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| 243 | #define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9 |
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| 244 | #define R2057_IPA5G_IAUX_CORE1 0x0fa |
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| 245 | #define R2057_IPA5G_GAIN_CORE1 0x0fb |
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| 246 | #define R2057_TSSI5G_SPARE1_CORE1 0x0fc |
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| 247 | #define R2057_TSSI5G_SPARE2_CORE1 0x0fd |
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| 248 | #define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe |
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| 249 | #define R2057_IPA5G_PTAT_CORE1 0x0ff |
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| 250 | #define R2057_IPA5G_IMAIN_CORE1 0x100 |
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| 251 | #define R2057_IPA5G_CASCONV_CORE1 0x101 |
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| 252 | #define R2057_IPA5G_BIAS_FILTER_CORE1 0x102 |
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| 253 | #define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105 |
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| 254 | #define R2057_TR2G_CONFIG1_CORE1_NU 0x106 |
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| 255 | #define R2057_TR2G_CONFIG2_CORE1_NU 0x107 |
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| 256 | #define R2057_LNA5G_RFEN_CORE1 0x108 |
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| 257 | #define R2057_TR5G_CONFIG2_CORE1_NU 0x109 |
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| 258 | #define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a |
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| 259 | #define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b |
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| 260 | #define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c |
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| 261 | #define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d |
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| 262 | #define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e |
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| 263 | #define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f |
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| 264 | #define R2057_LNA2_IAUX_PTAT_CORE1 0x110 |
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| 265 | #define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111 |
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| 266 | #define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112 |
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| 267 | #define R2057_RXRFBIAS_BANDSEL_CORE1 0x113 |
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| 268 | #define R2057_TIA_CONFIG_CORE1 0x114 |
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| 269 | #define R2057_TIA_IQGAIN_CORE1 0x115 |
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| 270 | #define R2057_TIA_IBIAS2_CORE1 0x116 |
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| 271 | #define R2057_TIA_IBIAS1_CORE1 0x117 |
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| 272 | #define R2057_TIA_SPARE_Q_CORE1 0x118 |
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| 273 | #define R2057_TIA_SPARE_I_CORE1 0x119 |
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| 274 | #define R2057_RXMIX2G_PUS_CORE1 0x11a |
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| 275 | #define R2057_RXMIX2G_VCMREFS_CORE1 0x11b |
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| 276 | #define R2057_RXMIX2G_LODC_QI_CORE1 0x11c |
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| 277 | #define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d |
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| 278 | #define R2057_LNA2G_GAIN_CORE1 0x11e |
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| 279 | #define R2057_LNA2G_TUNE_CORE1 0x11f |
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| 280 | #define R2057_RXMIX5G_PUS_CORE1 0x120 |
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| 281 | #define R2057_RXMIX5G_VCMREFS_CORE1 0x121 |
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| 282 | #define R2057_RXMIX5G_LODC_QI_CORE1 0x122 |
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| 283 | #define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123 |
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| 284 | #define R2057_LNA5G_GAIN_CORE1 0x124 |
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| 285 | #define R2057_LNA5G_TUNE_CORE1 0x125 |
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| 286 | #define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126 |
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| 287 | #define R2057_RXBB_BIAS_MASTER_CORE1 0x127 |
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| 288 | #define R2057_RXBB_VGABUF_IDACS_CORE1 0x128 |
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| 289 | #define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129 |
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| 290 | #define R2057_TXBUF_VINCM_CORE1 0x12a |
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| 291 | #define R2057_TXBUF_IDACS_CORE1 0x12b |
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| 292 | #define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c |
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| 293 | #define R2057_RXBB_CC_CORE1 0x12d |
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| 294 | #define R2057_RXBB_SPARE3_CORE1 0x12e |
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| 295 | #define R2057_RXBB_RCCAL_HPC_CORE1 0x12f |
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| 296 | #define R2057_LPF_IDACS_CORE1 0x130 |
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| 297 | #define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131 |
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| 298 | #define R2057_TXBUF_GAIN_CORE1 0x132 |
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| 299 | #define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133 |
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| 300 | #define R2057_RXBUF_DEGEN_CORE1 0x134 |
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| 301 | #define R2057_RXBB_SPARE2_CORE1 0x135 |
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| 302 | #define R2057_RXBB_SPARE1_CORE1 0x136 |
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| 303 | #define 0x137 |
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| 304 | #define R2057_W2_MASTER_CORE1 0x138 |
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| 305 | #define R2057_NB_MASTER_CORE1 0x139 |
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| 306 | #define R2057_W2_IDACS0_Q_CORE1 0x13a |
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| 307 | #define R2057_W2_IDACS1_Q_CORE1 0x13b |
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| 308 | #define R2057_W2_IDACS0_I_CORE1 0x13c |
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| 309 | #define R2057_W2_IDACS1_I_CORE1 0x13d |
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| 310 | #define 0x13e |
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| 311 | #define R2057_NB_IDACS_Q_CORE1 0x13f |
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| 312 | #define R2057_NB_IDACS_I_CORE1 0x140 |
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| 313 | #define R2057_BACKUP4_CORE1 0x146 |
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| 314 | #define R2057_BACKUP3_CORE1 0x147 |
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| 315 | #define R2057_BACKUP2_CORE1 0x148 |
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| 316 | #define R2057_BACKUP1_CORE1 0x149 |
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| 317 | #define R2057_SPARE16_CORE1 0x14a |
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| 318 | #define R2057_SPARE15_CORE1 0x14b |
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| 319 | #define R2057_SPARE14_CORE1 0x14c |
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| 320 | #define R2057_SPARE13_CORE1 0x14d |
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| 321 | #define R2057_SPARE12_CORE1 0x14e |
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| 322 | #define R2057_SPARE11_CORE1 0x14f |
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| 323 | #define R2057_TX2G_BIAS_RESETS_CORE1 0x150 |
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| 324 | #define R2057_TX5G_BIAS_RESETS_CORE1 0x151 |
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| 325 | #define R2057_SPARE8_CORE1 0x152 |
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| 326 | #define R2057_SPARE7_CORE1 0x153 |
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| 327 | #define R2057_BUFS_MISC_LPFBW_CORE1 0x154 |
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| 328 | #define R2057_TXLPF_RCCAL_CORE1 0x155 |
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| 329 | #define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 |
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| 330 | #define R2057_LPF_GAIN_CORE1 0x157 |
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| 331 | #define R2057_DACBUF_IDACS_BW_CORE1 0x158 |
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| 332 | |
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| 333 | #define R2057_DACBUF_VINCM_CORE1 0x159 |
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| 334 | #define R2057_RCCAL_START_R1_Q1_P1 0x15a |
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| 335 | #define R2057_RCCAL_X1 0x15b |
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| 336 | #define R2057_RCCAL_TRC0 0x15c |
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| 337 | #define R2057_RCCAL_TRC1 0x15d |
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| 338 | #define R2057_RCCAL_DONE_OSCCAP 0x15e |
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| 339 | #define R2057_RCCAL_N0_0 0x15f |
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| 340 | #define R2057_RCCAL_N0_1 0x160 |
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| 341 | #define R2057_RCCAL_N1_0 0x161 |
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| 342 | #define R2057_RCCAL_N1_1 0x162 |
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| 343 | #define R2057_RCAL_STATUS 0x163 |
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| 344 | #define R2057_XTALPUOVR_PINCTRL 0x164 |
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| 345 | #define R2057_OVR_REG0 0x165 |
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| 346 | #define R2057_OVR_REG1 0x166 |
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| 347 | #define R2057_OVR_REG2 0x167 |
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| 348 | #define R2057_OVR_REG3 0x168 |
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| 349 | #define R2057_OVR_REG4 0x169 |
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| 350 | #define R2057_RCCAL_SCAP_VAL 0x16a |
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| 351 | #define R2057_RCCAL_BCAP_VAL 0x16b |
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| 352 | #define R2057_RCCAL_HPC_VAL 0x16c |
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| 353 | #define R2057_RCCAL_OVERRIDES 0x16d |
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| 354 | |
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| 355 | /* TX core 0 */ |
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| 356 | #define R2057_TX0_IQCAL_GAIN_BW 0x170 |
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| 357 | #define R2057_TX0_LOFT_FINE_I 0x171 |
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| 358 | #define R2057_TX0_LOFT_FINE_Q 0x172 |
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| 359 | #define R2057_TX0_LOFT_COARSE_I 0x173 |
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| 360 | #define R2057_TX0_LOFT_COARSE_Q 0x174 |
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| 361 | #define R2057_TX0_TX_SSI_MASTER 0x175 |
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| 362 | #define R2057_TX0_IQCAL_VCM_HG 0x176 |
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| 363 | #define R2057_TX0_IQCAL_IDAC 0x177 |
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| 364 | #define R2057_TX0_TSSI_VCM 0x178 |
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| 365 | #define R2057_TX0_TX_SSI_MUX 0x179 |
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| 366 | #define R2057_TX0_TSSIA 0x17a |
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| 367 | #define R2057_TX0_TSSIG 0x17b |
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| 368 | #define R2057_TX0_TSSI_MISC1 0x17c |
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| 369 | #define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d |
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| 370 | #define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e |
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| 371 | #define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f |
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| 372 | #define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 |
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| 373 | |
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| 374 | /* TX core 1 */ |
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| 375 | #define R2057_TX1_IQCAL_GAIN_BW 0x190 |
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| 376 | #define R2057_TX1_LOFT_FINE_I 0x191 |
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| 377 | #define R2057_TX1_LOFT_FINE_Q 0x192 |
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| 378 | #define R2057_TX1_LOFT_COARSE_I 0x193 |
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| 379 | #define R2057_TX1_LOFT_COARSE_Q 0x194 |
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| 380 | #define R2057_TX1_TX_SSI_MASTER 0x195 |
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| 381 | #define R2057_TX1_IQCAL_VCM_HG 0x196 |
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| 382 | #define R2057_TX1_IQCAL_IDAC 0x197 |
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| 383 | #define R2057_TX1_TSSI_VCM 0x198 |
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| 384 | #define R2057_TX1_TX_SSI_MUX 0x199 |
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| 385 | #define R2057_TX1_TSSIA 0x19a |
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| 386 | #define R2057_TX1_TSSIG 0x19b |
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| 387 | #define R2057_TX1_TSSI_MISC1 0x19c |
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| 388 | #define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d |
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| 389 | #define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e |
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| 390 | #define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f |
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| 391 | #define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 |
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| 392 | |
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| 393 | #define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 |
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| 394 | #define R2057_AFE_SET_VCM_I_CORE0 0x1a2 |
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| 395 | #define R2057_AFE_SET_VCM_Q_CORE0 0x1a3 |
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| 396 | #define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4 |
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| 397 | #define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5 |
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| 398 | #define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6 |
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| 399 | #define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7 |
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| 400 | #define R2057_AFE_SET_VCM_I_CORE1 0x1a8 |
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| 401 | #define R2057_AFE_SET_VCM_Q_CORE1 0x1a9 |
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| 402 | #define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa |
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| 403 | #define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab |
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| 404 | #define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac |
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| 405 | |
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| 406 | #define R2057v7_DACBUF_VINCM_CORE0 0x1ad |
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| 407 | #define R2057v7_RCCAL_MASTER 0x1ae |
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| 408 | #define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af |
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| 409 | #define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0 |
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| 410 | #define R2057v7_LOGEN_PUS1 0x1b1 |
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| 411 | #define R2057v7_OVR_REG5 0x1b2 |
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| 412 | #define R2057v7_OVR_REG6 0x1b3 |
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| 413 | #define R2057v7_OVR_REG7 0x1b4 |
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| 414 | #define R2057v7_OVR_REG8 0x1b5 |
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| 415 | #define R2057v7_OVR_REG9 0x1b6 |
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| 416 | #define R2057v7_OVR_REG10 0x1b7 |
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| 417 | #define R2057v7_OVR_REG11 0x1b8 |
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| 418 | #define R2057v7_OVR_REG12 0x1b9 |
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| 419 | #define R2057v7_OVR_REG13 0x1ba |
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| 420 | #define R2057v7_OVR_REG14 0x1bb |
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| 421 | #define R2057v7_OVR_REG15 0x1bc |
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| 422 | #define R2057v7_OVR_REG16 0x1bd |
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| 423 | #define R2057v7_OVR_REG1 0x1be |
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| 424 | #define R2057v7_OVR_REG18 0x1bf |
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| 425 | #define R2057v7_OVR_REG19 0x1c0 |
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| 426 | #define R2057v7_OVR_REG20 0x1c1 |
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| 427 | #define R2057v7_OVR_REG21 0x1c2 |
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| 428 | #define R2057v7_OVR_REG2 0x1c3 |
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| 429 | #define R2057v7_OVR_REG23 0x1c4 |
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| 430 | #define R2057v7_OVR_REG24 0x1c5 |
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| 431 | #define R2057v7_OVR_REG25 0x1c6 |
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| 432 | #define R2057v7_OVR_REG26 0x1c7 |
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| 433 | #define R2057v7_OVR_REG27 0x1c8 |
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| 434 | #define R2057v7_OVR_REG28 0x1c9 |
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| 435 | #define R2057v7_IQTEST_SEL_PU2 0x1ca |
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| 436 | |
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| 437 | #define R2057_VCM_MASK 0x7 |
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| 438 | |
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| 439 | struct b43_nphy_chantabent_rev7 { |
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| 440 | /* The channel frequency in MHz */ |
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| 441 | u16 freq; |
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| 442 | /* Radio regs values on channelswitch */ |
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| 443 | u8 radio_vcocal_countval0; |
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| 444 | u8 radio_vcocal_countval1; |
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| 445 | u8 radio_rfpll_refmaster_sparextalsize; |
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| 446 | u8 radio_rfpll_loopfilter_r1; |
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| 447 | u8 radio_rfpll_loopfilter_c2; |
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| 448 | u8 radio_rfpll_loopfilter_c1; |
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| 449 | u8 radio_cp_kpd_idac; |
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| 450 | u8 radio_rfpll_mmd0; |
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| 451 | u8 radio_rfpll_mmd1; |
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| 452 | u8 radio_vcobuf_tune; |
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| 453 | u8 radio_logen_mx2g_tune; |
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| 454 | u8 radio_logen_mx5g_tune; |
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| 455 | u8 radio_logen_indbuf2g_tune; |
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| 456 | u8 radio_logen_indbuf5g_tune; |
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| 457 | u8 radio_txmix2g_tune_boost_pu_core0; |
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| 458 | u8 radio_pad2g_tune_pus_core0; |
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| 459 | u8 radio_pga_boost_tune_core0; |
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| 460 | u8 radio_txmix5g_boost_tune_core0; |
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| 461 | u8 radio_pad5g_tune_misc_pus_core0; |
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| 462 | u8 radio_lna2g_tune_core0; |
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| 463 | u8 radio_lna5g_tune_core0; |
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| 464 | u8 radio_txmix2g_tune_boost_pu_core1; |
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| 465 | u8 radio_pad2g_tune_pus_core1; |
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| 466 | u8 radio_pga_boost_tune_core1; |
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| 467 | u8 radio_txmix5g_boost_tune_core1; |
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| 468 | u8 radio_pad5g_tune_misc_pus_core1; |
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| 469 | u8 radio_lna2g_tune_core1; |
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| 470 | u8 radio_lna5g_tune_core1; |
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| 471 | /* PHY res values on channelswitch */ |
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| 472 | struct b43_phy_n_sfo_cfg phy_regs; |
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| 473 | }; |
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| 474 | |
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| 475 | struct b43_nphy_chantabent_rev7_2g { |
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| 476 | /* The channel frequency in MHz */ |
|---|
| 477 | u16 freq; |
|---|
| 478 | /* Radio regs values on channelswitch */ |
|---|
| 479 | u8 radio_vcocal_countval0; |
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| 480 | u8 radio_vcocal_countval1; |
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| 481 | u8 radio_rfpll_refmaster_sparextalsize; |
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| 482 | u8 radio_rfpll_loopfilter_r1; |
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| 483 | u8 radio_rfpll_loopfilter_c2; |
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| 484 | u8 radio_rfpll_loopfilter_c1; |
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| 485 | u8 radio_cp_kpd_idac; |
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| 486 | u8 radio_rfpll_mmd0; |
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| 487 | u8 radio_rfpll_mmd1; |
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| 488 | u8 radio_vcobuf_tune; |
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| 489 | u8 radio_logen_mx2g_tune; |
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| 490 | u8 radio_logen_indbuf2g_tune; |
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| 491 | u8 radio_txmix2g_tune_boost_pu_core0; |
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| 492 | u8 radio_pad2g_tune_pus_core0; |
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| 493 | u8 radio_lna2g_tune_core0; |
|---|
| 494 | u8 radio_txmix2g_tune_boost_pu_core1; |
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| 495 | u8 radio_pad2g_tune_pus_core1; |
|---|
| 496 | u8 radio_lna2g_tune_core1; |
|---|
| 497 | /* PHY regs values on channelswitch */ |
|---|
| 498 | struct b43_phy_n_sfo_cfg phy_regs; |
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| 499 | }; |
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| 500 | |
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| 501 | void r2057_upload_inittabs(struct b43_wldev *dev); |
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| 502 | |
|---|
| 503 | void r2057_get_chantabent_rev7(struct b43_wldev *dev, u16 freq, |
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| 504 | const struct b43_nphy_chantabent_rev7 **tabent_r7, |
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| 505 | const struct b43_nphy_chantabent_rev7_2g **tabent_r7_2g); |
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| 506 | |
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| 507 | #endif /* B43_RADIO_2057_H_ */ |
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| 508 | |
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