| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2014 Intel Mobile Communications GmbH |
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| 4 | */ |
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| 5 | #ifndef __iwl_scd_h__ |
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| 6 | #define __iwl_scd_h__ |
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| 7 | |
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| 8 | #include "iwl-trans.h" |
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| 9 | #include "iwl-io.h" |
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| 10 | #include "iwl-prph.h" |
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| 11 | |
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| 12 | |
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| 13 | static inline void iwl_scd_txq_set_chain(struct iwl_trans *trans, |
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| 14 | u16 txq_id) |
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| 15 | { |
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| 16 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); |
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| 17 | } |
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| 18 | |
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| 19 | static inline void iwl_scd_txq_enable_agg(struct iwl_trans *trans, |
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| 20 | u16 txq_id) |
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| 21 | { |
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| 22 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
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| 23 | } |
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| 24 | |
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| 25 | static inline void iwl_scd_txq_disable_agg(struct iwl_trans *trans, |
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| 26 | u16 txq_id) |
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| 27 | { |
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| 28 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
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| 29 | } |
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| 30 | |
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| 31 | static inline void iwl_scd_disable_agg(struct iwl_trans *trans) |
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| 32 | { |
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| 33 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, mask: 0); |
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| 34 | } |
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| 35 | |
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| 36 | static inline void iwl_scd_activate_fifos(struct iwl_trans *trans) |
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| 37 | { |
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| 38 | iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7)); |
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| 39 | } |
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| 40 | |
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| 41 | static inline void iwl_scd_deactivate_fifos(struct iwl_trans *trans) |
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| 42 | { |
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| 43 | iwl_write_prph(trans, SCD_TXFACT, val: 0); |
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| 44 | } |
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| 45 | |
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| 46 | static inline void iwl_scd_enable_set_active(struct iwl_trans *trans, |
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| 47 | u32 value) |
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| 48 | { |
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| 49 | iwl_write_prph(trans, SCD_EN_CTRL, val: value); |
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| 50 | } |
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| 51 | |
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| 52 | static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl) |
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| 53 | { |
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| 54 | if (chnl < 20) |
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| 55 | return SCD_BASE + 0x18 + chnl * 4; |
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| 56 | WARN_ON_ONCE(chnl >= 32); |
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| 57 | return SCD_BASE + 0x284 + (chnl - 20) * 4; |
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| 58 | } |
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| 59 | |
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| 60 | static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl) |
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| 61 | { |
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| 62 | if (chnl < 20) |
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| 63 | return SCD_BASE + 0x68 + chnl * 4; |
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| 64 | WARN_ON_ONCE(chnl >= 32); |
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| 65 | return SCD_BASE + 0x2B4 + chnl * 4; |
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| 66 | } |
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| 67 | |
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| 68 | static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl) |
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| 69 | { |
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| 70 | if (chnl < 20) |
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| 71 | return SCD_BASE + 0x10c + chnl * 4; |
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| 72 | WARN_ON_ONCE(chnl >= 32); |
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| 73 | return SCD_BASE + 0x334 + chnl * 4; |
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| 74 | } |
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| 75 | |
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| 76 | static inline void iwl_scd_txq_set_inactive(struct iwl_trans *trans, |
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| 77 | u16 txq_id) |
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| 78 | { |
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| 79 | iwl_write_prph(trans, ofs: SCD_QUEUE_STATUS_BITS(chnl: txq_id), |
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| 80 | val: (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| |
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| 81 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); |
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| 82 | } |
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| 83 | |
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| 84 | #endif |
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| 85 | |
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