1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2019-2020 Realtek Corporation |
3 | */ |
4 | |
5 | #ifndef __RTW89_MAC_H__ |
6 | #define __RTW89_MAC_H__ |
7 | |
8 | #include "core.h" |
9 | #include "reg.h" |
10 | |
11 | #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 |
12 | #define ADDR_CAM_ENT_SIZE 0x40 |
13 | #define ADDR_CAM_ENT_SHORT_SIZE 0x20 |
14 | #define BSSID_CAM_ENT_SIZE 0x08 |
15 | #define HFC_PAGE_UNIT 64 |
16 | #define RPWM_TRY_CNT 3 |
17 | |
18 | enum rtw89_mac_hwmod_sel { |
19 | RTW89_DMAC_SEL = 0, |
20 | RTW89_CMAC_SEL = 1, |
21 | |
22 | RTW89_MAC_INVALID, |
23 | }; |
24 | |
25 | enum rtw89_mac_fwd_target { |
26 | RTW89_FWD_DONT_CARE = 0, |
27 | RTW89_FWD_TO_HOST = 1, |
28 | RTW89_FWD_TO_WLAN_CPU = 2 |
29 | }; |
30 | |
31 | enum rtw89_mac_wd_dma_intvl { |
32 | RTW89_MAC_WD_DMA_INTVL_0S, |
33 | RTW89_MAC_WD_DMA_INTVL_256NS, |
34 | RTW89_MAC_WD_DMA_INTVL_512NS, |
35 | RTW89_MAC_WD_DMA_INTVL_768NS, |
36 | RTW89_MAC_WD_DMA_INTVL_1US, |
37 | RTW89_MAC_WD_DMA_INTVL_1_5US, |
38 | RTW89_MAC_WD_DMA_INTVL_2US, |
39 | RTW89_MAC_WD_DMA_INTVL_4US, |
40 | RTW89_MAC_WD_DMA_INTVL_8US, |
41 | RTW89_MAC_WD_DMA_INTVL_16US, |
42 | RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE |
43 | }; |
44 | |
45 | enum rtw89_mac_multi_tag_num { |
46 | RTW89_MAC_TAG_NUM_1, |
47 | RTW89_MAC_TAG_NUM_2, |
48 | RTW89_MAC_TAG_NUM_3, |
49 | RTW89_MAC_TAG_NUM_4, |
50 | RTW89_MAC_TAG_NUM_5, |
51 | RTW89_MAC_TAG_NUM_6, |
52 | RTW89_MAC_TAG_NUM_7, |
53 | RTW89_MAC_TAG_NUM_8, |
54 | RTW89_MAC_TAG_NUM_DEF = 0xFE |
55 | }; |
56 | |
57 | enum rtw89_mac_lbc_tmr { |
58 | RTW89_MAC_LBC_TMR_8US = 0, |
59 | RTW89_MAC_LBC_TMR_16US, |
60 | RTW89_MAC_LBC_TMR_32US, |
61 | RTW89_MAC_LBC_TMR_64US, |
62 | RTW89_MAC_LBC_TMR_128US, |
63 | RTW89_MAC_LBC_TMR_256US, |
64 | RTW89_MAC_LBC_TMR_512US, |
65 | RTW89_MAC_LBC_TMR_1MS, |
66 | RTW89_MAC_LBC_TMR_2MS, |
67 | RTW89_MAC_LBC_TMR_4MS, |
68 | RTW89_MAC_LBC_TMR_8MS, |
69 | RTW89_MAC_LBC_TMR_DEF = 0xFE |
70 | }; |
71 | |
72 | enum rtw89_mac_cpuio_op_cmd_type { |
73 | CPUIO_OP_CMD_GET_1ST_PID = 0, |
74 | CPUIO_OP_CMD_GET_NEXT_PID = 1, |
75 | CPUIO_OP_CMD_ENQ_TO_TAIL = 4, |
76 | CPUIO_OP_CMD_ENQ_TO_HEAD = 5, |
77 | CPUIO_OP_CMD_DEQ = 8, |
78 | CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, |
79 | CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 |
80 | }; |
81 | |
82 | enum rtw89_mac_wde_dle_port_id { |
83 | WDE_DLE_PORT_ID_DISPATCH = 0, |
84 | WDE_DLE_PORT_ID_PKTIN = 1, |
85 | WDE_DLE_PORT_ID_CMAC0 = 3, |
86 | WDE_DLE_PORT_ID_CMAC1 = 4, |
87 | WDE_DLE_PORT_ID_CPU_IO = 6, |
88 | WDE_DLE_PORT_ID_WDRLS = 7, |
89 | WDE_DLE_PORT_ID_END = 8 |
90 | }; |
91 | |
92 | enum rtw89_mac_wde_dle_queid_wdrls { |
93 | WDE_DLE_QUEID_TXOK = 0, |
94 | WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, |
95 | WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, |
96 | WDE_DLE_QUEID_DROP_MACID_DROP = 3, |
97 | WDE_DLE_QUEID_NO_REPORT = 4 |
98 | }; |
99 | |
100 | enum rtw89_mac_ple_dle_port_id { |
101 | PLE_DLE_PORT_ID_DISPATCH = 0, |
102 | PLE_DLE_PORT_ID_MPDU = 1, |
103 | PLE_DLE_PORT_ID_SEC = 2, |
104 | PLE_DLE_PORT_ID_CMAC0 = 3, |
105 | PLE_DLE_PORT_ID_CMAC1 = 4, |
106 | PLE_DLE_PORT_ID_WDRLS = 5, |
107 | PLE_DLE_PORT_ID_CPU_IO = 6, |
108 | PLE_DLE_PORT_ID_PLRLS = 7, |
109 | PLE_DLE_PORT_ID_END = 8 |
110 | }; |
111 | |
112 | enum rtw89_mac_ple_dle_queid_plrls { |
113 | PLE_DLE_QUEID_NO_REPORT = 0x0 |
114 | }; |
115 | |
116 | enum rtw89_machdr_frame_type { |
117 | RTW89_MGNT = 0, |
118 | RTW89_CTRL = 1, |
119 | RTW89_DATA = 2, |
120 | }; |
121 | |
122 | enum rtw89_mac_dle_dfi_type { |
123 | DLE_DFI_TYPE_FREEPG = 0, |
124 | DLE_DFI_TYPE_QUOTA = 1, |
125 | DLE_DFI_TYPE_PAGELLT = 2, |
126 | DLE_DFI_TYPE_PKTINFO = 3, |
127 | DLE_DFI_TYPE_PREPKTLLT = 4, |
128 | DLE_DFI_TYPE_NXTPKTLLT = 5, |
129 | DLE_DFI_TYPE_QLNKTBL = 6, |
130 | DLE_DFI_TYPE_QEMPTY = 7, |
131 | }; |
132 | |
133 | enum rtw89_mac_dle_wde_quota_id { |
134 | WDE_QTAID_HOST_IF = 0, |
135 | WDE_QTAID_WLAN_CPU = 1, |
136 | WDE_QTAID_DATA_CPU = 2, |
137 | WDE_QTAID_PKTIN = 3, |
138 | WDE_QTAID_CPUIO = 4, |
139 | }; |
140 | |
141 | enum rtw89_mac_dle_ple_quota_id { |
142 | PLE_QTAID_B0_TXPL = 0, |
143 | PLE_QTAID_B1_TXPL = 1, |
144 | PLE_QTAID_C2H = 2, |
145 | PLE_QTAID_H2C = 3, |
146 | PLE_QTAID_WLAN_CPU = 4, |
147 | PLE_QTAID_MPDU = 5, |
148 | PLE_QTAID_CMAC0_RX = 6, |
149 | PLE_QTAID_CMAC1_RX = 7, |
150 | PLE_QTAID_CMAC1_BBRPT = 8, |
151 | PLE_QTAID_WDRLS = 9, |
152 | PLE_QTAID_CPUIO = 10, |
153 | }; |
154 | |
155 | enum rtw89_mac_dle_ctrl_type { |
156 | DLE_CTRL_TYPE_WDE = 0, |
157 | DLE_CTRL_TYPE_PLE = 1, |
158 | DLE_CTRL_TYPE_NUM = 2, |
159 | }; |
160 | |
161 | enum rtw89_mac_ax_l0_to_l1_event { |
162 | MAC_AX_L0_TO_L1_CHIF_IDLE = 0, |
163 | MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, |
164 | MAC_AX_L0_TO_L1_RLS_PKID = 2, |
165 | MAC_AX_L0_TO_L1_PTCL_IDLE = 3, |
166 | MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, |
167 | MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, |
168 | MAC_AX_L0_TO_L1_PCIE_STUCK = 6, |
169 | MAC_AX_L0_TO_L1_EVENT_MAX = 15, |
170 | }; |
171 | |
172 | enum rtw89_mac_wow_fw_status { |
173 | WOWLAN_NOT_READY = 0x00, |
174 | WOWLAN_SLEEP_READY = 0x01, |
175 | WOWLAN_RESUME_READY = 0x02, |
176 | }; |
177 | |
178 | #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) |
179 | |
180 | enum rtw89_mac_dbg_port_sel { |
181 | /* CMAC 0 related */ |
182 | RTW89_DBG_PORT_SEL_PTCL_C0 = 0, |
183 | RTW89_DBG_PORT_SEL_SCH_C0, |
184 | RTW89_DBG_PORT_SEL_TMAC_C0, |
185 | RTW89_DBG_PORT_SEL_RMAC_C0, |
186 | RTW89_DBG_PORT_SEL_RMACST_C0, |
187 | RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, |
188 | RTW89_DBG_PORT_SEL_TRXPTCL_C0, |
189 | RTW89_DBG_PORT_SEL_TX_INFOL_C0, |
190 | RTW89_DBG_PORT_SEL_TX_INFOH_C0, |
191 | RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, |
192 | RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, |
193 | /* CMAC 1 related */ |
194 | RTW89_DBG_PORT_SEL_PTCL_C1, |
195 | RTW89_DBG_PORT_SEL_SCH_C1, |
196 | RTW89_DBG_PORT_SEL_TMAC_C1, |
197 | RTW89_DBG_PORT_SEL_RMAC_C1, |
198 | RTW89_DBG_PORT_SEL_RMACST_C1, |
199 | RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, |
200 | RTW89_DBG_PORT_SEL_TRXPTCL_C1, |
201 | RTW89_DBG_PORT_SEL_TX_INFOL_C1, |
202 | RTW89_DBG_PORT_SEL_TX_INFOH_C1, |
203 | RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, |
204 | RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, |
205 | /* DLE related */ |
206 | RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, |
207 | RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, |
208 | RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, |
209 | RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, |
210 | RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, |
211 | RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, |
212 | RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, |
213 | RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, |
214 | RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, |
215 | RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, |
216 | RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, |
217 | RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, |
218 | RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, |
219 | RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, |
220 | RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, |
221 | RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, |
222 | RTW89_DBG_PORT_SEL_PKTINFO, |
223 | /* DISPATCHER related */ |
224 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, |
225 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, |
226 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, |
227 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, |
228 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, |
229 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, |
230 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, |
231 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, |
232 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, |
233 | RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, |
234 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, |
235 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, |
236 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, |
237 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, |
238 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, |
239 | RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, |
240 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, |
241 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, |
242 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, |
243 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, |
244 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, |
245 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, |
246 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, |
247 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, |
248 | RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, |
249 | RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, |
250 | RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, |
251 | RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, |
252 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, |
253 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, |
254 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, |
255 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, |
256 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, |
257 | RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, |
258 | RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, |
259 | RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, |
260 | RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, |
261 | RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, |
262 | RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, |
263 | RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, |
264 | RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, |
265 | RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, |
266 | RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, |
267 | RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, |
268 | /* PCIE related */ |
269 | RTW89_DBG_PORT_SEL_PCIE_TXDMA, |
270 | RTW89_DBG_PORT_SEL_PCIE_RXDMA, |
271 | RTW89_DBG_PORT_SEL_PCIE_CVT, |
272 | RTW89_DBG_PORT_SEL_PCIE_CXPL, |
273 | RTW89_DBG_PORT_SEL_PCIE_IO, |
274 | RTW89_DBG_PORT_SEL_PCIE_MISC, |
275 | RTW89_DBG_PORT_SEL_PCIE_MISC2, |
276 | |
277 | /* keep last */ |
278 | RTW89_DBG_PORT_SEL_LAST, |
279 | RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, |
280 | RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, |
281 | }; |
282 | |
283 | /* SRAM mem dump */ |
284 | #define R_AX_INDIR_ACCESS_ENTRY 0x40000 |
285 | #define R_BE_INDIR_ACCESS_ENTRY 0x80000 |
286 | |
287 | #define AXIDMA_BASE_ADDR 0x18006000 |
288 | #define STA_SCHED_BASE_ADDR 0x18808000 |
289 | #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 |
290 | #define SECURITY_CAM_BASE_ADDR 0x18814000 |
291 | #define WOW_CAM_BASE_ADDR 0x18815000 |
292 | #define CMAC_TBL_BASE_ADDR 0x18840000 |
293 | #define ADDR_CAM_BASE_ADDR 0x18850000 |
294 | #define BSSID_CAM_BASE_ADDR 0x18853000 |
295 | #define BA_CAM_BASE_ADDR 0x18854000 |
296 | #define BCN_IE_CAM0_BASE_ADDR 0x18855000 |
297 | #define SHARED_BUF_BASE_ADDR 0x18700000 |
298 | #define DMAC_TBL_BASE_ADDR 0x18800000 |
299 | #define SHCUT_MACHDR_BASE_ADDR 0x18800800 |
300 | #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 |
301 | #define TXD_FIFO_0_BASE_ADDR 0x18856200 |
302 | #define TXD_FIFO_1_BASE_ADDR 0x188A1080 |
303 | #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ |
304 | #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ |
305 | #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 |
306 | #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 |
307 | #define CPU_LOCAL_BASE_ADDR 0x18003000 |
308 | |
309 | #define WD_PAGE_BASE_ADDR_BE 0x0 |
310 | #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 |
311 | #define AXIDMA_BASE_ADDR_BE 0x18006000 |
312 | #define SHARED_BUF_BASE_ADDR_BE 0x18700000 |
313 | #define DMAC_TBL_BASE_ADDR_BE 0x18800000 |
314 | #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 |
315 | #define STA_SCHED_BASE_ADDR_BE 0x18818000 |
316 | #define NAT25_CAM_BASE_ADDR_BE 0x18820000 |
317 | #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 |
318 | #define SEC_CAM_BASE_ADDR_BE 0x18824000 |
319 | #define WOW_CAM_BASE_ADDR_BE 0x18828000 |
320 | #define MLD_TBL_BASE_ADDR_BE 0x18829000 |
321 | #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 |
322 | #define CMAC_TBL_BASE_ADDR_BE 0x18840000 |
323 | #define ADDR_CAM_BASE_ADDR_BE 0x18850000 |
324 | #define BSSID_CAM_BASE_ADDR_BE 0x18858000 |
325 | #define BA_CAM_BASE_ADDR_BE 0x18859000 |
326 | #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 |
327 | #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 |
328 | #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 |
329 | #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 |
330 | #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 |
331 | #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 |
332 | #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 |
333 | |
334 | #define CCTL_INFO_SIZE 32 |
335 | |
336 | enum rtw89_mac_mem_sel { |
337 | RTW89_MAC_MEM_AXIDMA, |
338 | RTW89_MAC_MEM_SHARED_BUF, |
339 | RTW89_MAC_MEM_DMAC_TBL, |
340 | RTW89_MAC_MEM_SHCUT_MACHDR, |
341 | RTW89_MAC_MEM_STA_SCHED, |
342 | RTW89_MAC_MEM_RXPLD_FLTR_CAM, |
343 | RTW89_MAC_MEM_SECURITY_CAM, |
344 | RTW89_MAC_MEM_WOW_CAM, |
345 | RTW89_MAC_MEM_CMAC_TBL, |
346 | RTW89_MAC_MEM_ADDR_CAM, |
347 | RTW89_MAC_MEM_BA_CAM, |
348 | RTW89_MAC_MEM_BCN_IE_CAM0, |
349 | RTW89_MAC_MEM_BCN_IE_CAM1, |
350 | RTW89_MAC_MEM_TXD_FIFO_0, |
351 | RTW89_MAC_MEM_TXD_FIFO_1, |
352 | RTW89_MAC_MEM_TXDATA_FIFO_0, |
353 | RTW89_MAC_MEM_TXDATA_FIFO_1, |
354 | RTW89_MAC_MEM_CPU_LOCAL, |
355 | RTW89_MAC_MEM_BSSID_CAM, |
356 | RTW89_MAC_MEM_TXD_FIFO_0_V1, |
357 | RTW89_MAC_MEM_TXD_FIFO_1_V1, |
358 | RTW89_MAC_MEM_WD_PAGE, |
359 | |
360 | /* keep last */ |
361 | RTW89_MAC_MEM_NUM, |
362 | }; |
363 | |
364 | enum rtw89_rpwm_req_pwr_state { |
365 | RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, |
366 | RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, |
367 | RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, |
368 | RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, |
369 | RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, |
370 | RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, |
371 | RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, |
372 | RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, |
373 | RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, |
374 | }; |
375 | |
376 | struct rtw89_pwr_cfg { |
377 | u16 addr; |
378 | u8 cv_msk; |
379 | u8 intf_msk; |
380 | u8 base:4; |
381 | u8 cmd:4; |
382 | u8 msk; |
383 | u8 val; |
384 | }; |
385 | |
386 | enum rtw89_mac_c2h_ofld_func { |
387 | RTW89_MAC_C2H_FUNC_EFUSE_DUMP, |
388 | RTW89_MAC_C2H_FUNC_READ_RSP, |
389 | RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, |
390 | RTW89_MAC_C2H_FUNC_BCN_RESEND, |
391 | RTW89_MAC_C2H_FUNC_MACID_PAUSE, |
392 | RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, |
393 | RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, |
394 | RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, |
395 | RTW89_MAC_C2H_FUNC_OFLD_MAX, |
396 | }; |
397 | |
398 | enum rtw89_mac_c2h_info_func { |
399 | RTW89_MAC_C2H_FUNC_REC_ACK, |
400 | RTW89_MAC_C2H_FUNC_DONE_ACK, |
401 | RTW89_MAC_C2H_FUNC_C2H_LOG, |
402 | RTW89_MAC_C2H_FUNC_BCN_CNT, |
403 | RTW89_MAC_C2H_FUNC_INFO_MAX, |
404 | }; |
405 | |
406 | enum rtw89_mac_c2h_mcc_func { |
407 | RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, |
408 | RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, |
409 | RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, |
410 | RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, |
411 | |
412 | NUM_OF_RTW89_MAC_C2H_FUNC_MCC, |
413 | }; |
414 | |
415 | enum rtw89_mac_c2h_mrc_func { |
416 | RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, |
417 | RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, |
418 | |
419 | NUM_OF_RTW89_MAC_C2H_FUNC_MRC, |
420 | }; |
421 | |
422 | enum rtw89_mac_c2h_class { |
423 | RTW89_MAC_C2H_CLASS_INFO = 0x0, |
424 | RTW89_MAC_C2H_CLASS_OFLD = 0x1, |
425 | RTW89_MAC_C2H_CLASS_TWT = 0x2, |
426 | RTW89_MAC_C2H_CLASS_WOW = 0x3, |
427 | RTW89_MAC_C2H_CLASS_MCC = 0x4, |
428 | RTW89_MAC_C2H_CLASS_FWDBG = 0x5, |
429 | RTW89_MAC_C2H_CLASS_MRC = 0xe, |
430 | RTW89_MAC_C2H_CLASS_MAX, |
431 | }; |
432 | |
433 | enum rtw89_mac_mcc_status { |
434 | RTW89_MAC_MCC_ADD_ROLE_OK = 0, |
435 | RTW89_MAC_MCC_START_GROUP_OK = 1, |
436 | RTW89_MAC_MCC_STOP_GROUP_OK = 2, |
437 | RTW89_MAC_MCC_DEL_GROUP_OK = 3, |
438 | RTW89_MAC_MCC_RESET_GROUP_OK = 4, |
439 | RTW89_MAC_MCC_SWITCH_CH_OK = 5, |
440 | RTW89_MAC_MCC_TXNULL0_OK = 6, |
441 | RTW89_MAC_MCC_TXNULL1_OK = 7, |
442 | |
443 | RTW89_MAC_MCC_SWITCH_EARLY = 10, |
444 | RTW89_MAC_MCC_TBTT = 11, |
445 | RTW89_MAC_MCC_DURATION_START = 12, |
446 | RTW89_MAC_MCC_DURATION_END = 13, |
447 | |
448 | RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, |
449 | RTW89_MAC_MCC_START_GROUP_FAIL = 21, |
450 | RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, |
451 | RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, |
452 | RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, |
453 | RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, |
454 | RTW89_MAC_MCC_TXNULL0_FAIL = 26, |
455 | RTW89_MAC_MCC_TXNULL1_FAIL = 27, |
456 | }; |
457 | |
458 | enum rtw89_mac_mrc_status { |
459 | RTW89_MAC_MRC_START_SCH_OK = 0, |
460 | RTW89_MAC_MRC_STOP_SCH_OK = 1, |
461 | RTW89_MAC_MRC_DEL_SCH_OK = 2, |
462 | }; |
463 | |
464 | struct rtw89_mac_ax_coex { |
465 | #define RTW89_MAC_AX_COEX_RTK_MODE 0 |
466 | #define RTW89_MAC_AX_COEX_CSR_MODE 1 |
467 | u8 pta_mode; |
468 | #define RTW89_MAC_AX_COEX_INNER 0 |
469 | #define RTW89_MAC_AX_COEX_OUTPUT 1 |
470 | #define RTW89_MAC_AX_COEX_INPUT 2 |
471 | u8 direction; |
472 | }; |
473 | |
474 | struct rtw89_mac_ax_plt { |
475 | #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) |
476 | #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) |
477 | #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) |
478 | #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) |
479 | u8 band; |
480 | u8 tx; |
481 | u8 rx; |
482 | }; |
483 | |
484 | enum rtw89_mac_bf_rrsc_rate { |
485 | RTW89_MAC_BF_RRSC_6M = 0, |
486 | RTW89_MAC_BF_RRSC_9M = 1, |
487 | RTW89_MAC_BF_RRSC_12M, |
488 | RTW89_MAC_BF_RRSC_18M, |
489 | RTW89_MAC_BF_RRSC_24M, |
490 | RTW89_MAC_BF_RRSC_36M, |
491 | RTW89_MAC_BF_RRSC_48M, |
492 | RTW89_MAC_BF_RRSC_54M, |
493 | RTW89_MAC_BF_RRSC_HT_MSC0, |
494 | RTW89_MAC_BF_RRSC_HT_MSC1, |
495 | RTW89_MAC_BF_RRSC_HT_MSC2, |
496 | RTW89_MAC_BF_RRSC_HT_MSC3, |
497 | RTW89_MAC_BF_RRSC_HT_MSC4, |
498 | RTW89_MAC_BF_RRSC_HT_MSC5, |
499 | RTW89_MAC_BF_RRSC_HT_MSC6, |
500 | RTW89_MAC_BF_RRSC_HT_MSC7, |
501 | RTW89_MAC_BF_RRSC_VHT_MSC0, |
502 | RTW89_MAC_BF_RRSC_VHT_MSC1, |
503 | RTW89_MAC_BF_RRSC_VHT_MSC2, |
504 | RTW89_MAC_BF_RRSC_VHT_MSC3, |
505 | RTW89_MAC_BF_RRSC_VHT_MSC4, |
506 | RTW89_MAC_BF_RRSC_VHT_MSC5, |
507 | RTW89_MAC_BF_RRSC_VHT_MSC6, |
508 | RTW89_MAC_BF_RRSC_VHT_MSC7, |
509 | RTW89_MAC_BF_RRSC_HE_MSC0, |
510 | RTW89_MAC_BF_RRSC_HE_MSC1, |
511 | RTW89_MAC_BF_RRSC_HE_MSC2, |
512 | RTW89_MAC_BF_RRSC_HE_MSC3, |
513 | RTW89_MAC_BF_RRSC_HE_MSC4, |
514 | RTW89_MAC_BF_RRSC_HE_MSC5, |
515 | RTW89_MAC_BF_RRSC_HE_MSC6, |
516 | RTW89_MAC_BF_RRSC_HE_MSC7 = 31, |
517 | RTW89_MAC_BF_RRSC_MAX = 32 |
518 | }; |
519 | |
520 | #define RTW89_R32_EA 0xEAEAEAEA |
521 | #define RTW89_R32_DEAD 0xDEADBEEF |
522 | #define MAC_REG_POOL_COUNT 10 |
523 | #define ACCESS_CMAC(_addr) \ |
524 | ({typeof(_addr) __addr = (_addr); \ |
525 | __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) |
526 | #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 |
527 | #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 |
528 | |
529 | #define PTCL_IDLE_POLL_CNT 10000 |
530 | #define SW_CVR_DUR_US 8 |
531 | #define SW_CVR_CNT 8 |
532 | |
533 | #define DLE_BOUND_UNIT (8 * 1024) |
534 | #define DLE_WAIT_CNT 2000 |
535 | #define TRXCFG_WAIT_CNT 2000 |
536 | |
537 | #define RTW89_WDE_PG_64 64 |
538 | #define RTW89_WDE_PG_128 128 |
539 | #define RTW89_WDE_PG_256 256 |
540 | |
541 | #define S_AX_WDE_PAGE_SEL_64 0 |
542 | #define S_AX_WDE_PAGE_SEL_128 1 |
543 | #define S_AX_WDE_PAGE_SEL_256 2 |
544 | |
545 | #define RTW89_PLE_PG_64 64 |
546 | #define RTW89_PLE_PG_128 128 |
547 | #define RTW89_PLE_PG_256 256 |
548 | |
549 | #define S_AX_PLE_PAGE_SEL_64 0 |
550 | #define S_AX_PLE_PAGE_SEL_128 1 |
551 | #define S_AX_PLE_PAGE_SEL_256 2 |
552 | |
553 | #define B_CMAC0_MGQ_NORMAL BIT(2) |
554 | #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) |
555 | #define B_CMAC0_CPUMGQ BIT(4) |
556 | #define B_CMAC1_MGQ_NORMAL BIT(10) |
557 | #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) |
558 | #define B_CMAC1_CPUMGQ BIT(12) |
559 | |
560 | #define B_CMAC0_MGQ_NORMAL_BE BIT(2) |
561 | #define B_CMAC1_MGQ_NORMAL_BE BIT(30) |
562 | |
563 | #define QEMP_ACQ_GRP_MACID_NUM 8 |
564 | #define QEMP_ACQ_GRP_QSEL_SH 4 |
565 | #define QEMP_ACQ_GRP_QSEL_MASK 0xF |
566 | |
567 | #define SDIO_LOCAL_BASE_ADDR 0x80000000 |
568 | |
569 | #define PWR_CMD_WRITE 0 |
570 | #define PWR_CMD_POLL 1 |
571 | #define PWR_CMD_DELAY 2 |
572 | #define PWR_CMD_END 3 |
573 | |
574 | #define PWR_INTF_MSK_SDIO BIT(0) |
575 | #define PWR_INTF_MSK_USB BIT(1) |
576 | #define PWR_INTF_MSK_PCIE BIT(2) |
577 | #define PWR_INTF_MSK_ALL 0x7 |
578 | |
579 | #define PWR_BASE_MAC 0 |
580 | #define PWR_BASE_USB 1 |
581 | #define PWR_BASE_PCIE 2 |
582 | #define PWR_BASE_SDIO 3 |
583 | |
584 | #define PWR_CV_MSK_A BIT(0) |
585 | #define PWR_CV_MSK_B BIT(1) |
586 | #define PWR_CV_MSK_C BIT(2) |
587 | #define PWR_CV_MSK_D BIT(3) |
588 | #define PWR_CV_MSK_E BIT(4) |
589 | #define PWR_CV_MSK_F BIT(5) |
590 | #define PWR_CV_MSK_G BIT(6) |
591 | #define PWR_CV_MSK_TEST BIT(7) |
592 | #define PWR_CV_MSK_ALL 0xFF |
593 | |
594 | #define PWR_DELAY_US 0 |
595 | #define PWR_DELAY_MS 1 |
596 | |
597 | /* STA scheduler */ |
598 | #define SS_MACID_SH 8 |
599 | #define SS_TX_LEN_MSK 0x1FFFFF |
600 | #define SS_CTRL1_R_TX_LEN 5 |
601 | #define SS_CTRL1_R_NEXT_LINK 20 |
602 | #define SS_LINK_SIZE 256 |
603 | |
604 | /* MAC debug port */ |
605 | #define TMAC_DBG_SEL_C0 0xA5 |
606 | #define RMAC_DBG_SEL_C0 0xA6 |
607 | #define TRXPTCL_DBG_SEL_C0 0xA7 |
608 | #define TMAC_DBG_SEL_C1 0xB5 |
609 | #define RMAC_DBG_SEL_C1 0xB6 |
610 | #define TRXPTCL_DBG_SEL_C1 0xB7 |
611 | #define FW_PROG_CNTR_DBG_SEL 0xF2 |
612 | #define PCIE_TXDMA_DBG_SEL 0x30 |
613 | #define PCIE_RXDMA_DBG_SEL 0x31 |
614 | #define PCIE_CVT_DBG_SEL 0x32 |
615 | #define PCIE_CXPL_DBG_SEL 0x33 |
616 | #define PCIE_IO_DBG_SEL 0x37 |
617 | #define PCIE_MISC_DBG_SEL 0x38 |
618 | #define PCIE_MISC2_DBG_SEL 0x00 |
619 | #define MAC_DBG_SEL 1 |
620 | #define RMAC_CMAC_DBG_SEL 1 |
621 | |
622 | /* TRXPTCL dbg port sel */ |
623 | #define TRXPTRL_DBG_SEL_TMAC 0 |
624 | #define TRXPTRL_DBG_SEL_RMAC 1 |
625 | |
626 | struct rtw89_cpuio_ctrl { |
627 | u16 pkt_num; |
628 | u16 start_pktid; |
629 | u16 end_pktid; |
630 | u8 cmd_type; |
631 | u8 macid; |
632 | u8 src_pid; |
633 | u8 src_qid; |
634 | u8 dst_pid; |
635 | u8 dst_qid; |
636 | u16 pktid; |
637 | }; |
638 | |
639 | struct rtw89_mac_dbg_port_info { |
640 | u32 sel_addr; |
641 | u8 sel_byte; |
642 | u32 sel_msk; |
643 | u32 srt; |
644 | u32 end; |
645 | u32 rd_addr; |
646 | u8 rd_byte; |
647 | u32 rd_msk; |
648 | }; |
649 | |
650 | #define QLNKTBL_ADDR_INFO_SEL BIT(0) |
651 | #define QLNKTBL_ADDR_INFO_SEL_0 0 |
652 | #define QLNKTBL_ADDR_INFO_SEL_1 1 |
653 | #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) |
654 | #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) |
655 | |
656 | struct rtw89_mac_dle_dfi_ctrl { |
657 | enum rtw89_mac_dle_ctrl_type type; |
658 | u32 target; |
659 | u32 addr; |
660 | u32 out_data; |
661 | }; |
662 | |
663 | struct rtw89_mac_dle_dfi_quota { |
664 | enum rtw89_mac_dle_ctrl_type dle_type; |
665 | u32 qtaid; |
666 | u16 rsv_pgnum; |
667 | u16 use_pgnum; |
668 | }; |
669 | |
670 | struct rtw89_mac_dle_dfi_qempty { |
671 | enum rtw89_mac_dle_ctrl_type dle_type; |
672 | u32 grpsel; |
673 | u32 qempty; |
674 | }; |
675 | |
676 | enum rtw89_mac_dle_rsvd_qt_type { |
677 | DLE_RSVD_QT_MPDU_INFO, |
678 | DLE_RSVD_QT_B0_CSI, |
679 | DLE_RSVD_QT_B1_CSI, |
680 | DLE_RSVD_QT_B0_LMR, |
681 | DLE_RSVD_QT_B1_LMR, |
682 | DLE_RSVD_QT_B0_FTM, |
683 | DLE_RSVD_QT_B1_FTM, |
684 | }; |
685 | |
686 | struct rtw89_mac_dle_rsvd_qt_cfg { |
687 | u16 pktid; |
688 | u16 pg_num; |
689 | u32 size; |
690 | }; |
691 | |
692 | enum rtw89_mac_error_scenario { |
693 | RTW89_RXI300_ERROR = 1, |
694 | RTW89_WCPU_CPU_EXCEPTION = 2, |
695 | RTW89_WCPU_ASSERTION = 3, |
696 | }; |
697 | |
698 | #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) |
699 | |
700 | /* Define DBG and recovery enum */ |
701 | enum mac_ax_err_info { |
702 | /* Get error info */ |
703 | |
704 | /* L0 */ |
705 | MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, |
706 | MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, |
707 | MAC_AX_ERR_L0_RESET_DONE = 0x0003, |
708 | MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, |
709 | |
710 | /* L1 */ |
711 | MAC_AX_ERR_L1_PREERR_DMAC = 0x999, |
712 | MAC_AX_ERR_L1_ERR_DMAC = 0x1000, |
713 | MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, |
714 | MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, |
715 | MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, |
716 | MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, |
717 | |
718 | /* L2 */ |
719 | /* address hole (master) */ |
720 | MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, |
721 | MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, |
722 | MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, |
723 | MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, |
724 | MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, |
725 | MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, |
726 | MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, |
727 | MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, |
728 | |
729 | /* AHB bridge timeout (master) */ |
730 | MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, |
731 | MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, |
732 | MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, |
733 | MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, |
734 | MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, |
735 | MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, |
736 | MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, |
737 | MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, |
738 | |
739 | /* APB_SA bridge timeout (master + slave) */ |
740 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, |
741 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, |
742 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, |
743 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, |
744 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, |
745 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, |
746 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, |
747 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, |
748 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, |
749 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, |
750 | MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, |
751 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, |
752 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, |
753 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, |
754 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, |
755 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, |
756 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, |
757 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, |
758 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, |
759 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, |
760 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, |
761 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, |
762 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, |
763 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, |
764 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, |
765 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, |
766 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, |
767 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, |
768 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, |
769 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, |
770 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, |
771 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, |
772 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, |
773 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, |
774 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, |
775 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, |
776 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, |
777 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, |
778 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, |
779 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, |
780 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, |
781 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, |
782 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, |
783 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, |
784 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, |
785 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, |
786 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, |
787 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, |
788 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, |
789 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, |
790 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, |
791 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, |
792 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, |
793 | MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, |
794 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, |
795 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, |
796 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, |
797 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, |
798 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, |
799 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, |
800 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, |
801 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, |
802 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, |
803 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, |
804 | MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, |
805 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, |
806 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, |
807 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, |
808 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, |
809 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, |
810 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, |
811 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, |
812 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, |
813 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, |
814 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, |
815 | MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, |
816 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, |
817 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, |
818 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, |
819 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, |
820 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, |
821 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, |
822 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, |
823 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, |
824 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, |
825 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, |
826 | MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, |
827 | |
828 | /* APB_BBRF bridge timeout (master) */ |
829 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, |
830 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, |
831 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, |
832 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, |
833 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, |
834 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, |
835 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, |
836 | MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, |
837 | MAC_AX_ERR_L2_RESET_DONE = 0x2400, |
838 | MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, |
839 | MAC_AX_ERR_CPU_EXCEPTION = 0x3000, |
840 | MAC_AX_ERR_ASSERTION = 0x4000, |
841 | MAC_AX_ERR_RXI300 = 0x5000, |
842 | MAC_AX_GET_ERR_MAX, |
843 | MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, |
844 | |
845 | /* set error info */ |
846 | MAC_AX_ERR_L1_DISABLE_EN = 0x0001, |
847 | MAC_AX_ERR_L1_RCVY_EN = 0x0002, |
848 | MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, |
849 | MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, |
850 | MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, |
851 | MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, |
852 | MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, |
853 | MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, |
854 | MAC_AX_ERR_L0_RCVY_EN = 0x0013, |
855 | MAC_AX_SET_ERR_MAX, |
856 | }; |
857 | |
858 | struct rtw89_mac_size_set { |
859 | const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; |
860 | const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; |
861 | const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; |
862 | const struct rtw89_dle_size wde_size0; |
863 | const struct rtw89_dle_size wde_size0_v1; |
864 | const struct rtw89_dle_size wde_size4; |
865 | const struct rtw89_dle_size wde_size4_v1; |
866 | const struct rtw89_dle_size wde_size6; |
867 | const struct rtw89_dle_size wde_size7; |
868 | const struct rtw89_dle_size wde_size9; |
869 | const struct rtw89_dle_size wde_size18; |
870 | const struct rtw89_dle_size wde_size19; |
871 | const struct rtw89_dle_size ple_size0; |
872 | const struct rtw89_dle_size ple_size0_v1; |
873 | const struct rtw89_dle_size ple_size3_v1; |
874 | const struct rtw89_dle_size ple_size4; |
875 | const struct rtw89_dle_size ple_size6; |
876 | const struct rtw89_dle_size ple_size8; |
877 | const struct rtw89_dle_size ple_size18; |
878 | const struct rtw89_dle_size ple_size19; |
879 | const struct rtw89_wde_quota wde_qt0; |
880 | const struct rtw89_wde_quota wde_qt0_v1; |
881 | const struct rtw89_wde_quota wde_qt4; |
882 | const struct rtw89_wde_quota wde_qt6; |
883 | const struct rtw89_wde_quota wde_qt7; |
884 | const struct rtw89_wde_quota wde_qt17; |
885 | const struct rtw89_wde_quota wde_qt18; |
886 | const struct rtw89_ple_quota ple_qt0; |
887 | const struct rtw89_ple_quota ple_qt1; |
888 | const struct rtw89_ple_quota ple_qt4; |
889 | const struct rtw89_ple_quota ple_qt5; |
890 | const struct rtw89_ple_quota ple_qt9; |
891 | const struct rtw89_ple_quota ple_qt13; |
892 | const struct rtw89_ple_quota ple_qt18; |
893 | const struct rtw89_ple_quota ple_qt44; |
894 | const struct rtw89_ple_quota ple_qt45; |
895 | const struct rtw89_ple_quota ple_qt46; |
896 | const struct rtw89_ple_quota ple_qt47; |
897 | const struct rtw89_ple_quota ple_qt58; |
898 | const struct rtw89_ple_quota ple_qt_52a_wow; |
899 | const struct rtw89_ple_quota ple_qt_52b_wow; |
900 | const struct rtw89_ple_quota ple_qt_51b_wow; |
901 | const struct rtw89_rsvd_quota ple_rsvd_qt0; |
902 | const struct rtw89_rsvd_quota ple_rsvd_qt1; |
903 | const struct rtw89_dle_rsvd_size rsvd0_size0; |
904 | const struct rtw89_dle_rsvd_size rsvd1_size0; |
905 | }; |
906 | |
907 | extern const struct rtw89_mac_size_set rtw89_mac_size; |
908 | |
909 | struct rtw89_mac_gen_def { |
910 | u32 band1_offset; |
911 | u32 filter_model_addr; |
912 | u32 indir_access_addr; |
913 | const u32 *mem_base_addrs; |
914 | u32 rx_fltr; |
915 | const struct rtw89_port_reg *port_base; |
916 | u32 agg_len_ht; |
917 | u32 ps_status; |
918 | |
919 | struct rtw89_reg_def muedca_ctrl; |
920 | struct rtw89_reg_def bfee_ctrl; |
921 | struct rtw89_reg_def narrow_bw_ru_dis; |
922 | struct rtw89_reg_def wow_ctrl; |
923 | |
924 | int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, |
925 | enum rtw89_mac_hwmod_sel sel); |
926 | int (*sys_init)(struct rtw89_dev *rtwdev); |
927 | int (*trx_init)(struct rtw89_dev *rtwdev); |
928 | void (*hci_func_en)(struct rtw89_dev *rtwdev); |
929 | void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); |
930 | void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); |
931 | void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); |
932 | void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, |
933 | struct ieee80211_sta *sta); |
934 | |
935 | int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, |
936 | enum rtw89_machdr_frame_type type, |
937 | enum rtw89_mac_fwd_target fwd_target, |
938 | u8 mac_idx); |
939 | int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); |
940 | |
941 | int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); |
942 | int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); |
943 | int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); |
944 | void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); |
945 | void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); |
946 | void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); |
947 | void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); |
948 | void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, |
949 | const struct rtw89_wde_quota *min_cfg, |
950 | const struct rtw89_wde_quota *max_cfg, |
951 | u16 ext_wde_min_qt_wcpu); |
952 | void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, |
953 | const struct rtw89_ple_quota *min_cfg, |
954 | const struct rtw89_ple_quota *max_cfg); |
955 | int (*set_cpuio)(struct rtw89_dev *rtwdev, |
956 | struct rtw89_cpuio_ctrl *ctrl_para, bool wd); |
957 | int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); |
958 | |
959 | void (*disable_cpu)(struct rtw89_dev *rtwdev); |
960 | int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, |
961 | bool dlfw, bool include_bb); |
962 | u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); |
963 | int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); |
964 | int (*parse_efuse_map)(struct rtw89_dev *rtwdev); |
965 | int (*parse_phycap_map)(struct rtw89_dev *rtwdev); |
966 | int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); |
967 | |
968 | int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); |
969 | u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); |
970 | |
971 | bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, |
972 | enum rtw89_phy_idx phy_idx, |
973 | u32 reg_base, u32 *cr); |
974 | |
975 | int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); |
976 | int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); |
977 | |
978 | void (*dump_qta_lost)(struct rtw89_dev *rtwdev); |
979 | void (*dump_err_status)(struct rtw89_dev *rtwdev, |
980 | enum mac_ax_err_info err); |
981 | |
982 | bool (*is_txq_empty)(struct rtw89_dev *rtwdev); |
983 | |
984 | int (*add_chan_list)(struct rtw89_dev *rtwdev, |
985 | struct rtw89_vif *rtwvif, bool connected); |
986 | int (*scan_offload)(struct rtw89_dev *rtwdev, |
987 | struct rtw89_scan_option *option, |
988 | struct rtw89_vif *rtwvif); |
989 | |
990 | int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); |
991 | }; |
992 | |
993 | extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; |
994 | extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; |
995 | |
996 | static inline |
997 | u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) |
998 | { |
999 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1000 | |
1001 | return band == 0 ? reg_base : (reg_base + mac->band1_offset); |
1002 | } |
1003 | |
1004 | static inline |
1005 | u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) |
1006 | { |
1007 | return rtw89_mac_reg_by_idx(rtwdev, reg_base: base + port * 0x40, band: mac_idx); |
1008 | } |
1009 | |
1010 | static inline u32 |
1011 | rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) |
1012 | { |
1013 | u32 reg; |
1014 | |
1015 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1016 | return rtw89_read32(rtwdev, addr: reg); |
1017 | } |
1018 | |
1019 | static inline u32 |
1020 | rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1021 | u32 base, u32 mask) |
1022 | { |
1023 | u32 reg; |
1024 | |
1025 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1026 | return rtw89_read32_mask(rtwdev, addr: reg, mask); |
1027 | } |
1028 | |
1029 | static inline void |
1030 | rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, |
1031 | u32 data) |
1032 | { |
1033 | u32 reg; |
1034 | |
1035 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1036 | rtw89_write32(rtwdev, addr: reg, data); |
1037 | } |
1038 | |
1039 | static inline void |
1040 | rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1041 | u32 base, u32 mask, u32 data) |
1042 | { |
1043 | u32 reg; |
1044 | |
1045 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1046 | rtw89_write32_mask(rtwdev, addr: reg, mask, data); |
1047 | } |
1048 | |
1049 | static inline void |
1050 | rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1051 | u32 base, u32 mask, u16 data) |
1052 | { |
1053 | u32 reg; |
1054 | |
1055 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1056 | rtw89_write16_mask(rtwdev, addr: reg, mask, data); |
1057 | } |
1058 | |
1059 | static inline void |
1060 | rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1061 | u32 base, u32 bit) |
1062 | { |
1063 | u32 reg; |
1064 | |
1065 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1066 | rtw89_write32_clr(rtwdev, addr: reg, bit); |
1067 | } |
1068 | |
1069 | static inline void |
1070 | rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1071 | u32 base, u16 bit) |
1072 | { |
1073 | u32 reg; |
1074 | |
1075 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1076 | rtw89_write16_clr(rtwdev, addr: reg, bit); |
1077 | } |
1078 | |
1079 | static inline void |
1080 | rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1081 | u32 base, u32 bit) |
1082 | { |
1083 | u32 reg; |
1084 | |
1085 | reg = rtw89_mac_reg_by_port(rtwdev, base, port: rtwvif->port, mac_idx: rtwvif->mac_idx); |
1086 | rtw89_write32_set(rtwdev, addr: reg, bit); |
1087 | } |
1088 | |
1089 | void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); |
1090 | int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); |
1091 | int rtw89_mac_init(struct rtw89_dev *rtwdev); |
1092 | int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, |
1093 | enum rtw89_qta_mode ext_mode); |
1094 | int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); |
1095 | int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, |
1096 | enum rtw89_qta_mode mode); |
1097 | bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); |
1098 | static inline |
1099 | int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, |
1100 | enum rtw89_mac_hwmod_sel sel) |
1101 | { |
1102 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1103 | |
1104 | return mac->check_mac_en(rtwdev, band, sel); |
1105 | } |
1106 | |
1107 | int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); |
1108 | int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); |
1109 | int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); |
1110 | int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, |
1111 | struct rtw89_mac_dle_dfi_quota *quota); |
1112 | void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); |
1113 | int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, |
1114 | struct rtw89_mac_dle_dfi_qempty *qempty); |
1115 | void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, |
1116 | enum mac_ax_err_info err); |
1117 | int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); |
1118 | int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
1119 | void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, |
1120 | struct rtw89_vif *rtwvif, |
1121 | struct rtw89_vif *rtwvif_src, |
1122 | u16 offset_tu); |
1123 | int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, |
1124 | u64 *tsf); |
1125 | void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, |
1126 | struct rtw89_vif *rtwvif, bool en); |
1127 | void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, |
1128 | struct ieee80211_vif *vif); |
1129 | void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
1130 | void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); |
1131 | int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); |
1132 | int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); |
1133 | int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); |
1134 | |
1135 | static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) |
1136 | { |
1137 | const struct rtw89_chip_info *chip = rtwdev->chip; |
1138 | |
1139 | return chip->ops->enable_bb_rf(rtwdev); |
1140 | } |
1141 | |
1142 | static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) |
1143 | { |
1144 | const struct rtw89_chip_info *chip = rtwdev->chip; |
1145 | |
1146 | return chip->ops->disable_bb_rf(rtwdev); |
1147 | } |
1148 | |
1149 | static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) |
1150 | { |
1151 | int ret; |
1152 | |
1153 | if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) |
1154 | return 0; |
1155 | |
1156 | ret = rtw89_chip_disable_bb_rf(rtwdev); |
1157 | if (ret) |
1158 | return ret; |
1159 | ret = rtw89_chip_enable_bb_rf(rtwdev); |
1160 | if (ret) |
1161 | return ret; |
1162 | |
1163 | return 0; |
1164 | } |
1165 | |
1166 | u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); |
1167 | int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); |
1168 | bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, |
1169 | u8 class, u8 func); |
1170 | void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, |
1171 | u32 len, u8 class, u8 func); |
1172 | int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); |
1173 | int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, |
1174 | u32 *tx_en, enum rtw89_sch_tx_sel sel); |
1175 | int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, |
1176 | u32 *tx_en, enum rtw89_sch_tx_sel sel); |
1177 | int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, |
1178 | u32 *tx_en, enum rtw89_sch_tx_sel sel); |
1179 | int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); |
1180 | int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); |
1181 | int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); |
1182 | |
1183 | static inline |
1184 | int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) |
1185 | { |
1186 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1187 | |
1188 | return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); |
1189 | } |
1190 | |
1191 | void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); |
1192 | void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); |
1193 | int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); |
1194 | int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, |
1195 | const struct rtw89_mac_ax_coex *coex); |
1196 | int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, |
1197 | const struct rtw89_mac_ax_coex_gnt *gnt_cfg); |
1198 | int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, |
1199 | const struct rtw89_mac_ax_coex_gnt *gnt_cfg); |
1200 | int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, |
1201 | const struct rtw89_mac_ax_coex_gnt *gnt_cfg); |
1202 | |
1203 | static inline |
1204 | int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) |
1205 | { |
1206 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1207 | |
1208 | return mac->cfg_plt(rtwdev, plt); |
1209 | } |
1210 | |
1211 | static inline |
1212 | u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) |
1213 | { |
1214 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1215 | |
1216 | return mac->get_plt_cnt(rtwdev, band); |
1217 | } |
1218 | |
1219 | void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); |
1220 | u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); |
1221 | bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); |
1222 | int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); |
1223 | int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); |
1224 | int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); |
1225 | void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); |
1226 | void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); |
1227 | |
1228 | static inline |
1229 | void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, |
1230 | struct ieee80211_sta *sta) |
1231 | { |
1232 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1233 | |
1234 | if (mac->bf_assoc) |
1235 | mac->bf_assoc(rtwdev, vif, sta); |
1236 | } |
1237 | |
1238 | void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, |
1239 | struct ieee80211_sta *sta); |
1240 | void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, |
1241 | struct ieee80211_bss_conf *conf); |
1242 | void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, |
1243 | struct ieee80211_sta *sta, bool disconnect); |
1244 | void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); |
1245 | void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); |
1246 | int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
1247 | int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
1248 | int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, |
1249 | struct rtw89_vif *rtwvif, bool en); |
1250 | int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); |
1251 | |
1252 | static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) |
1253 | { |
1254 | if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) |
1255 | return; |
1256 | |
1257 | if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) |
1258 | return; |
1259 | |
1260 | _rtw89_mac_bf_monitor_track(rtwdev); |
1261 | } |
1262 | |
1263 | static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, |
1264 | enum rtw89_phy_idx phy_idx, |
1265 | u32 reg_base, u32 *val) |
1266 | { |
1267 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1268 | u32 cr; |
1269 | |
1270 | if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) |
1271 | return -EINVAL; |
1272 | |
1273 | *val = rtw89_read32(rtwdev, addr: cr); |
1274 | return 0; |
1275 | } |
1276 | |
1277 | static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, |
1278 | enum rtw89_phy_idx phy_idx, |
1279 | u32 reg_base, u32 val) |
1280 | { |
1281 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1282 | u32 cr; |
1283 | |
1284 | if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) |
1285 | return -EINVAL; |
1286 | |
1287 | rtw89_write32(rtwdev, addr: cr, data: val); |
1288 | return 0; |
1289 | } |
1290 | |
1291 | static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, |
1292 | enum rtw89_phy_idx phy_idx, |
1293 | u32 reg_base, u32 mask, u32 val) |
1294 | { |
1295 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1296 | u32 cr; |
1297 | |
1298 | if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) |
1299 | return -EINVAL; |
1300 | |
1301 | rtw89_write32_mask(rtwdev, addr: cr, mask, data: val); |
1302 | return 0; |
1303 | } |
1304 | |
1305 | static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, |
1306 | bool enable) |
1307 | { |
1308 | const struct rtw89_chip_info *chip = rtwdev->chip; |
1309 | |
1310 | if (enable) |
1311 | rtw89_write32_set(rtwdev, addr: chip->hci_func_en_addr, |
1312 | B_AX_HCI_TXDMA_EN); |
1313 | else |
1314 | rtw89_write32_clr(rtwdev, addr: chip->hci_func_en_addr, |
1315 | B_AX_HCI_TXDMA_EN); |
1316 | } |
1317 | |
1318 | static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, |
1319 | bool enable) |
1320 | { |
1321 | const struct rtw89_chip_info *chip = rtwdev->chip; |
1322 | |
1323 | if (enable) |
1324 | rtw89_write32_set(rtwdev, addr: chip->hci_func_en_addr, |
1325 | B_AX_HCI_RXDMA_EN); |
1326 | else |
1327 | rtw89_write32_clr(rtwdev, addr: chip->hci_func_en_addr, |
1328 | B_AX_HCI_RXDMA_EN); |
1329 | } |
1330 | |
1331 | static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, |
1332 | bool enable) |
1333 | { |
1334 | const struct rtw89_chip_info *chip = rtwdev->chip; |
1335 | |
1336 | if (enable) |
1337 | rtw89_write32_set(rtwdev, addr: chip->hci_func_en_addr, |
1338 | B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); |
1339 | else |
1340 | rtw89_write32_clr(rtwdev, addr: chip->hci_func_en_addr, |
1341 | B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); |
1342 | } |
1343 | |
1344 | static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) |
1345 | { |
1346 | u32 val; |
1347 | |
1348 | val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, |
1349 | B_AX_WLMAC_PWR_STE_MASK); |
1350 | |
1351 | return !!val; |
1352 | } |
1353 | |
1354 | int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, |
1355 | bool resume, u32 tx_time); |
1356 | int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, |
1357 | u32 *tx_time); |
1358 | int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, |
1359 | struct rtw89_sta *rtwsta, |
1360 | bool resume, u8 tx_retry); |
1361 | int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, |
1362 | struct rtw89_sta *rtwsta, u8 *tx_retry); |
1363 | |
1364 | enum rtw89_mac_xtal_si_offset { |
1365 | XTAL0 = 0x0, |
1366 | XTAL3 = 0x3, |
1367 | XTAL_SI_XTAL_SC_XI = 0x04, |
1368 | #define XTAL_SC_XI_MASK GENMASK(7, 0) |
1369 | XTAL_SI_XTAL_SC_XO = 0x05, |
1370 | #define XTAL_SC_XO_MASK GENMASK(7, 0) |
1371 | XTAL_SI_XREF_MODE = 0x0B, |
1372 | XTAL_SI_PWR_CUT = 0x10, |
1373 | #define XTAL_SI_SMALL_PWR_CUT BIT(0) |
1374 | #define XTAL_SI_BIG_PWR_CUT BIT(1) |
1375 | XTAL_SI_XTAL_DRV = 0x15, |
1376 | #define XTAL_SI_DRV_LATCH BIT(4) |
1377 | XTAL_SI_XTAL_PLL = 0x16, |
1378 | XTAL_SI_XTAL_XMD_2 = 0x24, |
1379 | #define XTAL_SI_LDO_LPS GENMASK(6, 4) |
1380 | XTAL_SI_XTAL_XMD_4 = 0x26, |
1381 | #define XTAL_SI_LPS_CAP GENMASK(3, 0) |
1382 | XTAL_SI_XREF_RF1 = 0x2D, |
1383 | XTAL_SI_XREF_RF2 = 0x2E, |
1384 | XTAL_SI_CV = 0x41, |
1385 | #define XTAL_SI_ACV_MASK GENMASK(3, 0) |
1386 | XTAL_SI_LOW_ADDR = 0x62, |
1387 | #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) |
1388 | XTAL_SI_CTRL = 0x63, |
1389 | #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) |
1390 | #define XTAL_SI_RDY BIT(5) |
1391 | #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) |
1392 | XTAL_SI_READ_VAL = 0x7A, |
1393 | XTAL_SI_WL_RFC_S0 = 0x80, |
1394 | #define XTAL_SI_RF00S_EN GENMASK(2, 0) |
1395 | #define XTAL_SI_RF00 BIT(0) |
1396 | XTAL_SI_WL_RFC_S1 = 0x81, |
1397 | #define XTAL_SI_RF10S_EN GENMASK(2, 0) |
1398 | #define XTAL_SI_RF10 BIT(0) |
1399 | XTAL_SI_ANAPAR_WL = 0x90, |
1400 | #define XTAL_SI_SRAM2RFC BIT(7) |
1401 | #define XTAL_SI_GND_SHDN_WL BIT(6) |
1402 | #define XTAL_SI_SHDN_WL BIT(5) |
1403 | #define XTAL_SI_RFC2RF BIT(4) |
1404 | #define XTAL_SI_OFF_EI BIT(3) |
1405 | #define XTAL_SI_OFF_WEI BIT(2) |
1406 | #define XTAL_SI_PON_EI BIT(1) |
1407 | #define XTAL_SI_PON_WEI BIT(0) |
1408 | XTAL_SI_SRAM_CTRL = 0xA1, |
1409 | #define XTAL_SI_SRAM_DIS BIT(1) |
1410 | #define FULL_BIT_MASK GENMASK(7, 0) |
1411 | XTAL_SI_APBT = 0xD1, |
1412 | XTAL_SI_PLL = 0xE0, |
1413 | XTAL_SI_PLL_1 = 0xE1, |
1414 | }; |
1415 | |
1416 | static inline |
1417 | int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) |
1418 | { |
1419 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1420 | |
1421 | return mac->write_xtal_si(rtwdev, offset, val, mask); |
1422 | } |
1423 | |
1424 | static inline |
1425 | int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) |
1426 | { |
1427 | const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; |
1428 | |
1429 | return mac->read_xtal_si(rtwdev, offset, val); |
1430 | } |
1431 | |
1432 | void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
1433 | int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); |
1434 | int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, |
1435 | enum rtw89_mac_idx band); |
1436 | void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); |
1437 | int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, |
1438 | bool band1_en); |
1439 | int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, |
1440 | enum rtw89_mac_dle_rsvd_qt_type type, |
1441 | struct rtw89_mac_dle_rsvd_qt_cfg *cfg); |
1442 | |
1443 | #endif |
1444 | |