1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2019-2020 Realtek Corporation |
3 | */ |
4 | |
5 | #ifndef __RTW89_PHY_H__ |
6 | #define __RTW89_PHY_H__ |
7 | |
8 | #include "core.h" |
9 | |
10 | #define RTW89_BBMCU_ADDR_OFFSET 0x30000 |
11 | #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) |
12 | |
13 | #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) |
14 | #define PHY_HEADLINE_VALID 0xf |
15 | #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) |
16 | #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ |
17 | FIELD_PREP(GENMASK(7, 0), cv)) |
18 | |
19 | #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) |
20 | #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) |
21 | #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) |
22 | #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) |
23 | #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) |
24 | #define PHY_COND_BRANCH_IF 0x8 |
25 | #define PHY_COND_BRANCH_ELIF 0x9 |
26 | #define PHY_COND_BRANCH_ELSE 0xa |
27 | #define PHY_COND_BRANCH_END 0xb |
28 | #define PHY_COND_CHECK 0x4 |
29 | #define PHY_COND_DONT_CARE 0xff |
30 | |
31 | #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) |
32 | #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) |
33 | #define RA_MASK_SUBCCK_RATES 0x5ULL |
34 | #define RA_MASK_SUBOFDM_RATES 0x10ULL |
35 | #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) |
36 | #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) |
37 | #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) |
38 | #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) |
39 | #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) |
40 | #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) |
41 | #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) |
42 | #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) |
43 | #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) |
44 | #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) |
45 | #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) |
46 | #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) |
47 | #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) |
48 | #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) |
49 | #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) |
50 | #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12) |
51 | #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28) |
52 | #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44) |
53 | #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60) |
54 | #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12) |
55 | |
56 | #define CFO_TRK_ENABLE_TH (2 << 2) |
57 | #define CFO_TRK_STOP_TH_4 (30 << 2) |
58 | #define CFO_TRK_STOP_TH_3 (20 << 2) |
59 | #define CFO_TRK_STOP_TH_2 (10 << 2) |
60 | #define CFO_TRK_STOP_TH_1 (00 << 2) |
61 | #define CFO_TRK_STOP_TH (2 << 2) |
62 | #define CFO_SW_COMP_FINE_TUNE (2 << 2) |
63 | #define CFO_PERIOD_CNT 15 |
64 | #define CFO_BOUND 64 |
65 | #define CFO_TP_UPPER 100 |
66 | #define CFO_TP_LOWER 50 |
67 | #define CFO_COMP_PERIOD 250 |
68 | #define CFO_COMP_WEIGHT 8 |
69 | #define MAX_CFO_TOLERANCE 30 |
70 | #define CFO_TF_CNT_TH 300 |
71 | |
72 | #define UL_TB_TF_CNT_L2H_TH 100 |
73 | #define UL_TB_TF_CNT_H2L_TH 70 |
74 | |
75 | #define ANTDIV_TRAINNING_CNT 2 |
76 | #define ANTDIV_TRAINNING_INTVL 30 |
77 | #define ANTDIV_DELAY 110 |
78 | #define ANTDIV_TP_DIFF_TH_HIGH 100 |
79 | #define ANTDIV_TP_DIFF_TH_LOW 5 |
80 | #define ANTDIV_EVM_DIFF_TH 8 |
81 | #define 3 |
82 | |
83 | #define CCX_MAX_PERIOD 2097 |
84 | #define CCX_MAX_PERIOD_UNIT 32 |
85 | #define MS_TO_4US_RATIO 250 |
86 | #define ENV_MNTR_FAIL_DWORD 0xffffffff |
87 | #define ENV_MNTR_IFSCLM_HIS_MAX 127 |
88 | #define PERMIL 1000 |
89 | #define PERCENT 100 |
90 | #define IFS_CLM_TH0_UPPER 64 |
91 | #define IFS_CLM_TH_MUL 4 |
92 | #define IFS_CLM_TH_START_IDX 0 |
93 | |
94 | #define TIA0_GAIN_A 12 |
95 | #define TIA0_GAIN_G 16 |
96 | #define LNA0_GAIN (-24) |
97 | #define U4_MAX_BIT 3 |
98 | #define U8_MAX_BIT 7 |
99 | #define DIG_GAIN_SHIFT 2 |
100 | #define DIG_GAIN 8 |
101 | |
102 | #define LNA_IDX_MAX 6 |
103 | #define LNA_IDX_MIN 0 |
104 | #define TIA_IDX_MAX 1 |
105 | #define TIA_IDX_MIN 0 |
106 | #define RXB_IDX_MAX 31 |
107 | #define RXB_IDX_MIN 0 |
108 | |
109 | #define 110 |
110 | #define 70 |
111 | #define 8 |
112 | #define (-18) |
113 | #define PD_TH_BW160_CMP_VAL 9 |
114 | #define PD_TH_BW80_CMP_VAL 6 |
115 | #define PD_TH_BW40_CMP_VAL 3 |
116 | #define PD_TH_BW20_CMP_VAL 0 |
117 | #define PD_TH_CMP_VAL 3 |
118 | #define PD_TH_SB_FLTR_CMP_VAL 7 |
119 | |
120 | #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) |
121 | #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) |
122 | #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) |
123 | #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) |
124 | #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) |
125 | |
126 | #define EDCCA_MAX 249 |
127 | #define EDCCA_TH_L2H_LB 66 |
128 | #define EDCCA_TH_REF 3 |
129 | #define EDCCA_HL_DIFF_NORMAL 8 |
130 | #define 110 |
131 | #define EDCCA_UNIT_CONVER 128 |
132 | |
133 | enum rtw89_phy_c2h_ra_func { |
134 | RTW89_PHY_C2H_FUNC_STS_RPT, |
135 | RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, |
136 | RTW89_PHY_C2H_FUNC_TXSTS, |
137 | RTW89_PHY_C2H_FUNC_RA_MAX, |
138 | }; |
139 | |
140 | enum rtw89_phy_c2h_rfk_log_func { |
141 | RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0, |
142 | RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1, |
143 | RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2, |
144 | RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, |
145 | RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, |
146 | RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, |
147 | |
148 | RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, |
149 | }; |
150 | |
151 | enum rtw89_phy_c2h_rfk_report_func { |
152 | RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, |
153 | }; |
154 | |
155 | enum rtw89_phy_c2h_dm_func { |
156 | RTW89_PHY_C2H_DM_FUNC_FW_TEST, |
157 | RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, |
158 | RTW89_PHY_C2H_DM_FUNC_SIGB, |
159 | RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, |
160 | RTW89_PHY_C2H_DM_FUNC_MCC_DIG, |
161 | RTW89_PHY_C2H_DM_FUNC_NUM, |
162 | }; |
163 | |
164 | enum rtw89_phy_c2h_class { |
165 | RTW89_PHY_C2H_CLASS_RUA, |
166 | RTW89_PHY_C2H_CLASS_RA, |
167 | RTW89_PHY_C2H_CLASS_DM, |
168 | RTW89_PHY_C2H_RFK_LOG = 0x8, |
169 | RTW89_PHY_C2H_RFK_REPORT = 0x9, |
170 | RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, |
171 | RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, |
172 | RTW89_PHY_C2H_CLASS_MAX, |
173 | }; |
174 | |
175 | enum rtw89_env_monitor_result_level { |
176 | RTW89_PHY_ENV_MON_CCX_FAIL = 0, |
177 | RTW89_PHY_ENV_MON_NHM = BIT(0), |
178 | RTW89_PHY_ENV_MON_CLM = BIT(1), |
179 | RTW89_PHY_ENV_MON_FAHM = BIT(2), |
180 | RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), |
181 | RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), |
182 | }; |
183 | |
184 | #define CCX_US_BASE_RATIO 4 |
185 | enum rtw89_ccx_unit { |
186 | RTW89_CCX_4_US = 0, |
187 | RTW89_CCX_8_US = 1, |
188 | RTW89_CCX_16_US = 2, |
189 | RTW89_CCX_32_US = 3 |
190 | }; |
191 | |
192 | enum rtw89_phy_status_ie_type { |
193 | RTW89_PHYSTS_IE00_CMN_CCK = 0, |
194 | RTW89_PHYSTS_IE01_CMN_OFDM = 1, |
195 | RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, |
196 | RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, |
197 | RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, |
198 | RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, |
199 | RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, |
200 | RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, |
201 | RTW89_PHYSTS_IE08_FTR_CH = 8, |
202 | RTW89_PHYSTS_IE09_FTR_0 = 9, |
203 | RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, |
204 | RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, |
205 | RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, |
206 | RTW89_PHYSTS_IE13_DL_MU_DEF = 13, |
207 | RTW89_PHYSTS_IE14_TB_UL_CQI = 14, |
208 | RTW89_PHYSTS_IE15_TB_UL_DEF = 15, |
209 | RTW89_PHYSTS_IE16_RSVD16 = 16, |
210 | RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, |
211 | RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, |
212 | RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, |
213 | RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, |
214 | RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, |
215 | RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, |
216 | RTW89_PHYSTS_IE23_RSVD23 = 23, |
217 | RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, |
218 | RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, |
219 | RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, |
220 | RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, |
221 | RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, |
222 | RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, |
223 | RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, |
224 | RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, |
225 | |
226 | /* keep last */ |
227 | RTW89_PHYSTS_IE_NUM, |
228 | RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 |
229 | }; |
230 | |
231 | enum rtw89_phy_status_bitmap { |
232 | RTW89_TD_SEARCH_FAIL = 0, |
233 | RTW89_BRK_BY_TX_PKT = 1, |
234 | RTW89_CCA_SPOOF = 2, |
235 | RTW89_OFDM_BRK = 3, |
236 | RTW89_CCK_BRK = 4, |
237 | RTW89_DL_MU_SPOOFING = 5, |
238 | RTW89_HE_MU = 6, |
239 | RTW89_VHT_MU = 7, |
240 | RTW89_UL_TB_SPOOFING = 8, |
241 | RTW89_RSVD_9 = 9, |
242 | RTW89_TRIG_BASE_PPDU = 10, |
243 | RTW89_CCK_PKT = 11, |
244 | RTW89_LEGACY_OFDM_PKT = 12, |
245 | RTW89_HT_PKT = 13, |
246 | RTW89_VHT_PKT = 14, |
247 | RTW89_HE_PKT = 15, |
248 | |
249 | RTW89_PHYSTS_BITMAP_NUM |
250 | }; |
251 | |
252 | enum rtw89_dig_gain_type { |
253 | RTW89_DIG_GAIN_LNA_G = 0, |
254 | RTW89_DIG_GAIN_TIA_G = 1, |
255 | RTW89_DIG_GAIN_LNA_A = 2, |
256 | RTW89_DIG_GAIN_TIA_A = 3, |
257 | RTW89_DIG_GAIN_MAX = 4 |
258 | }; |
259 | |
260 | enum rtw89_dig_gain_lna_idx { |
261 | RTW89_DIG_GAIN_LNA_IDX1 = 1, |
262 | RTW89_DIG_GAIN_LNA_IDX2 = 2, |
263 | RTW89_DIG_GAIN_LNA_IDX3 = 3, |
264 | RTW89_DIG_GAIN_LNA_IDX4 = 4, |
265 | RTW89_DIG_GAIN_LNA_IDX5 = 5, |
266 | RTW89_DIG_GAIN_LNA_IDX6 = 6 |
267 | }; |
268 | |
269 | enum rtw89_dig_gain_tia_idx { |
270 | RTW89_DIG_GAIN_TIA_IDX0 = 0, |
271 | RTW89_DIG_GAIN_TIA_IDX1 = 1 |
272 | }; |
273 | |
274 | enum rtw89_tssi_bandedge_cfg { |
275 | RTW89_TSSI_BANDEDGE_FLAT, |
276 | RTW89_TSSI_BANDEDGE_LOW, |
277 | RTW89_TSSI_BANDEDGE_MID, |
278 | RTW89_TSSI_BANDEDGE_HIGH, |
279 | |
280 | RTW89_TSSI_CFG_NUM, |
281 | }; |
282 | |
283 | enum rtw89_tssi_sbw_idx { |
284 | RTW89_TSSI_SBW20, |
285 | RTW89_TSSI_SBW40_0, |
286 | RTW89_TSSI_SBW40_1, |
287 | RTW89_TSSI_SBW80_0, |
288 | RTW89_TSSI_SBW80_1, |
289 | RTW89_TSSI_SBW80_2, |
290 | RTW89_TSSI_SBW80_3, |
291 | RTW89_TSSI_SBW160_0, |
292 | RTW89_TSSI_SBW160_1, |
293 | RTW89_TSSI_SBW160_2, |
294 | RTW89_TSSI_SBW160_3, |
295 | RTW89_TSSI_SBW160_4, |
296 | RTW89_TSSI_SBW160_5, |
297 | RTW89_TSSI_SBW160_6, |
298 | RTW89_TSSI_SBW160_7, |
299 | |
300 | RTW89_TSSI_SBW_NUM, |
301 | }; |
302 | |
303 | struct rtw89_txpwr_byrate_cfg { |
304 | enum rtw89_band band; |
305 | enum rtw89_nss nss; |
306 | enum rtw89_rate_section rs; |
307 | u8 shf; |
308 | u8 len; |
309 | u32 data; |
310 | }; |
311 | |
312 | struct rtw89_txpwr_track_cfg { |
313 | const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; |
314 | const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; |
315 | const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; |
316 | const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; |
317 | const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; |
318 | const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; |
319 | const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; |
320 | const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; |
321 | const s8 *delta_swingidx_2gb_n; |
322 | const s8 *delta_swingidx_2gb_p; |
323 | const s8 *delta_swingidx_2ga_n; |
324 | const s8 *delta_swingidx_2ga_p; |
325 | const s8 *delta_swingidx_2g_cck_b_n; |
326 | const s8 *delta_swingidx_2g_cck_b_p; |
327 | const s8 *delta_swingidx_2g_cck_a_n; |
328 | const s8 *delta_swingidx_2g_cck_a_p; |
329 | }; |
330 | |
331 | struct rtw89_phy_dig_gain_cfg { |
332 | const struct rtw89_reg_def *table; |
333 | u8 size; |
334 | }; |
335 | |
336 | struct rtw89_phy_dig_gain_table { |
337 | const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; |
338 | const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; |
339 | const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; |
340 | const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; |
341 | }; |
342 | |
343 | struct rtw89_phy_tssi_dbw_table { |
344 | u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; |
345 | }; |
346 | |
347 | struct rtw89_phy_reg3_tbl { |
348 | const struct rtw89_reg3_def *reg3; |
349 | int size; |
350 | }; |
351 | |
352 | #define DECLARE_PHY_REG3_TBL(_name) \ |
353 | const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ |
354 | .reg3 = _name, \ |
355 | .size = ARRAY_SIZE(_name), \ |
356 | } |
357 | |
358 | struct rtw89_nbi_reg_def { |
359 | struct rtw89_reg_def notch1_idx; |
360 | struct rtw89_reg_def notch1_frac_idx; |
361 | struct rtw89_reg_def notch1_en; |
362 | struct rtw89_reg_def notch2_idx; |
363 | struct rtw89_reg_def notch2_frac_idx; |
364 | struct rtw89_reg_def notch2_en; |
365 | }; |
366 | |
367 | struct rtw89_ccx_regs { |
368 | u32 setting_addr; |
369 | u32 edcca_opt_mask; |
370 | u32 measurement_trig_mask; |
371 | u32 trig_opt_mask; |
372 | u32 en_mask; |
373 | u32 ifs_cnt_addr; |
374 | u32 ifs_clm_period_mask; |
375 | u32 ifs_clm_cnt_unit_mask; |
376 | u32 ifs_clm_cnt_clear_mask; |
377 | u32 ifs_collect_en_mask; |
378 | u32 ifs_t1_addr; |
379 | u32 ifs_t1_th_h_mask; |
380 | u32 ifs_t1_en_mask; |
381 | u32 ifs_t1_th_l_mask; |
382 | u32 ifs_t2_addr; |
383 | u32 ifs_t2_th_h_mask; |
384 | u32 ifs_t2_en_mask; |
385 | u32 ifs_t2_th_l_mask; |
386 | u32 ifs_t3_addr; |
387 | u32 ifs_t3_th_h_mask; |
388 | u32 ifs_t3_en_mask; |
389 | u32 ifs_t3_th_l_mask; |
390 | u32 ifs_t4_addr; |
391 | u32 ifs_t4_th_h_mask; |
392 | u32 ifs_t4_en_mask; |
393 | u32 ifs_t4_th_l_mask; |
394 | u32 ifs_clm_tx_cnt_addr; |
395 | u32 ifs_clm_edcca_excl_cca_fa_mask; |
396 | u32 ifs_clm_tx_cnt_msk; |
397 | u32 ifs_clm_cca_addr; |
398 | u32 ifs_clm_ofdmcca_excl_fa_mask; |
399 | u32 ifs_clm_cckcca_excl_fa_mask; |
400 | u32 ifs_clm_fa_addr; |
401 | u32 ifs_clm_ofdm_fa_mask; |
402 | u32 ifs_clm_cck_fa_mask; |
403 | u32 ifs_his_addr; |
404 | u32 ifs_t4_his_mask; |
405 | u32 ifs_t3_his_mask; |
406 | u32 ifs_t2_his_mask; |
407 | u32 ifs_t1_his_mask; |
408 | u32 ifs_avg_l_addr; |
409 | u32 ifs_t2_avg_mask; |
410 | u32 ifs_t1_avg_mask; |
411 | u32 ifs_avg_h_addr; |
412 | u32 ifs_t4_avg_mask; |
413 | u32 ifs_t3_avg_mask; |
414 | u32 ifs_cca_l_addr; |
415 | u32 ifs_t2_cca_mask; |
416 | u32 ifs_t1_cca_mask; |
417 | u32 ifs_cca_h_addr; |
418 | u32 ifs_t4_cca_mask; |
419 | u32 ifs_t3_cca_mask; |
420 | u32 ifs_total_addr; |
421 | u32 ifs_cnt_done_mask; |
422 | u32 ifs_total_mask; |
423 | }; |
424 | |
425 | struct rtw89_physts_regs { |
426 | u32 setting_addr; |
427 | u32 dis_trigger_fail_mask; |
428 | u32 dis_trigger_brk_mask; |
429 | }; |
430 | |
431 | struct rtw89_cfo_regs { |
432 | u32 comp; |
433 | u32 weighting_mask; |
434 | u32 comp_seg0; |
435 | u32 valid_0_mask; |
436 | }; |
437 | |
438 | enum rtw89_bandwidth_section_num_ax { |
439 | RTW89_BW20_SEC_NUM_AX = 8, |
440 | RTW89_BW40_SEC_NUM_AX = 4, |
441 | RTW89_BW80_SEC_NUM_AX = 2, |
442 | }; |
443 | |
444 | enum rtw89_bandwidth_section_num_be { |
445 | RTW89_BW20_SEC_NUM_BE = 16, |
446 | RTW89_BW40_SEC_NUM_BE = 8, |
447 | RTW89_BW80_SEC_NUM_BE = 4, |
448 | RTW89_BW160_SEC_NUM_BE = 2, |
449 | }; |
450 | |
451 | #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40 |
452 | |
453 | struct rtw89_txpwr_limit_ax { |
454 | s8 cck_20m[RTW89_BF_NUM]; |
455 | s8 cck_40m[RTW89_BF_NUM]; |
456 | s8 ofdm[RTW89_BF_NUM]; |
457 | s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM]; |
458 | s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM]; |
459 | s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM]; |
460 | s8 mcs_160m[RTW89_BF_NUM]; |
461 | s8 mcs_40m_0p5[RTW89_BF_NUM]; |
462 | s8 mcs_40m_2p5[RTW89_BF_NUM]; |
463 | }; |
464 | |
465 | #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76 |
466 | |
467 | struct rtw89_txpwr_limit_be { |
468 | s8 cck_20m[RTW89_BF_NUM]; |
469 | s8 cck_40m[RTW89_BF_NUM]; |
470 | s8 ofdm[RTW89_BF_NUM]; |
471 | s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM]; |
472 | s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM]; |
473 | s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM]; |
474 | s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM]; |
475 | s8 mcs_320m[RTW89_BF_NUM]; |
476 | s8 mcs_40m_0p5[RTW89_BF_NUM]; |
477 | s8 mcs_40m_2p5[RTW89_BF_NUM]; |
478 | s8 mcs_40m_4p5[RTW89_BF_NUM]; |
479 | s8 mcs_40m_6p5[RTW89_BF_NUM]; |
480 | }; |
481 | |
482 | #define RTW89_RU_SEC_NUM_AX 8 |
483 | |
484 | #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24 |
485 | |
486 | struct rtw89_txpwr_limit_ru_ax { |
487 | s8 ru26[RTW89_RU_SEC_NUM_AX]; |
488 | s8 ru52[RTW89_RU_SEC_NUM_AX]; |
489 | s8 ru106[RTW89_RU_SEC_NUM_AX]; |
490 | }; |
491 | |
492 | #define RTW89_RU_SEC_NUM_BE 16 |
493 | |
494 | #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80 |
495 | |
496 | struct rtw89_txpwr_limit_ru_be { |
497 | s8 ru26[RTW89_RU_SEC_NUM_BE]; |
498 | s8 ru52[RTW89_RU_SEC_NUM_BE]; |
499 | s8 ru106[RTW89_RU_SEC_NUM_BE]; |
500 | s8 ru52_26[RTW89_RU_SEC_NUM_BE]; |
501 | s8 ru106_26[RTW89_RU_SEC_NUM_BE]; |
502 | }; |
503 | |
504 | struct rtw89_phy_rfk_log_fmt { |
505 | const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM]; |
506 | }; |
507 | |
508 | struct rtw89_phy_gen_def { |
509 | u32 cr_base; |
510 | const struct rtw89_ccx_regs *ccx; |
511 | const struct rtw89_physts_regs *physts; |
512 | const struct rtw89_cfo_regs *cfo; |
513 | u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); |
514 | void (*config_bb_gain)(struct rtw89_dev *rtwdev, |
515 | const struct rtw89_reg2_def *reg, |
516 | enum rtw89_rf_path rf_path, |
517 | void *); |
518 | void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev); |
519 | void (*bb_wrap_init)(struct rtw89_dev *rtwdev); |
520 | void (*ch_info_init)(struct rtw89_dev *rtwdev); |
521 | |
522 | void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev, |
523 | const struct rtw89_chan *chan, |
524 | enum rtw89_phy_idx phy_idx); |
525 | void (*set_txpwr_offset)(struct rtw89_dev *rtwdev, |
526 | const struct rtw89_chan *chan, |
527 | enum rtw89_phy_idx phy_idx); |
528 | void (*set_txpwr_limit)(struct rtw89_dev *rtwdev, |
529 | const struct rtw89_chan *chan, |
530 | enum rtw89_phy_idx phy_idx); |
531 | void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev, |
532 | const struct rtw89_chan *chan, |
533 | enum rtw89_phy_idx phy_idx); |
534 | }; |
535 | |
536 | extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; |
537 | extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; |
538 | |
539 | static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, |
540 | u32 addr, u8 data) |
541 | { |
542 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
543 | |
544 | rtw89_write8(rtwdev, addr: addr + phy->cr_base, data); |
545 | } |
546 | |
547 | static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, |
548 | u32 addr, u16 data) |
549 | { |
550 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
551 | |
552 | rtw89_write16(rtwdev, addr: addr + phy->cr_base, data); |
553 | } |
554 | |
555 | static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, |
556 | u32 addr, u32 data) |
557 | { |
558 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
559 | |
560 | rtw89_write32(rtwdev, addr: addr + phy->cr_base, data); |
561 | } |
562 | |
563 | static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, |
564 | u32 addr, u32 bits) |
565 | { |
566 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
567 | |
568 | rtw89_write32_set(rtwdev, addr: addr + phy->cr_base, bit: bits); |
569 | } |
570 | |
571 | static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, |
572 | u32 addr, u32 bits) |
573 | { |
574 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
575 | |
576 | rtw89_write32_clr(rtwdev, addr: addr + phy->cr_base, bit: bits); |
577 | } |
578 | |
579 | static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, |
580 | u32 addr, u32 mask, u32 data) |
581 | { |
582 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
583 | |
584 | rtw89_write32_mask(rtwdev, addr: addr + phy->cr_base, mask, data); |
585 | } |
586 | |
587 | static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) |
588 | { |
589 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
590 | |
591 | return rtw89_read8(rtwdev, addr: addr + phy->cr_base); |
592 | } |
593 | |
594 | static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) |
595 | { |
596 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
597 | |
598 | return rtw89_read16(rtwdev, addr: addr + phy->cr_base); |
599 | } |
600 | |
601 | static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) |
602 | { |
603 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
604 | |
605 | return rtw89_read32(rtwdev, addr: addr + phy->cr_base); |
606 | } |
607 | |
608 | static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, |
609 | u32 addr, u32 mask) |
610 | { |
611 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
612 | |
613 | return rtw89_read32_mask(rtwdev, addr: addr + phy->cr_base, mask); |
614 | } |
615 | |
616 | static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev, |
617 | u32 addr, u32 data, enum rtw89_phy_idx phy_idx) |
618 | { |
619 | if (phy_idx && addr < 0x10000) |
620 | addr += 0x20000; |
621 | |
622 | rtw89_write32(rtwdev, addr: addr + RTW89_BBMCU_ADDR_OFFSET, data); |
623 | } |
624 | |
625 | static inline |
626 | enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) |
627 | { |
628 | switch (subband) { |
629 | default: |
630 | case RTW89_CH_2G: |
631 | return RTW89_GAIN_OFFSET_2G_OFDM; |
632 | case RTW89_CH_5G_BAND_1: |
633 | return RTW89_GAIN_OFFSET_5G_LOW; |
634 | case RTW89_CH_5G_BAND_3: |
635 | return RTW89_GAIN_OFFSET_5G_MID; |
636 | case RTW89_CH_5G_BAND_4: |
637 | return RTW89_GAIN_OFFSET_5G_HIGH; |
638 | case RTW89_CH_6G_BAND_IDX0: |
639 | return RTW89_GAIN_OFFSET_6G_L0; |
640 | case RTW89_CH_6G_BAND_IDX1: |
641 | return RTW89_GAIN_OFFSET_6G_L1; |
642 | case RTW89_CH_6G_BAND_IDX2: |
643 | return RTW89_GAIN_OFFSET_6G_M0; |
644 | case RTW89_CH_6G_BAND_IDX3: |
645 | return RTW89_GAIN_OFFSET_6G_M1; |
646 | case RTW89_CH_6G_BAND_IDX4: |
647 | return RTW89_GAIN_OFFSET_6G_H0; |
648 | case RTW89_CH_6G_BAND_IDX5: |
649 | return RTW89_GAIN_OFFSET_6G_H1; |
650 | case RTW89_CH_6G_BAND_IDX6: |
651 | return RTW89_GAIN_OFFSET_6G_UH0; |
652 | case RTW89_CH_6G_BAND_IDX7: |
653 | return RTW89_GAIN_OFFSET_6G_UH1; |
654 | } |
655 | } |
656 | |
657 | static inline |
658 | enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) |
659 | { |
660 | switch (subband) { |
661 | default: |
662 | case RTW89_CH_2G: |
663 | return RTW89_BB_GAIN_BAND_2G; |
664 | case RTW89_CH_5G_BAND_1: |
665 | return RTW89_BB_GAIN_BAND_5G_L; |
666 | case RTW89_CH_5G_BAND_3: |
667 | return RTW89_BB_GAIN_BAND_5G_M; |
668 | case RTW89_CH_5G_BAND_4: |
669 | return RTW89_BB_GAIN_BAND_5G_H; |
670 | case RTW89_CH_6G_BAND_IDX0: |
671 | case RTW89_CH_6G_BAND_IDX1: |
672 | return RTW89_BB_GAIN_BAND_6G_L; |
673 | case RTW89_CH_6G_BAND_IDX2: |
674 | case RTW89_CH_6G_BAND_IDX3: |
675 | return RTW89_BB_GAIN_BAND_6G_M; |
676 | case RTW89_CH_6G_BAND_IDX4: |
677 | case RTW89_CH_6G_BAND_IDX5: |
678 | return RTW89_BB_GAIN_BAND_6G_H; |
679 | case RTW89_CH_6G_BAND_IDX6: |
680 | case RTW89_CH_6G_BAND_IDX7: |
681 | return RTW89_BB_GAIN_BAND_6G_UH; |
682 | } |
683 | } |
684 | |
685 | static inline |
686 | enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband) |
687 | { |
688 | switch (subband) { |
689 | default: |
690 | case RTW89_CH_2G: |
691 | return RTW89_BB_GAIN_BAND_2G_BE; |
692 | case RTW89_CH_5G_BAND_1: |
693 | return RTW89_BB_GAIN_BAND_5G_L_BE; |
694 | case RTW89_CH_5G_BAND_3: |
695 | return RTW89_BB_GAIN_BAND_5G_M_BE; |
696 | case RTW89_CH_5G_BAND_4: |
697 | return RTW89_BB_GAIN_BAND_5G_H_BE; |
698 | case RTW89_CH_6G_BAND_IDX0: |
699 | return RTW89_BB_GAIN_BAND_6G_L0_BE; |
700 | case RTW89_CH_6G_BAND_IDX1: |
701 | return RTW89_BB_GAIN_BAND_6G_L1_BE; |
702 | case RTW89_CH_6G_BAND_IDX2: |
703 | return RTW89_BB_GAIN_BAND_6G_M0_BE; |
704 | case RTW89_CH_6G_BAND_IDX3: |
705 | return RTW89_BB_GAIN_BAND_6G_M1_BE; |
706 | case RTW89_CH_6G_BAND_IDX4: |
707 | return RTW89_BB_GAIN_BAND_6G_H0_BE; |
708 | case RTW89_CH_6G_BAND_IDX5: |
709 | return RTW89_BB_GAIN_BAND_6G_H1_BE; |
710 | case RTW89_CH_6G_BAND_IDX6: |
711 | return RTW89_BB_GAIN_BAND_6G_UH0_BE; |
712 | case RTW89_CH_6G_BAND_IDX7: |
713 | return RTW89_BB_GAIN_BAND_6G_UH1_BE; |
714 | } |
715 | } |
716 | |
717 | enum rtw89_rfk_flag { |
718 | RTW89_RFK_F_WRF = 0, |
719 | RTW89_RFK_F_WM = 1, |
720 | RTW89_RFK_F_WS = 2, |
721 | RTW89_RFK_F_WC = 3, |
722 | RTW89_RFK_F_DELAY = 4, |
723 | RTW89_RFK_F_NUM, |
724 | }; |
725 | |
726 | struct rtw89_rfk_tbl { |
727 | const struct rtw89_reg5_def *defs; |
728 | u32 size; |
729 | }; |
730 | |
731 | #define RTW89_DECLARE_RFK_TBL(_name) \ |
732 | const struct rtw89_rfk_tbl _name ## _tbl = { \ |
733 | .defs = _name, \ |
734 | .size = ARRAY_SIZE(_name), \ |
735 | } |
736 | |
737 | #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ |
738 | {.flag = RTW89_RFK_F_WRF, \ |
739 | .path = _path, \ |
740 | .addr = _addr, \ |
741 | .mask = _mask, \ |
742 | .data = _data,} |
743 | |
744 | #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ |
745 | {.flag = RTW89_RFK_F_WM, \ |
746 | .addr = _addr, \ |
747 | .mask = _mask, \ |
748 | .data = _data,} |
749 | |
750 | #define RTW89_DECL_RFK_WS(_addr, _mask) \ |
751 | {.flag = RTW89_RFK_F_WS, \ |
752 | .addr = _addr, \ |
753 | .mask = _mask,} |
754 | |
755 | #define RTW89_DECL_RFK_WC(_addr, _mask) \ |
756 | {.flag = RTW89_RFK_F_WC, \ |
757 | .addr = _addr, \ |
758 | .mask = _mask,} |
759 | |
760 | #define RTW89_DECL_RFK_DELAY(_data) \ |
761 | {.flag = RTW89_RFK_F_DELAY, \ |
762 | .data = _data,} |
763 | |
764 | void |
765 | rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); |
766 | |
767 | #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ |
768 | do { \ |
769 | typeof(dev) __dev = (dev); \ |
770 | if (cond) \ |
771 | rtw89_rfk_parser(__dev, (tbl_t)); \ |
772 | else \ |
773 | rtw89_rfk_parser(__dev, (tbl_f)); \ |
774 | } while (0) |
775 | |
776 | void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, |
777 | const struct rtw89_phy_reg3_tbl *tbl); |
778 | u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, |
779 | const struct rtw89_chan *chan, |
780 | enum rtw89_bandwidth dbw); |
781 | u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, |
782 | enum rtw89_bandwidth dbw); |
783 | u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
784 | u32 addr, u32 mask); |
785 | u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
786 | u32 addr, u32 mask); |
787 | u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
788 | u32 addr, u32 mask); |
789 | bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
790 | u32 addr, u32 mask, u32 data); |
791 | bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
792 | u32 addr, u32 mask, u32 data); |
793 | bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, |
794 | u32 addr, u32 mask, u32 data); |
795 | void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); |
796 | void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); |
797 | void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, |
798 | const struct rtw89_reg2_def *reg, |
799 | enum rtw89_rf_path rf_path, |
800 | void *); |
801 | void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); |
802 | void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, |
803 | u32 data, enum rtw89_phy_idx phy_idx); |
804 | u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, |
805 | enum rtw89_phy_idx phy_idx); |
806 | s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, |
807 | struct rtw89_txpwr_byrate *head, |
808 | const struct rtw89_rate_desc *desc); |
809 | s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, |
810 | const struct rtw89_rate_desc *rate_desc); |
811 | void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, |
812 | const struct rtw89_txpwr_table *tbl); |
813 | s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, |
814 | u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); |
815 | s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, |
816 | u8 ru, u8 ntx, u8 ch); |
817 | |
818 | static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev) |
819 | { |
820 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
821 | |
822 | phy->preinit_rf_nctl(rtwdev); |
823 | } |
824 | |
825 | static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) |
826 | { |
827 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
828 | |
829 | if (phy->bb_wrap_init) |
830 | phy->bb_wrap_init(rtwdev); |
831 | } |
832 | |
833 | static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) |
834 | { |
835 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
836 | |
837 | if (phy->ch_info_init) |
838 | phy->ch_info_init(rtwdev); |
839 | } |
840 | |
841 | static inline |
842 | void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, |
843 | const struct rtw89_chan *chan, |
844 | enum rtw89_phy_idx phy_idx) |
845 | { |
846 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
847 | |
848 | phy->set_txpwr_byrate(rtwdev, chan, phy_idx); |
849 | } |
850 | |
851 | static inline |
852 | void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, |
853 | const struct rtw89_chan *chan, |
854 | enum rtw89_phy_idx phy_idx) |
855 | { |
856 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
857 | |
858 | phy->set_txpwr_offset(rtwdev, chan, phy_idx); |
859 | } |
860 | |
861 | static inline |
862 | void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, |
863 | const struct rtw89_chan *chan, |
864 | enum rtw89_phy_idx phy_idx) |
865 | { |
866 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
867 | |
868 | phy->set_txpwr_limit(rtwdev, chan, phy_idx); |
869 | } |
870 | |
871 | static inline |
872 | void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, |
873 | const struct rtw89_chan *chan, |
874 | enum rtw89_phy_idx phy_idx) |
875 | { |
876 | const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; |
877 | |
878 | phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx); |
879 | } |
880 | |
881 | void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); |
882 | void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); |
883 | void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, |
884 | u32 changed); |
885 | void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, |
886 | struct ieee80211_vif *vif, |
887 | const struct cfg80211_bitrate_mask *mask); |
888 | bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); |
889 | void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, |
890 | u32 len, u8 class, u8 func); |
891 | int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, |
892 | enum rtw89_phy_idx phy_idx, |
893 | unsigned int ms); |
894 | int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, |
895 | enum rtw89_phy_idx phy_idx, |
896 | enum rtw89_tssi_mode tssi_mode, |
897 | unsigned int ms); |
898 | int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, |
899 | enum rtw89_phy_idx phy_idx, |
900 | unsigned int ms); |
901 | int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, |
902 | enum rtw89_phy_idx phy_idx, |
903 | unsigned int ms); |
904 | int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, |
905 | enum rtw89_phy_idx phy_idx, |
906 | unsigned int ms); |
907 | int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, |
908 | enum rtw89_phy_idx phy_idx, |
909 | unsigned int ms); |
910 | int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, |
911 | enum rtw89_phy_idx phy_idx, |
912 | unsigned int ms); |
913 | void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, |
914 | enum rtw89_phy_idx phy, |
915 | const struct rtw89_chan *chan, |
916 | struct rtw89_h2c_rf_tssi *h2c); |
917 | void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, |
918 | enum rtw89_phy_idx phy, |
919 | const struct rtw89_chan *chan, |
920 | struct rtw89_h2c_rf_tssi *h2c); |
921 | void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); |
922 | void rtw89_phy_cfo_track_work(struct work_struct *work); |
923 | void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, |
924 | struct rtw89_rx_phy_ppdu *phy_ppdu); |
925 | void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); |
926 | void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); |
927 | void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, |
928 | u32 val); |
929 | void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); |
930 | void rtw89_phy_dig(struct rtw89_dev *rtwdev); |
931 | void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); |
932 | void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, |
933 | struct rtw89_rx_phy_ppdu *phy_ppdu); |
934 | void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); |
935 | void rtw89_phy_antdiv_work(struct work_struct *work); |
936 | void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); |
937 | void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, |
938 | enum rtw89_mac_idx mac_idx, |
939 | enum rtw89_tssi_bandedge_cfg bandedge_cfg); |
940 | void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); |
941 | void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); |
942 | u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); |
943 | void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, |
944 | u8 *ch, enum nl80211_band *band); |
945 | void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); |
946 | void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); |
947 | void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev); |
948 | enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, |
949 | enum rtw89_phy_idx phy_idx); |
950 | enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, |
951 | enum rtw89_phy_idx phy_idx); |
952 | |
953 | #endif |
954 | |