1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | ** DINO manager |
4 | ** |
5 | ** (c) Copyright 1999 Red Hat Software |
6 | ** (c) Copyright 1999 SuSE GmbH |
7 | ** (c) Copyright 1999,2000 Hewlett-Packard Company |
8 | ** (c) Copyright 2000 Grant Grundler |
9 | ** (c) Copyright 2006-2019 Helge Deller |
10 | ** |
11 | ** |
12 | ** This module provides access to Dino PCI bus (config/IOport spaces) |
13 | ** and helps manage Dino IRQ lines. |
14 | ** |
15 | ** Dino interrupt handling is a bit complicated. |
16 | ** Dino always writes to the broadcast EIR via irr0 for now. |
17 | ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) |
18 | ** Only one processor interrupt is used for the 11 IRQ line |
19 | ** inputs to dino. |
20 | ** |
21 | ** The different between Built-in Dino and Card-Mode |
22 | ** dino is in chip initialization and pci device initialization. |
23 | ** |
24 | ** Linux drivers can only use Card-Mode Dino if pci devices I/O port |
25 | ** BARs are configured and used by the driver. Programming MMIO address |
26 | ** requires substantial knowledge of available Host I/O address ranges |
27 | ** is currently not supported. Port/Config accessor functions are the |
28 | ** same. "BIOS" differences are handled within the existing routines. |
29 | */ |
30 | |
31 | /* Changes : |
32 | ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) |
33 | ** - added support for the integrated RS232. |
34 | */ |
35 | |
36 | /* |
37 | ** TODO: create a virtual address for each Dino HPA. |
38 | ** GSC code might be able to do this since IODC data tells us |
39 | ** how many pages are used. PCI subsystem could (must?) do this |
40 | ** for PCI drivers devices which implement/use MMIO registers. |
41 | */ |
42 | |
43 | #include <linux/delay.h> |
44 | #include <linux/types.h> |
45 | #include <linux/kernel.h> |
46 | #include <linux/pci.h> |
47 | #include <linux/init.h> |
48 | #include <linux/ioport.h> |
49 | #include <linux/slab.h> |
50 | #include <linux/interrupt.h> /* for struct irqaction */ |
51 | #include <linux/spinlock.h> /* for spinlock_t and prototypes */ |
52 | |
53 | #include <asm/pdc.h> |
54 | #include <asm/page.h> |
55 | #include <asm/io.h> |
56 | #include <asm/hardware.h> |
57 | |
58 | #include "gsc.h" |
59 | #include "iommu.h" |
60 | |
61 | #undef DINO_DEBUG |
62 | |
63 | #ifdef DINO_DEBUG |
64 | #define DBG(x...) printk(x) |
65 | #else |
66 | #define DBG(x...) |
67 | #endif |
68 | |
69 | /* |
70 | ** Config accessor functions only pass in the 8-bit bus number |
71 | ** and not the 8-bit "PCI Segment" number. Each Dino will be |
72 | ** assigned a PCI bus number based on "when" it's discovered. |
73 | ** |
74 | ** The "secondary" bus number is set to this before calling |
75 | ** pci_scan_bus(). If any PPB's are present, the scan will |
76 | ** discover them and update the "secondary" and "subordinate" |
77 | ** fields in Dino's pci_bus structure. |
78 | ** |
79 | ** Changes in the configuration *will* result in a different |
80 | ** bus number for each dino. |
81 | */ |
82 | |
83 | #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) |
84 | #define is_cujo(id) ((id)->hversion == 0x682) |
85 | |
86 | #define DINO_IAR0 0x004 |
87 | #define DINO_IODC_ADDR 0x008 |
88 | #define DINO_IODC_DATA_0 0x008 |
89 | #define DINO_IODC_DATA_1 0x008 |
90 | #define DINO_IRR0 0x00C |
91 | #define DINO_IAR1 0x010 |
92 | #define DINO_IRR1 0x014 |
93 | #define DINO_IMR 0x018 |
94 | #define DINO_IPR 0x01C |
95 | #define DINO_TOC_ADDR 0x020 |
96 | #define DINO_ICR 0x024 |
97 | #define DINO_ILR 0x028 |
98 | #define DINO_IO_COMMAND 0x030 |
99 | #define DINO_IO_STATUS 0x034 |
100 | #define DINO_IO_CONTROL 0x038 |
101 | #define DINO_IO_GSC_ERR_RESP 0x040 |
102 | #define DINO_IO_ERR_INFO 0x044 |
103 | #define DINO_IO_PCI_ERR_RESP 0x048 |
104 | #define DINO_IO_FBB_EN 0x05c |
105 | #define DINO_IO_ADDR_EN 0x060 |
106 | #define DINO_PCI_ADDR 0x064 |
107 | #define DINO_CONFIG_DATA 0x068 |
108 | #define DINO_IO_DATA 0x06c |
109 | #define DINO_MEM_DATA 0x070 /* Dino 3.x only */ |
110 | #define DINO_GSC2X_CONFIG 0x7b4 |
111 | #define DINO_GMASK 0x800 |
112 | #define DINO_PAMR 0x804 |
113 | #define DINO_PAPR 0x808 |
114 | #define DINO_DAMODE 0x80c |
115 | #define DINO_PCICMD 0x810 |
116 | #define DINO_PCISTS 0x814 |
117 | #define DINO_MLTIM 0x81c |
118 | #define DINO_BRDG_FEAT 0x820 |
119 | #define DINO_PCIROR 0x824 |
120 | #define DINO_PCIWOR 0x828 |
121 | #define DINO_TLTIM 0x830 |
122 | |
123 | #define DINO_IRQS 11 /* bits 0-10 are architected */ |
124 | #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ |
125 | #define DINO_LOCAL_IRQS (DINO_IRQS+1) |
126 | |
127 | #define DINO_MASK_IRQ(x) (1<<(x)) |
128 | |
129 | #define PCIINTA 0x001 |
130 | #define PCIINTB 0x002 |
131 | #define PCIINTC 0x004 |
132 | #define PCIINTD 0x008 |
133 | #define PCIINTE 0x010 |
134 | #define PCIINTF 0x020 |
135 | #define GSCEXTINT 0x040 |
136 | /* #define xxx 0x080 - bit 7 is "default" */ |
137 | /* #define xxx 0x100 - bit 8 not used */ |
138 | /* #define xxx 0x200 - bit 9 not used */ |
139 | #define RS232INT 0x400 |
140 | |
141 | struct dino_device |
142 | { |
143 | struct pci_hba_data hba; /* 'C' inheritance - must be first */ |
144 | spinlock_t dinosaur_pen; |
145 | u32 imr; /* IRQ's which are enabled */ |
146 | struct gsc_irq gsc_irq; |
147 | int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ |
148 | #ifdef DINO_DEBUG |
149 | unsigned int dino_irr0; /* save most recent IRQ line stat */ |
150 | #endif |
151 | }; |
152 | |
153 | static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba) |
154 | { |
155 | return container_of(hba, struct dino_device, hba); |
156 | } |
157 | |
158 | /* |
159 | * Dino Configuration Space Accessor Functions |
160 | */ |
161 | |
162 | #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) |
163 | |
164 | /* |
165 | * keep the current highest bus count to assist in allocating busses. This |
166 | * tries to keep a global bus count total so that when we discover an |
167 | * entirely new bus, it can be given a unique bus number. |
168 | */ |
169 | static int dino_current_bus = 0; |
170 | |
171 | static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, |
172 | int size, u32 *val) |
173 | { |
174 | struct dino_device *d = DINO_DEV(hba: parisc_walk_tree(dev: bus->bridge)); |
175 | u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; |
176 | u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); |
177 | void __iomem *base_addr = d->hba.base_addr; |
178 | unsigned long flags; |
179 | |
180 | DBG("%s: %p, %d, %d, %d\n" , __func__, base_addr, devfn, where, |
181 | size); |
182 | spin_lock_irqsave(&d->dinosaur_pen, flags); |
183 | |
184 | /* tell HW which CFG address */ |
185 | __raw_writel(val: v, addr: base_addr + DINO_PCI_ADDR); |
186 | |
187 | /* generate cfg read cycle */ |
188 | if (size == 1) { |
189 | *val = readb(addr: base_addr + DINO_CONFIG_DATA + (where & 3)); |
190 | } else if (size == 2) { |
191 | *val = readw(addr: base_addr + DINO_CONFIG_DATA + (where & 2)); |
192 | } else if (size == 4) { |
193 | *val = readl(addr: base_addr + DINO_CONFIG_DATA); |
194 | } |
195 | |
196 | spin_unlock_irqrestore(lock: &d->dinosaur_pen, flags); |
197 | return 0; |
198 | } |
199 | |
200 | /* |
201 | * Dino address stepping "feature": |
202 | * When address stepping, Dino attempts to drive the bus one cycle too soon |
203 | * even though the type of cycle (config vs. MMIO) might be different. |
204 | * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. |
205 | */ |
206 | static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, |
207 | int size, u32 val) |
208 | { |
209 | struct dino_device *d = DINO_DEV(hba: parisc_walk_tree(dev: bus->bridge)); |
210 | u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; |
211 | u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); |
212 | void __iomem *base_addr = d->hba.base_addr; |
213 | unsigned long flags; |
214 | |
215 | DBG("%s: %p, %d, %d, %d\n" , __func__, base_addr, devfn, where, |
216 | size); |
217 | spin_lock_irqsave(&d->dinosaur_pen, flags); |
218 | |
219 | /* avoid address stepping feature */ |
220 | __raw_writel(val: v & 0xffffff00, addr: base_addr + DINO_PCI_ADDR); |
221 | __raw_readl(addr: base_addr + DINO_CONFIG_DATA); |
222 | |
223 | /* tell HW which CFG address */ |
224 | __raw_writel(val: v, addr: base_addr + DINO_PCI_ADDR); |
225 | /* generate cfg read cycle */ |
226 | if (size == 1) { |
227 | writeb(val, addr: base_addr + DINO_CONFIG_DATA + (where & 3)); |
228 | } else if (size == 2) { |
229 | writew(val, addr: base_addr + DINO_CONFIG_DATA + (where & 2)); |
230 | } else if (size == 4) { |
231 | writel(val, addr: base_addr + DINO_CONFIG_DATA); |
232 | } |
233 | |
234 | spin_unlock_irqrestore(lock: &d->dinosaur_pen, flags); |
235 | return 0; |
236 | } |
237 | |
238 | static struct pci_ops dino_cfg_ops = { |
239 | .read = dino_cfg_read, |
240 | .write = dino_cfg_write, |
241 | }; |
242 | |
243 | |
244 | /* |
245 | * Dino "I/O Port" Space Accessor Functions |
246 | * |
247 | * Many PCI devices don't require use of I/O port space (eg Tulip, |
248 | * NCR720) since they export the same registers to both MMIO and |
249 | * I/O port space. Performance is going to stink if drivers use |
250 | * I/O port instead of MMIO. |
251 | */ |
252 | |
253 | #define DINO_PORT_IN(type, size, mask) \ |
254 | static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ |
255 | { \ |
256 | u##size v; \ |
257 | unsigned long flags; \ |
258 | spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
259 | /* tell HW which IO Port address */ \ |
260 | __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ |
261 | /* generate I/O PORT read cycle */ \ |
262 | v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ |
263 | spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
264 | return v; \ |
265 | } |
266 | |
267 | DINO_PORT_IN(b, 8, 3) |
268 | DINO_PORT_IN(w, 16, 2) |
269 | DINO_PORT_IN(l, 32, 0) |
270 | |
271 | #define DINO_PORT_OUT(type, size, mask) \ |
272 | static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ |
273 | { \ |
274 | unsigned long flags; \ |
275 | spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
276 | /* tell HW which IO port address */ \ |
277 | __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ |
278 | /* generate cfg write cycle */ \ |
279 | write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ |
280 | spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ |
281 | } |
282 | |
283 | DINO_PORT_OUT(b, 8, 3) |
284 | DINO_PORT_OUT(w, 16, 2) |
285 | DINO_PORT_OUT(l, 32, 0) |
286 | |
287 | static struct pci_port_ops dino_port_ops = { |
288 | .inb = dino_in8, |
289 | .inw = dino_in16, |
290 | .inl = dino_in32, |
291 | .outb = dino_out8, |
292 | .outw = dino_out16, |
293 | .outl = dino_out32 |
294 | }; |
295 | |
296 | static void dino_mask_irq(struct irq_data *d) |
297 | { |
298 | struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); |
299 | int local_irq = gsc_find_local_irq(irq: d->irq, global_irq: dino_dev->global_irq, DINO_LOCAL_IRQS); |
300 | |
301 | DBG(KERN_WARNING "%s(0x%px, %d)\n" , __func__, dino_dev, d->irq); |
302 | |
303 | /* Clear the matching bit in the IMR register */ |
304 | dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); |
305 | __raw_writel(val: dino_dev->imr, addr: dino_dev->hba.base_addr+DINO_IMR); |
306 | } |
307 | |
308 | static void dino_unmask_irq(struct irq_data *d) |
309 | { |
310 | struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); |
311 | int local_irq = gsc_find_local_irq(irq: d->irq, global_irq: dino_dev->global_irq, DINO_LOCAL_IRQS); |
312 | u32 tmp; |
313 | |
314 | DBG(KERN_WARNING "%s(0x%px, %d)\n" , __func__, dino_dev, d->irq); |
315 | |
316 | /* |
317 | ** clear pending IRQ bits |
318 | ** |
319 | ** This does NOT change ILR state! |
320 | ** See comment below for ILR usage. |
321 | */ |
322 | __raw_readl(addr: dino_dev->hba.base_addr+DINO_IPR); |
323 | |
324 | /* set the matching bit in the IMR register */ |
325 | dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ |
326 | __raw_writel( val: dino_dev->imr, addr: dino_dev->hba.base_addr+DINO_IMR); |
327 | |
328 | /* Emulate "Level Triggered" Interrupt |
329 | ** Basically, a driver is blowing it if the IRQ line is asserted |
330 | ** while the IRQ is disabled. But tulip.c seems to do that.... |
331 | ** Give 'em a kluge award and a nice round of applause! |
332 | ** |
333 | ** The gsc_write will generate an interrupt which invokes dino_isr(). |
334 | ** dino_isr() will read IPR and find nothing. But then catch this |
335 | ** when it also checks ILR. |
336 | */ |
337 | tmp = __raw_readl(addr: dino_dev->hba.base_addr+DINO_ILR); |
338 | if (tmp & DINO_MASK_IRQ(local_irq)) { |
339 | DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n" , |
340 | __func__, tmp); |
341 | gsc_writel(dino_dev->gsc_irq.txn_data, dino_dev->gsc_irq.txn_addr); |
342 | } |
343 | } |
344 | |
345 | #ifdef CONFIG_SMP |
346 | static int dino_set_affinity_irq(struct irq_data *d, const struct cpumask *dest, |
347 | bool force) |
348 | { |
349 | struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); |
350 | struct cpumask tmask; |
351 | int cpu_irq; |
352 | u32 eim; |
353 | |
354 | if (!cpumask_and(dstp: &tmask, src1p: dest, cpu_online_mask)) |
355 | return -EINVAL; |
356 | |
357 | cpu_irq = cpu_check_affinity(d, &tmask); |
358 | if (cpu_irq < 0) |
359 | return cpu_irq; |
360 | |
361 | dino_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq); |
362 | eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data; |
363 | __raw_writel(val: eim, addr: dino_dev->hba.base_addr+DINO_IAR0); |
364 | |
365 | irq_data_update_effective_affinity(d, &tmask); |
366 | |
367 | return IRQ_SET_MASK_OK; |
368 | } |
369 | #endif |
370 | |
371 | static struct irq_chip dino_interrupt_type = { |
372 | .name = "GSC-PCI" , |
373 | .irq_unmask = dino_unmask_irq, |
374 | .irq_mask = dino_mask_irq, |
375 | #ifdef CONFIG_SMP |
376 | .irq_set_affinity = dino_set_affinity_irq, |
377 | #endif |
378 | }; |
379 | |
380 | |
381 | /* |
382 | * Handle a Processor interrupt generated by Dino. |
383 | * |
384 | * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from |
385 | * wedging the CPU. Could be removed or made optional at some point. |
386 | */ |
387 | static irqreturn_t dino_isr(int irq, void *intr_dev) |
388 | { |
389 | struct dino_device *dino_dev = intr_dev; |
390 | u32 mask; |
391 | int ilr_loop = 100; |
392 | |
393 | /* read and acknowledge pending interrupts */ |
394 | #ifdef DINO_DEBUG |
395 | dino_dev->dino_irr0 = |
396 | #endif |
397 | mask = __raw_readl(addr: dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; |
398 | |
399 | if (mask == 0) |
400 | return IRQ_NONE; |
401 | |
402 | ilr_again: |
403 | do { |
404 | int local_irq = __ffs(mask); |
405 | int irq = dino_dev->global_irq[local_irq]; |
406 | DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n" , |
407 | __func__, irq, intr_dev, mask); |
408 | generic_handle_irq(irq); |
409 | mask &= ~DINO_MASK_IRQ(local_irq); |
410 | } while (mask); |
411 | |
412 | /* Support for level triggered IRQ lines. |
413 | ** |
414 | ** Dropping this support would make this routine *much* faster. |
415 | ** But since PCI requires level triggered IRQ line to share lines... |
416 | ** device drivers may assume lines are level triggered (and not |
417 | ** edge triggered like EISA/ISA can be). |
418 | */ |
419 | mask = __raw_readl(addr: dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; |
420 | if (mask) { |
421 | if (--ilr_loop > 0) |
422 | goto ilr_again; |
423 | pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n" , |
424 | dino_dev->hba.base_addr, mask); |
425 | } |
426 | return IRQ_HANDLED; |
427 | } |
428 | |
429 | static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) |
430 | { |
431 | int irq = gsc_assign_irq(type: &dino_interrupt_type, data: dino); |
432 | if (irq == NO_IRQ) |
433 | return; |
434 | |
435 | *irqp = irq; |
436 | dino->global_irq[local_irq] = irq; |
437 | } |
438 | |
439 | static void dino_choose_irq(struct parisc_device *dev, void *ctrl) |
440 | { |
441 | int irq; |
442 | struct dino_device *dino = ctrl; |
443 | |
444 | switch (dev->id.sversion) { |
445 | case 0x00084: irq = 8; break; /* PS/2 */ |
446 | case 0x0008c: irq = 10; break; /* RS232 */ |
447 | case 0x00096: irq = 8; break; /* PS/2 */ |
448 | default: return; /* Unknown */ |
449 | } |
450 | |
451 | dino_assign_irq(dino, local_irq: irq, irqp: &dev->irq); |
452 | } |
453 | |
454 | |
455 | /* |
456 | * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) |
457 | * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) |
458 | */ |
459 | static void quirk_cirrus_cardbus(struct pci_dev *dev) |
460 | { |
461 | u8 new_irq = dev->irq - 1; |
462 | printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n" , |
463 | pci_name(dev), dev->irq, new_irq); |
464 | dev->irq = new_irq; |
465 | } |
466 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); |
467 | |
468 | #ifdef CONFIG_TULIP |
469 | /* Check if PCI device is behind a Card-mode Dino. */ |
470 | static int pci_dev_is_behind_card_dino(struct pci_dev *dev) |
471 | { |
472 | struct dino_device *dino_dev; |
473 | |
474 | dino_dev = DINO_DEV(hba: parisc_walk_tree(dev: dev->bus->bridge)); |
475 | return is_card_dino(&dino_dev->hba.dev->id); |
476 | } |
477 | |
478 | static void pci_fixup_tulip(struct pci_dev *dev) |
479 | { |
480 | if (!pci_dev_is_behind_card_dino(dev)) |
481 | return; |
482 | if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) |
483 | return; |
484 | pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n" , |
485 | pci_name(dev)); |
486 | /* Disable this card by zeroing the PCI resources */ |
487 | memset(&dev->resource[0], 0, sizeof(dev->resource[0])); |
488 | memset(&dev->resource[1], 0, sizeof(dev->resource[1])); |
489 | } |
490 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip); |
491 | #endif /* CONFIG_TULIP */ |
492 | |
493 | static void __init |
494 | dino_bios_init(void) |
495 | { |
496 | DBG("dino_bios_init\n" ); |
497 | } |
498 | |
499 | /* |
500 | * dino_card_setup - Set up the memory space for a Dino in card mode. |
501 | * @bus: the bus under this dino |
502 | * |
503 | * Claim an 8MB chunk of unused IO space and call the generic PCI routines |
504 | * to set up the addresses of the devices on this bus. |
505 | */ |
506 | #define _8MB 0x00800000UL |
507 | static void __init |
508 | dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) |
509 | { |
510 | int i; |
511 | struct dino_device *dino_dev = DINO_DEV(hba: parisc_walk_tree(dev: bus->bridge)); |
512 | struct resource *res; |
513 | char name[128]; |
514 | int size; |
515 | |
516 | res = &dino_dev->hba.lmmio_space; |
517 | res->flags = IORESOURCE_MEM; |
518 | size = scnprintf(buf: name, size: sizeof(name), fmt: "Dino LMMIO (%s)" , |
519 | dev_name(dev: bus->bridge)); |
520 | res->name = kmalloc(size: size+1, GFP_KERNEL); |
521 | if(res->name) |
522 | strcpy(p: (char *)res->name, q: name); |
523 | else |
524 | res->name = dino_dev->hba.lmmio_space.name; |
525 | |
526 | |
527 | if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, |
528 | F_EXTEND(0xf0000000UL) | _8MB, |
529 | F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { |
530 | struct pci_dev *dev, *tmp; |
531 | |
532 | printk(KERN_ERR "Dino: cannot attach bus %s\n" , |
533 | dev_name(bus->bridge)); |
534 | /* kill the bus, we can't do anything with it */ |
535 | list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) { |
536 | list_del(entry: &dev->bus_list); |
537 | } |
538 | |
539 | return; |
540 | } |
541 | bus->resource[1] = res; |
542 | bus->resource[0] = &(dino_dev->hba.io_space); |
543 | |
544 | /* Now tell dino what range it has */ |
545 | for (i = 1; i < 31; i++) { |
546 | if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) |
547 | break; |
548 | } |
549 | DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n" , |
550 | i, res->start, base_addr + DINO_IO_ADDR_EN); |
551 | __raw_writel(val: 1 << i, addr: base_addr + DINO_IO_ADDR_EN); |
552 | } |
553 | |
554 | static void __init |
555 | dino_card_fixup(struct pci_dev *dev) |
556 | { |
557 | u32 irq_pin; |
558 | |
559 | /* |
560 | ** REVISIT: card-mode PCI-PCI expansion chassis do exist. |
561 | ** Not sure they were ever productized. |
562 | ** Die here since we'll die later in dino_inb() anyway. |
563 | */ |
564 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
565 | panic(fmt: "Card-Mode Dino: PCI-PCI Bridge not supported\n" ); |
566 | } |
567 | |
568 | /* |
569 | ** Set Latency Timer to 0xff (not a shared bus) |
570 | ** Set CACHELINE_SIZE. |
571 | */ |
572 | dino_cfg_write(bus: dev->bus, devfn: dev->devfn, |
573 | PCI_CACHE_LINE_SIZE, size: 2, val: 0xff00 | L1_CACHE_BYTES/4); |
574 | |
575 | /* |
576 | ** Program INT_LINE for card-mode devices. |
577 | ** The cards are hardwired according to this algorithm. |
578 | ** And it doesn't matter if PPB's are present or not since |
579 | ** the IRQ lines bypass the PPB. |
580 | ** |
581 | ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. |
582 | ** The additional "-1" adjusts for skewing the IRQ<->slot. |
583 | */ |
584 | dino_cfg_read(bus: dev->bus, devfn: dev->devfn, PCI_INTERRUPT_PIN, size: 1, val: &irq_pin); |
585 | dev->irq = pci_swizzle_interrupt_pin(dev, pin: irq_pin) - 1; |
586 | |
587 | /* Shouldn't really need to do this but it's in case someone tries |
588 | ** to bypass PCI services and look at the card themselves. |
589 | */ |
590 | dino_cfg_write(bus: dev->bus, devfn: dev->devfn, PCI_INTERRUPT_LINE, size: 1, val: dev->irq); |
591 | } |
592 | |
593 | /* The alignment contraints for PCI bridges under dino */ |
594 | #define DINO_BRIDGE_ALIGN 0x100000 |
595 | |
596 | |
597 | static void __init |
598 | dino_fixup_bus(struct pci_bus *bus) |
599 | { |
600 | struct pci_dev *dev; |
601 | struct dino_device *dino_dev = DINO_DEV(hba: parisc_walk_tree(dev: bus->bridge)); |
602 | |
603 | DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n" , |
604 | __func__, bus, bus->busn_res.start, |
605 | bus->bridge->platform_data); |
606 | |
607 | /* Firmware doesn't set up card-mode dino, so we have to */ |
608 | if (is_card_dino(&dino_dev->hba.dev->id)) { |
609 | dino_card_setup(bus, base_addr: dino_dev->hba.base_addr); |
610 | } else if (bus->parent) { |
611 | int i; |
612 | |
613 | pci_read_bridge_bases(child: bus); |
614 | |
615 | |
616 | for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
617 | if((bus->self->resource[i].flags & |
618 | (IORESOURCE_IO | IORESOURCE_MEM)) == 0) |
619 | continue; |
620 | |
621 | if(bus->self->resource[i].flags & IORESOURCE_MEM) { |
622 | /* There's a quirk to alignment of |
623 | * bridge memory resources: the start |
624 | * is the alignment and start-end is |
625 | * the size. However, firmware will |
626 | * have assigned start and end, so we |
627 | * need to take this into account */ |
628 | bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; |
629 | bus->self->resource[i].start = DINO_BRIDGE_ALIGN; |
630 | |
631 | } |
632 | |
633 | DBG("DEBUG %s assigning %d [%pR]\n" , |
634 | dev_name(&bus->self->dev), i, |
635 | &bus->self->resource[i]); |
636 | WARN_ON(pci_assign_resource(bus->self, i)); |
637 | DBG("DEBUG %s after assign %d [%pR]\n" , |
638 | dev_name(&bus->self->dev), i, |
639 | &bus->self->resource[i]); |
640 | } |
641 | } |
642 | |
643 | |
644 | list_for_each_entry(dev, &bus->devices, bus_list) { |
645 | if (is_card_dino(&dino_dev->hba.dev->id)) |
646 | dino_card_fixup(dev); |
647 | |
648 | /* |
649 | ** P2PB's only have 2 BARs, no IRQs. |
650 | ** I'd like to just ignore them for now. |
651 | */ |
652 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
653 | pcibios_init_bridge(dev); |
654 | continue; |
655 | } |
656 | |
657 | /* null out the ROM resource if there is one (we don't |
658 | * care about an expansion rom on parisc, since it |
659 | * usually contains (x86) bios code) */ |
660 | dev->resource[PCI_ROM_RESOURCE].flags = 0; |
661 | |
662 | if(dev->irq == 255) { |
663 | |
664 | #define DINO_FIX_UNASSIGNED_INTERRUPTS |
665 | #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS |
666 | |
667 | /* This code tries to assign an unassigned |
668 | * interrupt. Leave it disabled unless you |
669 | * *really* know what you're doing since the |
670 | * pin<->interrupt line mapping varies by bus |
671 | * and machine */ |
672 | |
673 | u32 irq_pin; |
674 | |
675 | dino_cfg_read(bus: dev->bus, devfn: dev->devfn, |
676 | PCI_INTERRUPT_PIN, size: 1, val: &irq_pin); |
677 | irq_pin = pci_swizzle_interrupt_pin(dev, pin: irq_pin) - 1; |
678 | printk(KERN_WARNING "Device %s has undefined IRQ, " |
679 | "setting to %d\n" , pci_name(dev), irq_pin); |
680 | dino_cfg_write(bus: dev->bus, devfn: dev->devfn, |
681 | PCI_INTERRUPT_LINE, size: 1, val: irq_pin); |
682 | dino_assign_irq(dino: dino_dev, local_irq: irq_pin, irqp: &dev->irq); |
683 | #else |
684 | dev->irq = 65535; |
685 | printk(KERN_WARNING "Device %s has unassigned IRQ\n" , pci_name(dev)); |
686 | #endif |
687 | } else { |
688 | /* Adjust INT_LINE for that busses region */ |
689 | dino_assign_irq(dino: dino_dev, local_irq: dev->irq, irqp: &dev->irq); |
690 | } |
691 | } |
692 | } |
693 | |
694 | |
695 | static struct pci_bios_ops dino_bios_ops = { |
696 | .init = dino_bios_init, |
697 | .fixup_bus = dino_fixup_bus |
698 | }; |
699 | |
700 | |
701 | /* |
702 | * Initialise a DINO controller chip |
703 | */ |
704 | static void __init |
705 | dino_card_init(struct dino_device *dino_dev) |
706 | { |
707 | u32 brdg_feat = 0x00784e05; |
708 | unsigned long status; |
709 | |
710 | status = __raw_readl(addr: dino_dev->hba.base_addr+DINO_IO_STATUS); |
711 | if (status & 0x0000ff80) { |
712 | __raw_writel(val: 0x00000005, |
713 | addr: dino_dev->hba.base_addr+DINO_IO_COMMAND); |
714 | udelay(1); |
715 | } |
716 | |
717 | __raw_writel(val: 0x00000000, addr: dino_dev->hba.base_addr+DINO_GMASK); |
718 | __raw_writel(val: 0x00000001, addr: dino_dev->hba.base_addr+DINO_IO_FBB_EN); |
719 | __raw_writel(val: 0x00000000, addr: dino_dev->hba.base_addr+DINO_ICR); |
720 | |
721 | #if 1 |
722 | /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ |
723 | /* |
724 | ** PCX-L processors don't support XQL like Dino wants it. |
725 | ** PCX-L2 ignore XQL signal and it doesn't matter. |
726 | */ |
727 | brdg_feat &= ~0x4; /* UXQL */ |
728 | #endif |
729 | __raw_writel( val: brdg_feat, addr: dino_dev->hba.base_addr+DINO_BRDG_FEAT); |
730 | |
731 | /* |
732 | ** Don't enable address decoding until we know which I/O range |
733 | ** currently is available from the host. Only affects MMIO |
734 | ** and not I/O port space. |
735 | */ |
736 | __raw_writel(val: 0x00000000, addr: dino_dev->hba.base_addr+DINO_IO_ADDR_EN); |
737 | |
738 | __raw_writel(val: 0x00000000, addr: dino_dev->hba.base_addr+DINO_DAMODE); |
739 | __raw_writel(val: 0x00222222, addr: dino_dev->hba.base_addr+DINO_PCIROR); |
740 | __raw_writel(val: 0x00222222, addr: dino_dev->hba.base_addr+DINO_PCIWOR); |
741 | |
742 | __raw_writel(val: 0x00000040, addr: dino_dev->hba.base_addr+DINO_MLTIM); |
743 | __raw_writel(val: 0x00000080, addr: dino_dev->hba.base_addr+DINO_IO_CONTROL); |
744 | __raw_writel(val: 0x0000008c, addr: dino_dev->hba.base_addr+DINO_TLTIM); |
745 | |
746 | /* Disable PAMR before writing PAPR */ |
747 | __raw_writel(val: 0x0000007e, addr: dino_dev->hba.base_addr+DINO_PAMR); |
748 | __raw_writel(val: 0x0000007f, addr: dino_dev->hba.base_addr+DINO_PAPR); |
749 | __raw_writel(val: 0x00000000, addr: dino_dev->hba.base_addr+DINO_PAMR); |
750 | |
751 | /* |
752 | ** Dino ERS encourages enabling FBB (0x6f). |
753 | ** We can't until we know *all* devices below us can support it. |
754 | ** (Something in device configuration header tells us). |
755 | */ |
756 | __raw_writel(val: 0x0000004f, addr: dino_dev->hba.base_addr+DINO_PCICMD); |
757 | |
758 | /* Somewhere, the PCI spec says give devices 1 second |
759 | ** to recover from the #RESET being de-asserted. |
760 | ** Experience shows most devices only need 10ms. |
761 | ** This short-cut speeds up booting significantly. |
762 | */ |
763 | mdelay(pci_post_reset_delay); |
764 | } |
765 | |
766 | static int __init |
767 | dino_bridge_init(struct dino_device *dino_dev, const char *name) |
768 | { |
769 | unsigned long io_addr; |
770 | int result, i, count=0; |
771 | struct resource *res, *prevres = NULL; |
772 | /* |
773 | * Decoding IO_ADDR_EN only works for Built-in Dino |
774 | * since PDC has already initialized this. |
775 | */ |
776 | |
777 | io_addr = __raw_readl(addr: dino_dev->hba.base_addr + DINO_IO_ADDR_EN); |
778 | if (io_addr == 0) { |
779 | printk(KERN_WARNING "%s: No PCI devices enabled.\n" , name); |
780 | return -ENODEV; |
781 | } |
782 | |
783 | res = &dino_dev->hba.lmmio_space; |
784 | for (i = 0; i < 32; i++) { |
785 | unsigned long start, end; |
786 | |
787 | if((io_addr & (1 << i)) == 0) |
788 | continue; |
789 | |
790 | start = F_EXTEND(0xf0000000UL) | (i << 23); |
791 | end = start + 8 * 1024 * 1024 - 1; |
792 | |
793 | DBG("DINO RANGE %d is at 0x%lx-0x%lx\n" , count, |
794 | start, end); |
795 | |
796 | if(prevres && prevres->end + 1 == start) { |
797 | prevres->end = end; |
798 | } else { |
799 | if(count >= DINO_MAX_LMMIO_RESOURCES) { |
800 | printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n" , name, count, start, end); |
801 | break; |
802 | } |
803 | prevres = res; |
804 | res->start = start; |
805 | res->end = end; |
806 | res->flags = IORESOURCE_MEM; |
807 | res->name = kmalloc(size: 64, GFP_KERNEL); |
808 | if(res->name) |
809 | snprintf(buf: (char *)res->name, size: 64, fmt: "%s LMMIO %d" , |
810 | name, count); |
811 | res++; |
812 | count++; |
813 | } |
814 | } |
815 | |
816 | res = &dino_dev->hba.lmmio_space; |
817 | |
818 | for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { |
819 | if(res[i].flags == 0) |
820 | break; |
821 | |
822 | result = ccio_request_resource(dino_dev->hba.dev, &res[i]); |
823 | if (result < 0) { |
824 | printk(KERN_ERR "%s: failed to claim PCI Bus address " |
825 | "space %d (%pR)!\n" , name, i, &res[i]); |
826 | return result; |
827 | } |
828 | } |
829 | return 0; |
830 | } |
831 | |
832 | static int __init dino_common_init(struct parisc_device *dev, |
833 | struct dino_device *dino_dev, const char *name) |
834 | { |
835 | int status; |
836 | u32 eim; |
837 | struct resource *res; |
838 | |
839 | pcibios_register_hba(&dino_dev->hba); |
840 | |
841 | pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ |
842 | pci_port = &dino_port_ops; |
843 | |
844 | /* |
845 | ** Note: SMP systems can make use of IRR1/IAR1 registers |
846 | ** But it won't buy much performance except in very |
847 | ** specific applications/configurations. Note Dino |
848 | ** still only has 11 IRQ input lines - just map some of them |
849 | ** to a different processor. |
850 | */ |
851 | dev->irq = gsc_alloc_irq(dev: &dino_dev->gsc_irq); |
852 | eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data; |
853 | |
854 | /* |
855 | ** Dino needs a PA "IRQ" to get a processor's attention. |
856 | ** arch/parisc/kernel/irq.c returns an EIRR bit. |
857 | */ |
858 | if (dev->irq < 0) { |
859 | printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n" , name); |
860 | return 1; |
861 | } |
862 | |
863 | status = request_irq(irq: dev->irq, handler: dino_isr, flags: 0, name, dev: dino_dev); |
864 | if (status) { |
865 | printk(KERN_WARNING "%s: request_irq() failed with %d\n" , |
866 | name, status); |
867 | return 1; |
868 | } |
869 | |
870 | /* Support the serial port which is sometimes attached on built-in |
871 | * Dino / Cujo chips. |
872 | */ |
873 | |
874 | gsc_fixup_irqs(parent: dev, ctrl: dino_dev, choose: dino_choose_irq); |
875 | |
876 | /* |
877 | ** This enables DINO to generate interrupts when it sees |
878 | ** any of its inputs *change*. Just asserting an IRQ |
879 | ** before it's enabled (ie unmasked) isn't good enough. |
880 | */ |
881 | __raw_writel(val: eim, addr: dino_dev->hba.base_addr+DINO_IAR0); |
882 | |
883 | /* |
884 | ** Some platforms don't clear Dino's IRR0 register at boot time. |
885 | ** Reading will clear it now. |
886 | */ |
887 | __raw_readl(addr: dino_dev->hba.base_addr+DINO_IRR0); |
888 | |
889 | /* allocate I/O Port resource region */ |
890 | res = &dino_dev->hba.io_space; |
891 | if (!is_cujo(&dev->id)) { |
892 | res->name = "Dino I/O Port" ; |
893 | } else { |
894 | res->name = "Cujo I/O Port" ; |
895 | } |
896 | res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); |
897 | res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); |
898 | res->flags = IORESOURCE_IO; /* do not mark it busy ! */ |
899 | if (request_resource(root: &ioport_resource, new: res) < 0) { |
900 | printk(KERN_ERR "%s: request I/O Port region failed " |
901 | "0x%lx/%lx (hpa 0x%px)\n" , |
902 | name, (unsigned long)res->start, (unsigned long)res->end, |
903 | dino_dev->hba.base_addr); |
904 | return 1; |
905 | } |
906 | |
907 | return 0; |
908 | } |
909 | |
910 | #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) |
911 | #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) |
912 | #define CUJO_RAVEN_BADPAGE 0x01003000UL |
913 | #define CUJO_FIREHAWK_BADPAGE 0x01607000UL |
914 | |
915 | static const char dino_vers[][4] = { |
916 | "2.0" , |
917 | "2.1" , |
918 | "3.0" , |
919 | "3.1" |
920 | }; |
921 | |
922 | static const char cujo_vers[][4] = { |
923 | "1.0" , |
924 | "2.0" |
925 | }; |
926 | |
927 | /* |
928 | ** Determine if dino should claim this chip (return 0) or not (return 1). |
929 | ** If so, initialize the chip appropriately (card-mode vs bridge mode). |
930 | ** Much of the initialization is common though. |
931 | */ |
932 | static int __init dino_probe(struct parisc_device *dev) |
933 | { |
934 | struct dino_device *dino_dev; // Dino specific control struct |
935 | const char *version = "unknown" ; |
936 | char *name; |
937 | int is_cujo = 0; |
938 | LIST_HEAD(resources); |
939 | struct pci_bus *bus; |
940 | unsigned long hpa = dev->hpa.start; |
941 | int max; |
942 | |
943 | name = "Dino" ; |
944 | if (is_card_dino(&dev->id)) { |
945 | version = "3.x (card mode)" ; |
946 | } else { |
947 | if (!is_cujo(&dev->id)) { |
948 | if (dev->id.hversion_rev < 4) { |
949 | version = dino_vers[dev->id.hversion_rev]; |
950 | } |
951 | } else { |
952 | name = "Cujo" ; |
953 | is_cujo = 1; |
954 | if (dev->id.hversion_rev < 2) { |
955 | version = cujo_vers[dev->id.hversion_rev]; |
956 | } |
957 | } |
958 | } |
959 | |
960 | printk("%s version %s found at 0x%lx\n" , name, version, hpa); |
961 | |
962 | if (!request_mem_region(hpa, PAGE_SIZE, name)) { |
963 | printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n" , |
964 | hpa); |
965 | return 1; |
966 | } |
967 | |
968 | /* Check for bugs */ |
969 | if (is_cujo && dev->id.hversion_rev == 1) { |
970 | #ifdef CONFIG_IOMMU_CCIO |
971 | printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n" ); |
972 | if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { |
973 | ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); |
974 | } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { |
975 | ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); |
976 | } else { |
977 | printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n" , hpa); |
978 | } |
979 | #endif |
980 | } else if (!is_cujo && !is_card_dino(&dev->id) && |
981 | dev->id.hversion_rev < 3) { |
982 | printk(KERN_WARNING |
983 | "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" |
984 | "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" |
985 | "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" |
986 | "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n" , |
987 | dev->id.hversion_rev); |
988 | /* REVISIT: why are C200/C240 listed in the README table but not |
989 | ** "Models affected"? Could be an omission in the original literature. |
990 | */ |
991 | } |
992 | |
993 | dino_dev = kzalloc(size: sizeof(struct dino_device), GFP_KERNEL); |
994 | if (!dino_dev) { |
995 | printk("dino_init_chip - couldn't alloc dino_device\n" ); |
996 | return 1; |
997 | } |
998 | |
999 | dino_dev->hba.dev = dev; |
1000 | dino_dev->hba.base_addr = ioremap(offset: hpa, size: 4096); |
1001 | dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND; |
1002 | spin_lock_init(&dino_dev->dinosaur_pen); |
1003 | dino_dev->hba.iommu = ccio_get_iommu(dev); |
1004 | |
1005 | if (is_card_dino(&dev->id)) { |
1006 | dino_card_init(dino_dev); |
1007 | } else { |
1008 | dino_bridge_init(dino_dev, name); |
1009 | } |
1010 | |
1011 | if (dino_common_init(dev, dino_dev, name)) |
1012 | return 1; |
1013 | |
1014 | dev->dev.platform_data = dino_dev; |
1015 | |
1016 | pci_add_resource_offset(resources: &resources, res: &dino_dev->hba.io_space, |
1017 | offset: HBA_PORT_BASE(dino_dev->hba.hba_num)); |
1018 | if (dino_dev->hba.lmmio_space.flags) |
1019 | pci_add_resource_offset(resources: &resources, res: &dino_dev->hba.lmmio_space, |
1020 | offset: dino_dev->hba.lmmio_space_offset); |
1021 | if (dino_dev->hba.elmmio_space.flags) |
1022 | pci_add_resource_offset(resources: &resources, res: &dino_dev->hba.elmmio_space, |
1023 | offset: dino_dev->hba.lmmio_space_offset); |
1024 | if (dino_dev->hba.gmmio_space.flags) |
1025 | pci_add_resource(resources: &resources, res: &dino_dev->hba.gmmio_space); |
1026 | |
1027 | dino_dev->hba.bus_num.start = dino_current_bus; |
1028 | dino_dev->hba.bus_num.end = 255; |
1029 | dino_dev->hba.bus_num.flags = IORESOURCE_BUS; |
1030 | pci_add_resource(resources: &resources, res: &dino_dev->hba.bus_num); |
1031 | /* |
1032 | ** It's not used to avoid chicken/egg problems |
1033 | ** with configuration accessor functions. |
1034 | */ |
1035 | dino_dev->hba.hba_bus = bus = pci_create_root_bus(parent: &dev->dev, |
1036 | bus: dino_current_bus, ops: &dino_cfg_ops, NULL, resources: &resources); |
1037 | if (!bus) { |
1038 | printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n" , |
1039 | dev_name(&dev->dev), dino_current_bus); |
1040 | pci_free_resource_list(resources: &resources); |
1041 | /* increment the bus number in case of duplicates */ |
1042 | dino_current_bus++; |
1043 | return 0; |
1044 | } |
1045 | |
1046 | max = pci_scan_child_bus(bus); |
1047 | pci_bus_update_busn_res_end(b: bus, busmax: max); |
1048 | |
1049 | /* This code *depends* on scanning being single threaded |
1050 | * if it isn't, this global bus number count will fail |
1051 | */ |
1052 | dino_current_bus = max + 1; |
1053 | pci_bus_assign_resources(bus); |
1054 | pci_bus_add_devices(bus); |
1055 | return 0; |
1056 | } |
1057 | |
1058 | /* |
1059 | * Normally, we would just test sversion. But the Elroy PCI adapter has |
1060 | * the same sversion as Dino, so we have to check hversion as well. |
1061 | * Unfortunately, the J2240 PDC reports the wrong hversion for the first |
1062 | * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. |
1063 | * For card-mode Dino, most machines report an sversion of 9D. But 715 |
1064 | * and 725 firmware misreport it as 0x08080 for no adequately explained |
1065 | * reason. |
1066 | */ |
1067 | static const struct parisc_device_id dino_tbl[] __initconst = { |
1068 | { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ |
1069 | { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ |
1070 | { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ |
1071 | { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ |
1072 | { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ |
1073 | { 0, } |
1074 | }; |
1075 | |
1076 | static struct parisc_driver dino_driver __refdata = { |
1077 | .name = "dino" , |
1078 | .id_table = dino_tbl, |
1079 | .probe = dino_probe, |
1080 | }; |
1081 | |
1082 | /* |
1083 | * One time initialization to let the world know Dino is here. |
1084 | * This is the only routine which is NOT static. |
1085 | * Must be called exactly once before pci_init(). |
1086 | */ |
1087 | static int __init dino_init(void) |
1088 | { |
1089 | return register_parisc_driver(&dino_driver); |
1090 | } |
1091 | arch_initcall(dino_init); |
1092 | |