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1/*
2** DINO manager
3**
4** (c) Copyright 1999 Red Hat Software
5** (c) Copyright 1999 SuSE GmbH
6** (c) Copyright 1999,2000 Hewlett-Packard Company
7** (c) Copyright 2000 Grant Grundler
8** (c) Copyright 2006 Helge Deller
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15** This module provides access to Dino PCI bus (config/IOport spaces)
16** and helps manage Dino IRQ lines.
17**
18** Dino interrupt handling is a bit complicated.
19** Dino always writes to the broadcast EIR via irr0 for now.
20** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
21** Only one processor interrupt is used for the 11 IRQ line
22** inputs to dino.
23**
24** The different between Built-in Dino and Card-Mode
25** dino is in chip initialization and pci device initialization.
26**
27** Linux drivers can only use Card-Mode Dino if pci devices I/O port
28** BARs are configured and used by the driver. Programming MMIO address
29** requires substantial knowledge of available Host I/O address ranges
30** is currently not supported. Port/Config accessor functions are the
31** same. "BIOS" differences are handled within the existing routines.
32*/
33
34/* Changes :
35** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
36** - added support for the integrated RS232.
37*/
38
39/*
40** TODO: create a virtual address for each Dino HPA.
41** GSC code might be able to do this since IODC data tells us
42** how many pages are used. PCI subsystem could (must?) do this
43** for PCI drivers devices which implement/use MMIO registers.
44*/
45
46#include <linux/delay.h>
47#include <linux/types.h>
48#include <linux/kernel.h>
49#include <linux/pci.h>
50#include <linux/init.h>
51#include <linux/ioport.h>
52#include <linux/slab.h>
53#include <linux/interrupt.h> /* for struct irqaction */
54#include <linux/spinlock.h> /* for spinlock_t and prototypes */
55
56#include <asm/pdc.h>
57#include <asm/page.h>
58#include <asm/io.h>
59#include <asm/hardware.h>
60
61#include "gsc.h"
62#include "iommu.h"
63
64#undef DINO_DEBUG
65
66#ifdef DINO_DEBUG
67#define DBG(x...) printk(x)
68#else
69#define DBG(x...)
70#endif
71
72/*
73** Config accessor functions only pass in the 8-bit bus number
74** and not the 8-bit "PCI Segment" number. Each Dino will be
75** assigned a PCI bus number based on "when" it's discovered.
76**
77** The "secondary" bus number is set to this before calling
78** pci_scan_bus(). If any PPB's are present, the scan will
79** discover them and update the "secondary" and "subordinate"
80** fields in Dino's pci_bus structure.
81**
82** Changes in the configuration *will* result in a different
83** bus number for each dino.
84*/
85
86#define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
87#define is_cujo(id) ((id)->hversion == 0x682)
88
89#define DINO_IAR0 0x004
90#define DINO_IODC_ADDR 0x008
91#define DINO_IODC_DATA_0 0x008
92#define DINO_IODC_DATA_1 0x008
93#define DINO_IRR0 0x00C
94#define DINO_IAR1 0x010
95#define DINO_IRR1 0x014
96#define DINO_IMR 0x018
97#define DINO_IPR 0x01C
98#define DINO_TOC_ADDR 0x020
99#define DINO_ICR 0x024
100#define DINO_ILR 0x028
101#define DINO_IO_COMMAND 0x030
102#define DINO_IO_STATUS 0x034
103#define DINO_IO_CONTROL 0x038
104#define DINO_IO_GSC_ERR_RESP 0x040
105#define DINO_IO_ERR_INFO 0x044
106#define DINO_IO_PCI_ERR_RESP 0x048
107#define DINO_IO_FBB_EN 0x05c
108#define DINO_IO_ADDR_EN 0x060
109#define DINO_PCI_ADDR 0x064
110#define DINO_CONFIG_DATA 0x068
111#define DINO_IO_DATA 0x06c
112#define DINO_MEM_DATA 0x070 /* Dino 3.x only */
113#define DINO_GSC2X_CONFIG 0x7b4
114#define DINO_GMASK 0x800
115#define DINO_PAMR 0x804
116#define DINO_PAPR 0x808
117#define DINO_DAMODE 0x80c
118#define DINO_PCICMD 0x810
119#define DINO_PCISTS 0x814
120#define DINO_MLTIM 0x81c
121#define DINO_BRDG_FEAT 0x820
122#define DINO_PCIROR 0x824
123#define DINO_PCIWOR 0x828
124#define DINO_TLTIM 0x830
125
126#define DINO_IRQS 11 /* bits 0-10 are architected */
127#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
128#define DINO_LOCAL_IRQS (DINO_IRQS+1)
129
130#define DINO_MASK_IRQ(x) (1<<(x))
131
132#define PCIINTA 0x001
133#define PCIINTB 0x002
134#define PCIINTC 0x004
135#define PCIINTD 0x008
136#define PCIINTE 0x010
137#define PCIINTF 0x020
138#define GSCEXTINT 0x040
139/* #define xxx 0x080 - bit 7 is "default" */
140/* #define xxx 0x100 - bit 8 not used */
141/* #define xxx 0x200 - bit 9 not used */
142#define RS232INT 0x400
143
144struct dino_device
145{
146 struct pci_hba_data hba; /* 'C' inheritance - must be first */
147 spinlock_t dinosaur_pen;
148 unsigned long txn_addr; /* EIR addr to generate interrupt */
149 u32 txn_data; /* EIR data assign to each dino */
150 u32 imr; /* IRQ's which are enabled */
151 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
152#ifdef DINO_DEBUG
153 unsigned int dino_irr0; /* save most recent IRQ line stat */
154#endif
155};
156
157static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba)
158{
159 return container_of(hba, struct dino_device, hba);
160}
161
162/*
163 * Dino Configuration Space Accessor Functions
164 */
165
166#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
167
168/*
169 * keep the current highest bus count to assist in allocating busses. This
170 * tries to keep a global bus count total so that when we discover an
171 * entirely new bus, it can be given a unique bus number.
172 */
173static int dino_current_bus = 0;
174
175static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
176 int size, u32 *val)
177{
178 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
179 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
180 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
181 void __iomem *base_addr = d->hba.base_addr;
182 unsigned long flags;
183
184 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
185 size);
186 spin_lock_irqsave(&d->dinosaur_pen, flags);
187
188 /* tell HW which CFG address */
189 __raw_writel(v, base_addr + DINO_PCI_ADDR);
190
191 /* generate cfg read cycle */
192 if (size == 1) {
193 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
194 } else if (size == 2) {
195 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
196 } else if (size == 4) {
197 *val = readl(base_addr + DINO_CONFIG_DATA);
198 }
199
200 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
201 return 0;
202}
203
204/*
205 * Dino address stepping "feature":
206 * When address stepping, Dino attempts to drive the bus one cycle too soon
207 * even though the type of cycle (config vs. MMIO) might be different.
208 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
209 */
210static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
211 int size, u32 val)
212{
213 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
214 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
215 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
216 void __iomem *base_addr = d->hba.base_addr;
217 unsigned long flags;
218
219 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
220 size);
221 spin_lock_irqsave(&d->dinosaur_pen, flags);
222
223 /* avoid address stepping feature */
224 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
225 __raw_readl(base_addr + DINO_CONFIG_DATA);
226
227 /* tell HW which CFG address */
228 __raw_writel(v, base_addr + DINO_PCI_ADDR);
229 /* generate cfg read cycle */
230 if (size == 1) {
231 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
232 } else if (size == 2) {
233 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
234 } else if (size == 4) {
235 writel(val, base_addr + DINO_CONFIG_DATA);
236 }
237
238 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
239 return 0;
240}
241
242static struct pci_ops dino_cfg_ops = {
243 .read = dino_cfg_read,
244 .write = dino_cfg_write,
245};
246
247
248/*
249 * Dino "I/O Port" Space Accessor Functions
250 *
251 * Many PCI devices don't require use of I/O port space (eg Tulip,
252 * NCR720) since they export the same registers to both MMIO and
253 * I/O port space. Performance is going to stink if drivers use
254 * I/O port instead of MMIO.
255 */
256
257#define DINO_PORT_IN(type, size, mask) \
258static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
259{ \
260 u##size v; \
261 unsigned long flags; \
262 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
263 /* tell HW which IO Port address */ \
264 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
265 /* generate I/O PORT read cycle */ \
266 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
267 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
268 return v; \
269}
270
271DINO_PORT_IN(b, 8, 3)
272DINO_PORT_IN(w, 16, 2)
273DINO_PORT_IN(l, 32, 0)
274
275#define DINO_PORT_OUT(type, size, mask) \
276static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
277{ \
278 unsigned long flags; \
279 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
280 /* tell HW which IO port address */ \
281 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
282 /* generate cfg write cycle */ \
283 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
284 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
285}
286
287DINO_PORT_OUT(b, 8, 3)
288DINO_PORT_OUT(w, 16, 2)
289DINO_PORT_OUT(l, 32, 0)
290
291static struct pci_port_ops dino_port_ops = {
292 .inb = dino_in8,
293 .inw = dino_in16,
294 .inl = dino_in32,
295 .outb = dino_out8,
296 .outw = dino_out16,
297 .outl = dino_out32
298};
299
300static void dino_mask_irq(struct irq_data *d)
301{
302 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
303 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
304
305 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
306
307 /* Clear the matching bit in the IMR register */
308 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
309 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
310}
311
312static void dino_unmask_irq(struct irq_data *d)
313{
314 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
315 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
316 u32 tmp;
317
318 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
319
320 /*
321 ** clear pending IRQ bits
322 **
323 ** This does NOT change ILR state!
324 ** See comment below for ILR usage.
325 */
326 __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
327
328 /* set the matching bit in the IMR register */
329 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */
330 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
331
332 /* Emulate "Level Triggered" Interrupt
333 ** Basically, a driver is blowing it if the IRQ line is asserted
334 ** while the IRQ is disabled. But tulip.c seems to do that....
335 ** Give 'em a kluge award and a nice round of applause!
336 **
337 ** The gsc_write will generate an interrupt which invokes dino_isr().
338 ** dino_isr() will read IPR and find nothing. But then catch this
339 ** when it also checks ILR.
340 */
341 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
342 if (tmp & DINO_MASK_IRQ(local_irq)) {
343 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
344 __func__, tmp);
345 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
346 }
347}
348
349static struct irq_chip dino_interrupt_type = {
350 .name = "GSC-PCI",
351 .irq_unmask = dino_unmask_irq,
352 .irq_mask = dino_mask_irq,
353};
354
355
356/*
357 * Handle a Processor interrupt generated by Dino.
358 *
359 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
360 * wedging the CPU. Could be removed or made optional at some point.
361 */
362static irqreturn_t dino_isr(int irq, void *intr_dev)
363{
364 struct dino_device *dino_dev = intr_dev;
365 u32 mask;
366 int ilr_loop = 100;
367
368 /* read and acknowledge pending interrupts */
369#ifdef DINO_DEBUG
370 dino_dev->dino_irr0 =
371#endif
372 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
373
374 if (mask == 0)
375 return IRQ_NONE;
376
377ilr_again:
378 do {
379 int local_irq = __ffs(mask);
380 int irq = dino_dev->global_irq[local_irq];
381 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
382 __func__, irq, intr_dev, mask);
383 generic_handle_irq(irq);
384 mask &= ~DINO_MASK_IRQ(local_irq);
385 } while (mask);
386
387 /* Support for level triggered IRQ lines.
388 **
389 ** Dropping this support would make this routine *much* faster.
390 ** But since PCI requires level triggered IRQ line to share lines...
391 ** device drivers may assume lines are level triggered (and not
392 ** edge triggered like EISA/ISA can be).
393 */
394 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
395 if (mask) {
396 if (--ilr_loop > 0)
397 goto ilr_again;
398 pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n",
399 dino_dev->hba.base_addr, mask);
400 }
401 return IRQ_HANDLED;
402}
403
404static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
405{
406 int irq = gsc_assign_irq(&dino_interrupt_type, dino);
407 if (irq == NO_IRQ)
408 return;
409
410 *irqp = irq;
411 dino->global_irq[local_irq] = irq;
412}
413
414static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
415{
416 int irq;
417 struct dino_device *dino = ctrl;
418
419 switch (dev->id.sversion) {
420 case 0x00084: irq = 8; break; /* PS/2 */
421 case 0x0008c: irq = 10; break; /* RS232 */
422 case 0x00096: irq = 8; break; /* PS/2 */
423 default: return; /* Unknown */
424 }
425
426 dino_assign_irq(dino, irq, &dev->irq);
427}
428
429
430/*
431 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
432 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
433 */
434static void quirk_cirrus_cardbus(struct pci_dev *dev)
435{
436 u8 new_irq = dev->irq - 1;
437 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
438 pci_name(dev), dev->irq, new_irq);
439 dev->irq = new_irq;
440}
441DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
442
443
444static void __init
445dino_bios_init(void)
446{
447 DBG("dino_bios_init\n");
448}
449
450/*
451 * dino_card_setup - Set up the memory space for a Dino in card mode.
452 * @bus: the bus under this dino
453 *
454 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
455 * to set up the addresses of the devices on this bus.
456 */
457#define _8MB 0x00800000UL
458static void __init
459dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
460{
461 int i;
462 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
463 struct resource *res;
464 char name[128];
465 int size;
466
467 res = &dino_dev->hba.lmmio_space;
468 res->flags = IORESOURCE_MEM;
469 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
470 dev_name(bus->bridge));
471 res->name = kmalloc(size+1, GFP_KERNEL);
472 if(res->name)
473 strcpy((char *)res->name, name);
474 else
475 res->name = dino_dev->hba.lmmio_space.name;
476
477
478 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
479 F_EXTEND(0xf0000000UL) | _8MB,
480 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
481 struct pci_dev *dev, *tmp;
482
483 printk(KERN_ERR "Dino: cannot attach bus %s\n",
484 dev_name(bus->bridge));
485 /* kill the bus, we can't do anything with it */
486 list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
487 list_del(&dev->bus_list);
488 }
489
490 return;
491 }
492 bus->resource[1] = res;
493 bus->resource[0] = &(dino_dev->hba.io_space);
494
495 /* Now tell dino what range it has */
496 for (i = 1; i < 31; i++) {
497 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
498 break;
499 }
500 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
501 i, res->start, base_addr + DINO_IO_ADDR_EN);
502 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
503}
504
505static void __init
506dino_card_fixup(struct pci_dev *dev)
507{
508 u32 irq_pin;
509
510 /*
511 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
512 ** Not sure they were ever productized.
513 ** Die here since we'll die later in dino_inb() anyway.
514 */
515 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
516 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
517 }
518
519 /*
520 ** Set Latency Timer to 0xff (not a shared bus)
521 ** Set CACHELINE_SIZE.
522 */
523 dino_cfg_write(dev->bus, dev->devfn,
524 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
525
526 /*
527 ** Program INT_LINE for card-mode devices.
528 ** The cards are hardwired according to this algorithm.
529 ** And it doesn't matter if PPB's are present or not since
530 ** the IRQ lines bypass the PPB.
531 **
532 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
533 ** The additional "-1" adjusts for skewing the IRQ<->slot.
534 */
535 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
536 dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
537
538 /* Shouldn't really need to do this but it's in case someone tries
539 ** to bypass PCI services and look at the card themselves.
540 */
541 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
542}
543
544/* The alignment contraints for PCI bridges under dino */
545#define DINO_BRIDGE_ALIGN 0x100000
546
547
548static void __init
549dino_fixup_bus(struct pci_bus *bus)
550{
551 struct pci_dev *dev;
552 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
553
554 DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n",
555 __func__, bus, bus->busn_res.start,
556 bus->bridge->platform_data);
557
558 /* Firmware doesn't set up card-mode dino, so we have to */
559 if (is_card_dino(&dino_dev->hba.dev->id)) {
560 dino_card_setup(bus, dino_dev->hba.base_addr);
561 } else if (bus->parent) {
562 int i;
563
564 pci_read_bridge_bases(bus);
565
566
567 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
568 if((bus->self->resource[i].flags &
569 (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
570 continue;
571
572 if(bus->self->resource[i].flags & IORESOURCE_MEM) {
573 /* There's a quirk to alignment of
574 * bridge memory resources: the start
575 * is the alignment and start-end is
576 * the size. However, firmware will
577 * have assigned start and end, so we
578 * need to take this into account */
579 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
580 bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
581
582 }
583
584 DBG("DEBUG %s assigning %d [%pR]\n",
585 dev_name(&bus->self->dev), i,
586 &bus->self->resource[i]);
587 WARN_ON(pci_assign_resource(bus->self, i));
588 DBG("DEBUG %s after assign %d [%pR]\n",
589 dev_name(&bus->self->dev), i,
590 &bus->self->resource[i]);
591 }
592 }
593
594
595 list_for_each_entry(dev, &bus->devices, bus_list) {
596 if (is_card_dino(&dino_dev->hba.dev->id))
597 dino_card_fixup(dev);
598
599 /*
600 ** P2PB's only have 2 BARs, no IRQs.
601 ** I'd like to just ignore them for now.
602 */
603 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
604 pcibios_init_bridge(dev);
605 continue;
606 }
607
608 /* null out the ROM resource if there is one (we don't
609 * care about an expansion rom on parisc, since it
610 * usually contains (x86) bios code) */
611 dev->resource[PCI_ROM_RESOURCE].flags = 0;
612
613 if(dev->irq == 255) {
614
615#define DINO_FIX_UNASSIGNED_INTERRUPTS
616#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
617
618 /* This code tries to assign an unassigned
619 * interrupt. Leave it disabled unless you
620 * *really* know what you're doing since the
621 * pin<->interrupt line mapping varies by bus
622 * and machine */
623
624 u32 irq_pin;
625
626 dino_cfg_read(dev->bus, dev->devfn,
627 PCI_INTERRUPT_PIN, 1, &irq_pin);
628 irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
629 printk(KERN_WARNING "Device %s has undefined IRQ, "
630 "setting to %d\n", pci_name(dev), irq_pin);
631 dino_cfg_write(dev->bus, dev->devfn,
632 PCI_INTERRUPT_LINE, 1, irq_pin);
633 dino_assign_irq(dino_dev, irq_pin, &dev->irq);
634#else
635 dev->irq = 65535;
636 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
637#endif
638 } else {
639 /* Adjust INT_LINE for that busses region */
640 dino_assign_irq(dino_dev, dev->irq, &dev->irq);
641 }
642 }
643}
644
645
646static struct pci_bios_ops dino_bios_ops = {
647 .init = dino_bios_init,
648 .fixup_bus = dino_fixup_bus
649};
650
651
652/*
653 * Initialise a DINO controller chip
654 */
655static void __init
656dino_card_init(struct dino_device *dino_dev)
657{
658 u32 brdg_feat = 0x00784e05;
659 unsigned long status;
660
661 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
662 if (status & 0x0000ff80) {
663 __raw_writel(0x00000005,
664 dino_dev->hba.base_addr+DINO_IO_COMMAND);
665 udelay(1);
666 }
667
668 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
669 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
670 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
671
672#if 1
673/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
674 /*
675 ** PCX-L processors don't support XQL like Dino wants it.
676 ** PCX-L2 ignore XQL signal and it doesn't matter.
677 */
678 brdg_feat &= ~0x4; /* UXQL */
679#endif
680 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
681
682 /*
683 ** Don't enable address decoding until we know which I/O range
684 ** currently is available from the host. Only affects MMIO
685 ** and not I/O port space.
686 */
687 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
688
689 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
690 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
691 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
692
693 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
694 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
695 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
696
697 /* Disable PAMR before writing PAPR */
698 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
699 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
700 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
701
702 /*
703 ** Dino ERS encourages enabling FBB (0x6f).
704 ** We can't until we know *all* devices below us can support it.
705 ** (Something in device configuration header tells us).
706 */
707 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
708
709 /* Somewhere, the PCI spec says give devices 1 second
710 ** to recover from the #RESET being de-asserted.
711 ** Experience shows most devices only need 10ms.
712 ** This short-cut speeds up booting significantly.
713 */
714 mdelay(pci_post_reset_delay);
715}
716
717static int __init
718dino_bridge_init(struct dino_device *dino_dev, const char *name)
719{
720 unsigned long io_addr;
721 int result, i, count=0;
722 struct resource *res, *prevres = NULL;
723 /*
724 * Decoding IO_ADDR_EN only works for Built-in Dino
725 * since PDC has already initialized this.
726 */
727
728 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
729 if (io_addr == 0) {
730 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
731 return -ENODEV;
732 }
733
734 res = &dino_dev->hba.lmmio_space;
735 for (i = 0; i < 32; i++) {
736 unsigned long start, end;
737
738 if((io_addr & (1 << i)) == 0)
739 continue;
740
741 start = F_EXTEND(0xf0000000UL) | (i << 23);
742 end = start + 8 * 1024 * 1024 - 1;
743
744 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
745 start, end);
746
747 if(prevres && prevres->end + 1 == start) {
748 prevres->end = end;
749 } else {
750 if(count >= DINO_MAX_LMMIO_RESOURCES) {
751 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
752 break;
753 }
754 prevres = res;
755 res->start = start;
756 res->end = end;
757 res->flags = IORESOURCE_MEM;
758 res->name = kmalloc(64, GFP_KERNEL);
759 if(res->name)
760 snprintf((char *)res->name, 64, "%s LMMIO %d",
761 name, count);
762 res++;
763 count++;
764 }
765 }
766
767 res = &dino_dev->hba.lmmio_space;
768
769 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
770 if(res[i].flags == 0)
771 break;
772
773 result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
774 if (result < 0) {
775 printk(KERN_ERR "%s: failed to claim PCI Bus address "
776 "space %d (%pR)!\n", name, i, &res[i]);
777 return result;
778 }
779 }
780 return 0;
781}
782
783static int __init dino_common_init(struct parisc_device *dev,
784 struct dino_device *dino_dev, const char *name)
785{
786 int status;
787 u32 eim;
788 struct gsc_irq gsc_irq;
789 struct resource *res;
790
791 pcibios_register_hba(&dino_dev->hba);
792
793 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
794 pci_port = &dino_port_ops;
795
796 /*
797 ** Note: SMP systems can make use of IRR1/IAR1 registers
798 ** But it won't buy much performance except in very
799 ** specific applications/configurations. Note Dino
800 ** still only has 11 IRQ input lines - just map some of them
801 ** to a different processor.
802 */
803 dev->irq = gsc_alloc_irq(&gsc_irq);
804 dino_dev->txn_addr = gsc_irq.txn_addr;
805 dino_dev->txn_data = gsc_irq.txn_data;
806 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
807
808 /*
809 ** Dino needs a PA "IRQ" to get a processor's attention.
810 ** arch/parisc/kernel/irq.c returns an EIRR bit.
811 */
812 if (dev->irq < 0) {
813 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
814 return 1;
815 }
816
817 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
818 if (status) {
819 printk(KERN_WARNING "%s: request_irq() failed with %d\n",
820 name, status);
821 return 1;
822 }
823
824 /* Support the serial port which is sometimes attached on built-in
825 * Dino / Cujo chips.
826 */
827
828 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
829
830 /*
831 ** This enables DINO to generate interrupts when it sees
832 ** any of its inputs *change*. Just asserting an IRQ
833 ** before it's enabled (ie unmasked) isn't good enough.
834 */
835 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
836
837 /*
838 ** Some platforms don't clear Dino's IRR0 register at boot time.
839 ** Reading will clear it now.
840 */
841 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
842
843 /* allocate I/O Port resource region */
844 res = &dino_dev->hba.io_space;
845 if (!is_cujo(&dev->id)) {
846 res->name = "Dino I/O Port";
847 } else {
848 res->name = "Cujo I/O Port";
849 }
850 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
851 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
852 res->flags = IORESOURCE_IO; /* do not mark it busy ! */
853 if (request_resource(&ioport_resource, res) < 0) {
854 printk(KERN_ERR "%s: request I/O Port region failed "
855 "0x%lx/%lx (hpa 0x%px)\n",
856 name, (unsigned long)res->start, (unsigned long)res->end,
857 dino_dev->hba.base_addr);
858 return 1;
859 }
860
861 return 0;
862}
863
864#define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
865#define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
866#define CUJO_RAVEN_BADPAGE 0x01003000UL
867#define CUJO_FIREHAWK_BADPAGE 0x01607000UL
868
869static const char *dino_vers[] = {
870 "2.0",
871 "2.1",
872 "3.0",
873 "3.1"
874};
875
876static const char *cujo_vers[] = {
877 "1.0",
878 "2.0"
879};
880
881void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
882
883/*
884** Determine if dino should claim this chip (return 0) or not (return 1).
885** If so, initialize the chip appropriately (card-mode vs bridge mode).
886** Much of the initialization is common though.
887*/
888static int __init dino_probe(struct parisc_device *dev)
889{
890 struct dino_device *dino_dev; // Dino specific control struct
891 const char *version = "unknown";
892 char *name;
893 int is_cujo = 0;
894 LIST_HEAD(resources);
895 struct pci_bus *bus;
896 unsigned long hpa = dev->hpa.start;
897 int max;
898
899 name = "Dino";
900 if (is_card_dino(&dev->id)) {
901 version = "3.x (card mode)";
902 } else {
903 if (!is_cujo(&dev->id)) {
904 if (dev->id.hversion_rev < 4) {
905 version = dino_vers[dev->id.hversion_rev];
906 }
907 } else {
908 name = "Cujo";
909 is_cujo = 1;
910 if (dev->id.hversion_rev < 2) {
911 version = cujo_vers[dev->id.hversion_rev];
912 }
913 }
914 }
915
916 printk("%s version %s found at 0x%lx\n", name, version, hpa);
917
918 if (!request_mem_region(hpa, PAGE_SIZE, name)) {
919 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
920 hpa);
921 return 1;
922 }
923
924 /* Check for bugs */
925 if (is_cujo && dev->id.hversion_rev == 1) {
926#ifdef CONFIG_IOMMU_CCIO
927 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
928 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
929 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
930 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
931 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
932 } else {
933 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
934 }
935#endif
936 } else if (!is_cujo && !is_card_dino(&dev->id) &&
937 dev->id.hversion_rev < 3) {
938 printk(KERN_WARNING
939"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
940"data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
941"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
942"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
943 dev->id.hversion_rev);
944/* REVISIT: why are C200/C240 listed in the README table but not
945** "Models affected"? Could be an omission in the original literature.
946*/
947 }
948
949 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
950 if (!dino_dev) {
951 printk("dino_init_chip - couldn't alloc dino_device\n");
952 return 1;
953 }
954
955 dino_dev->hba.dev = dev;
956 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
957 dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
958 spin_lock_init(&dino_dev->dinosaur_pen);
959 dino_dev->hba.iommu = ccio_get_iommu(dev);
960
961 if (is_card_dino(&dev->id)) {
962 dino_card_init(dino_dev);
963 } else {
964 dino_bridge_init(dino_dev, name);
965 }
966
967 if (dino_common_init(dev, dino_dev, name))
968 return 1;
969
970 dev->dev.platform_data = dino_dev;
971
972 pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
973 HBA_PORT_BASE(dino_dev->hba.hba_num));
974 if (dino_dev->hba.lmmio_space.flags)
975 pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
976 dino_dev->hba.lmmio_space_offset);
977 if (dino_dev->hba.elmmio_space.flags)
978 pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
979 dino_dev->hba.lmmio_space_offset);
980 if (dino_dev->hba.gmmio_space.flags)
981 pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
982
983 dino_dev->hba.bus_num.start = dino_current_bus;
984 dino_dev->hba.bus_num.end = 255;
985 dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
986 pci_add_resource(&resources, &dino_dev->hba.bus_num);
987 /*
988 ** It's not used to avoid chicken/egg problems
989 ** with configuration accessor functions.
990 */
991 dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
992 dino_current_bus, &dino_cfg_ops, NULL, &resources);
993 if (!bus) {
994 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
995 dev_name(&dev->dev), dino_current_bus);
996 pci_free_resource_list(&resources);
997 /* increment the bus number in case of duplicates */
998 dino_current_bus++;
999 return 0;
1000 }
1001
1002 max = pci_scan_child_bus(bus);
1003 pci_bus_update_busn_res_end(bus, max);
1004
1005 /* This code *depends* on scanning being single threaded
1006 * if it isn't, this global bus number count will fail
1007 */
1008 dino_current_bus = max + 1;
1009 pci_bus_assign_resources(bus);
1010 pci_bus_add_devices(bus);
1011 return 0;
1012}
1013
1014/*
1015 * Normally, we would just test sversion. But the Elroy PCI adapter has
1016 * the same sversion as Dino, so we have to check hversion as well.
1017 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1018 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1019 * For card-mode Dino, most machines report an sversion of 9D. But 715
1020 * and 725 firmware misreport it as 0x08080 for no adequately explained
1021 * reason.
1022 */
1023static const struct parisc_device_id dino_tbl[] __initconst = {
1024 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1025 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1026 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1027 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1028 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1029 { 0, }
1030};
1031
1032static struct parisc_driver dino_driver __refdata = {
1033 .name = "dino",
1034 .id_table = dino_tbl,
1035 .probe = dino_probe,
1036};
1037
1038/*
1039 * One time initialization to let the world know Dino is here.
1040 * This is the only routine which is NOT static.
1041 * Must be called exactly once before pci_init().
1042 */
1043int __init dino_init(void)
1044{
1045 register_parisc_driver(&dino_driver);
1046 return 0;
1047}
1048
1049

Warning: That file was not part of the compilation database. It may have many parsing errors.