1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Cadence Sierra PHY Driver |
4 | * |
5 | * Copyright (c) 2018 Cadence Design Systems |
6 | * Author: Alan Douglas <adouglas@cadence.com> |
7 | * |
8 | */ |
9 | #include <linux/clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/err.h> |
13 | #include <linux/io.h> |
14 | #include <linux/module.h> |
15 | #include <linux/phy/phy.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/pm_runtime.h> |
18 | #include <linux/regmap.h> |
19 | #include <linux/reset.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/of.h> |
22 | #include <linux/of_platform.h> |
23 | #include <dt-bindings/phy/phy.h> |
24 | #include <dt-bindings/phy/phy-cadence.h> |
25 | |
26 | #define NUM_SSC_MODE 3 |
27 | #define NUM_PHY_TYPE 5 |
28 | |
29 | /* PHY register offsets */ |
30 | #define SIERRA_COMMON_CDB_OFFSET 0x0 |
31 | #define SIERRA_MACRO_ID_REG 0x0 |
32 | #define SIERRA_CMN_PLLLC_GEN_PREG 0x42 |
33 | #define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG 0x43 |
34 | #define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG 0x45 |
35 | #define SIERRA_CMN_PLLLC_INIT_PREG 0x46 |
36 | #define SIERRA_CMN_PLLLC_ITERTMR_PREG 0x47 |
37 | #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 |
38 | #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 |
39 | #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A |
40 | #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B |
41 | #define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG 0x4C |
42 | #define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D |
43 | #define SIERRA_CMN_PLLLC_CLK0_PREG 0x4E |
44 | #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F |
45 | #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 |
46 | #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 |
47 | #define SIERRA_CMN_PLLLC_SS_PREG 0x52 |
48 | #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 |
49 | #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 |
50 | #define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG 0x5D |
51 | #define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG 0x5E |
52 | #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 |
53 | #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 |
54 | #define SIERRA_SDOSCCAL_CLK_CNT_PREG 0x6E |
55 | #define SIERRA_CMN_REFRCV_PREG 0x98 |
56 | #define SIERRA_CMN_RESCAL_CTRLA_PREG 0xA0 |
57 | #define SIERRA_CMN_REFRCV1_PREG 0xB8 |
58 | #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 |
59 | #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3 |
60 | #define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5 |
61 | #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA |
62 | #define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE |
63 | #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 |
64 | #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 |
65 | |
66 | #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
67 | ((0x4000 << (block_offset)) + \ |
68 | (((ln) << 9) << (reg_offset))) |
69 | |
70 | #define SIERRA_DET_STANDEC_A_PREG 0x000 |
71 | #define SIERRA_DET_STANDEC_B_PREG 0x001 |
72 | #define SIERRA_DET_STANDEC_C_PREG 0x002 |
73 | #define SIERRA_DET_STANDEC_D_PREG 0x003 |
74 | #define SIERRA_DET_STANDEC_E_PREG 0x004 |
75 | #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 |
76 | #define SIERRA_PSM_A0IN_TMR_PREG 0x009 |
77 | #define SIERRA_PSM_A3IN_TMR_PREG 0x00C |
78 | #define SIERRA_PSM_DIAG_PREG 0x015 |
79 | #define SIERRA_PSC_LN_A3_PREG 0x023 |
80 | #define SIERRA_PSC_LN_A4_PREG 0x024 |
81 | #define SIERRA_PSC_LN_IDLE_PREG 0x026 |
82 | #define SIERRA_PSC_TX_A0_PREG 0x028 |
83 | #define SIERRA_PSC_TX_A1_PREG 0x029 |
84 | #define SIERRA_PSC_TX_A2_PREG 0x02A |
85 | #define SIERRA_PSC_TX_A3_PREG 0x02B |
86 | #define SIERRA_PSC_RX_A0_PREG 0x030 |
87 | #define SIERRA_PSC_RX_A1_PREG 0x031 |
88 | #define SIERRA_PSC_RX_A2_PREG 0x032 |
89 | #define SIERRA_PSC_RX_A3_PREG 0x033 |
90 | #define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039 |
91 | #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A |
92 | #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B |
93 | #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E |
94 | #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F |
95 | #define SIERRA_PLLCTRL_STATUS_PREG 0x044 |
96 | #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B |
97 | #define SIERRA_DFE_BIASTRIM_PREG 0x04C |
98 | #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A |
99 | #define SIERRA_DRVCTRL_BOOST_PREG 0x06F |
100 | #define SIERRA_LANE_TX_RECEIVER_DETECT_PREG 0x071 |
101 | #define SIERRA_TX_RCVDET_OVRD_PREG 0x072 |
102 | #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 |
103 | #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 |
104 | #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 |
105 | #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 |
106 | #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 |
107 | #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C |
108 | #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E |
109 | #define SIERRA_RX_CTLE_CAL_PREG 0x08F |
110 | #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 |
111 | #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 |
112 | #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 |
113 | #define SIERRA_CREQ_SPARE_PREG 0x096 |
114 | #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 |
115 | #define SIERRA_CTLELUT_CTRL_PREG 0x098 |
116 | #define SIERRA_DEQ_BLK_TAU_CTRL1_PREG 0x0AC |
117 | #define SIERRA_DEQ_BLK_TAU_CTRL4_PREG 0x0AF |
118 | #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 |
119 | #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 |
120 | #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 |
121 | #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 |
122 | #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 |
123 | #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD |
124 | #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE |
125 | #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 |
126 | #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 |
127 | #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 |
128 | #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 |
129 | #define SIERRA_DEQ_GLUT0 0x0E8 |
130 | #define SIERRA_DEQ_GLUT1 0x0E9 |
131 | #define SIERRA_DEQ_GLUT2 0x0EA |
132 | #define SIERRA_DEQ_GLUT3 0x0EB |
133 | #define SIERRA_DEQ_GLUT4 0x0EC |
134 | #define SIERRA_DEQ_GLUT5 0x0ED |
135 | #define SIERRA_DEQ_GLUT6 0x0EE |
136 | #define SIERRA_DEQ_GLUT7 0x0EF |
137 | #define SIERRA_DEQ_GLUT8 0x0F0 |
138 | #define SIERRA_DEQ_GLUT9 0x0F1 |
139 | #define SIERRA_DEQ_GLUT10 0x0F2 |
140 | #define SIERRA_DEQ_GLUT11 0x0F3 |
141 | #define SIERRA_DEQ_GLUT12 0x0F4 |
142 | #define SIERRA_DEQ_GLUT13 0x0F5 |
143 | #define SIERRA_DEQ_GLUT14 0x0F6 |
144 | #define SIERRA_DEQ_GLUT15 0x0F7 |
145 | #define SIERRA_DEQ_GLUT16 0x0F8 |
146 | #define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG 0x0F9 |
147 | #define SIERRA_TAU_EN_CEPH2TO0_PREG 0x0FB |
148 | #define SIERRA_TAU_EN_CEPH5TO3_PREG 0x0FC |
149 | #define SIERRA_DEQ_ALUT0 0x108 |
150 | #define SIERRA_DEQ_ALUT1 0x109 |
151 | #define SIERRA_DEQ_ALUT2 0x10A |
152 | #define SIERRA_DEQ_ALUT3 0x10B |
153 | #define SIERRA_DEQ_ALUT4 0x10C |
154 | #define SIERRA_DEQ_ALUT5 0x10D |
155 | #define SIERRA_DEQ_ALUT6 0x10E |
156 | #define SIERRA_DEQ_ALUT7 0x10F |
157 | #define SIERRA_DEQ_ALUT8 0x110 |
158 | #define SIERRA_DEQ_ALUT9 0x111 |
159 | #define SIERRA_DEQ_ALUT10 0x112 |
160 | #define SIERRA_DEQ_ALUT11 0x113 |
161 | #define SIERRA_DEQ_ALUT12 0x114 |
162 | #define SIERRA_DEQ_ALUT13 0x115 |
163 | #define SIERRA_OEPH_EN_CTRL_PREG 0x124 |
164 | #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 |
165 | #define SIERRA_DEQ_DFETAP0 0x129 |
166 | #define SIERRA_DEQ_DFETAP1 0x12B |
167 | #define SIERRA_DEQ_DFETAP2 0x12D |
168 | #define SIERRA_DEQ_DFETAP3 0x12F |
169 | #define SIERRA_DEQ_DFETAP4 0x131 |
170 | #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 |
171 | #define SIERRA_DEQ_PRECUR_PREG 0x138 |
172 | #define SIERRA_DEQ_POSTCUR_PREG 0x140 |
173 | #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 |
174 | #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 |
175 | #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 |
176 | #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 |
177 | #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 |
178 | #define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159 |
179 | #define SIERRA_DEQ_PICTRL_PREG 0x161 |
180 | #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 |
181 | #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 |
182 | #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 |
183 | #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C |
184 | #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E |
185 | #define SIERRA_CPI_TRIM_PREG 0x17F |
186 | #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 |
187 | #define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG 0x184 |
188 | #define SIERRA_EPI_CTRL_PREG 0x187 |
189 | #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 |
190 | #define SIERRA_LFPSFILT_NS_PREG 0x18A |
191 | #define SIERRA_LFPSFILT_RD_PREG 0x18B |
192 | #define SIERRA_LFPSFILT_MP_PREG 0x18C |
193 | #define SIERRA_SIGDET_SUPPORT_PREG 0x190 |
194 | #define SIERRA_SDFILT_H2L_A_PREG 0x191 |
195 | #define SIERRA_SDFILT_L2H_PREG 0x193 |
196 | #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E |
197 | #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F |
198 | #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 |
199 | #define SIERRA_LN_SPARE_REG_PREG 0x1B0 |
200 | #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F |
201 | #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 |
202 | |
203 | /* PHY PCS common registers */ |
204 | #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ |
205 | (0xc000 << (block_offset)) |
206 | #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 |
207 | #define SIERRA_PHY_PLL_CFG 0xe |
208 | |
209 | /* PHY PCS lane registers */ |
210 | #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
211 | ((0xD000 << (block_offset)) + \ |
212 | (((ln) << 8) << (reg_offset))) |
213 | |
214 | #define SIERRA_PHY_ISO_LINK_CTRL 0xB |
215 | |
216 | /* PHY PMA common registers */ |
217 | #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) \ |
218 | (0xE000 << (block_offset)) |
219 | #define SIERRA_PHY_PMA_CMN_CTRL 0x000 |
220 | |
221 | /* PHY PMA lane registers */ |
222 | #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ |
223 | ((0xF000 << (block_offset)) + \ |
224 | (((ln) << 8) << (reg_offset))) |
225 | |
226 | #define SIERRA_PHY_PMA_XCVR_CTRL 0x000 |
227 | |
228 | #define SIERRA_MACRO_ID 0x00007364 |
229 | #define SIERRA_MAX_LANES 16 |
230 | #define PLL_LOCK_TIME 100000 |
231 | |
232 | #define CDNS_SIERRA_OUTPUT_CLOCKS 3 |
233 | #define CDNS_SIERRA_INPUT_CLOCKS 3 |
234 | enum cdns_sierra_clock_input { |
235 | PHY_CLK, |
236 | CMN_REFCLK_DIG_DIV, |
237 | CMN_REFCLK1_DIG_DIV, |
238 | }; |
239 | |
240 | #define SIERRA_NUM_CMN_PLLC 2 |
241 | #define SIERRA_NUM_CMN_PLLC_PARENTS 2 |
242 | |
243 | static const struct reg_field macro_id_type = |
244 | REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); |
245 | static const struct reg_field phy_pll_cfg_1 = |
246 | REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); |
247 | static const struct reg_field pma_cmn_ready = |
248 | REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); |
249 | static const struct reg_field pllctrl_lock = |
250 | REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); |
251 | static const struct reg_field phy_iso_link_ctrl_1 = |
252 | REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); |
253 | static const struct reg_field cmn_plllc_clk1outdiv_preg = |
254 | REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6); |
255 | static const struct reg_field cmn_plllc_clk1_en_preg = |
256 | REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12); |
257 | |
258 | static const char * const clk_names[] = { |
259 | [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc" , |
260 | [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1" , |
261 | [CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der" , |
262 | }; |
263 | |
264 | enum cdns_sierra_cmn_plllc { |
265 | CMN_PLLLC, |
266 | CMN_PLLLC1, |
267 | }; |
268 | |
269 | struct cdns_sierra_pll_mux_reg_fields { |
270 | struct reg_field pfdclk_sel_preg; |
271 | struct reg_field plllc1en_field; |
272 | struct reg_field termen_field; |
273 | }; |
274 | |
275 | static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { |
276 | [CMN_PLLLC] = { |
277 | .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), |
278 | .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), |
279 | .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), |
280 | }, |
281 | [CMN_PLLLC1] = { |
282 | .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), |
283 | .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), |
284 | .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), |
285 | }, |
286 | }; |
287 | |
288 | struct cdns_sierra_pll_mux { |
289 | struct clk_hw hw; |
290 | struct regmap_field *pfdclk_sel_preg; |
291 | struct regmap_field *plllc1en_field; |
292 | struct regmap_field *termen_field; |
293 | struct clk_init_data clk_data; |
294 | }; |
295 | |
296 | #define to_cdns_sierra_pll_mux(_hw) \ |
297 | container_of(_hw, struct cdns_sierra_pll_mux, hw) |
298 | |
299 | #define PLL0_REFCLK_NAME "pll0_refclk" |
300 | #define PLL1_REFCLK_NAME "pll1_refclk" |
301 | |
302 | static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = { |
303 | [CMN_PLLLC] = { |
304 | { .fw_name = PLL0_REFCLK_NAME }, |
305 | { .fw_name = PLL1_REFCLK_NAME } |
306 | }, |
307 | [CMN_PLLLC1] = { |
308 | { .fw_name = PLL1_REFCLK_NAME }, |
309 | { .fw_name = PLL0_REFCLK_NAME } |
310 | }, |
311 | }; |
312 | |
313 | static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = { |
314 | [CMN_PLLLC] = { 0, 1 }, |
315 | [CMN_PLLLC1] = { 1, 0 }, |
316 | }; |
317 | |
318 | struct cdns_sierra_derived_refclk { |
319 | struct clk_hw hw; |
320 | struct regmap_field *cmn_plllc_clk1outdiv_preg; |
321 | struct regmap_field *cmn_plllc_clk1_en_preg; |
322 | struct clk_init_data clk_data; |
323 | }; |
324 | |
325 | #define to_cdns_sierra_derived_refclk(_hw) \ |
326 | container_of(_hw, struct cdns_sierra_derived_refclk, hw) |
327 | |
328 | enum cdns_sierra_phy_type { |
329 | TYPE_NONE, |
330 | TYPE_PCIE, |
331 | TYPE_USB, |
332 | TYPE_SGMII, |
333 | TYPE_QSGMII |
334 | }; |
335 | |
336 | enum cdns_sierra_ssc_mode { |
337 | NO_SSC, |
338 | EXTERNAL_SSC, |
339 | INTERNAL_SSC |
340 | }; |
341 | |
342 | struct cdns_sierra_inst { |
343 | struct phy *phy; |
344 | enum cdns_sierra_phy_type phy_type; |
345 | u32 num_lanes; |
346 | u32 mlane; |
347 | struct reset_control *lnk_rst; |
348 | enum cdns_sierra_ssc_mode ssc_mode; |
349 | }; |
350 | |
351 | struct cdns_reg_pairs { |
352 | u16 val; |
353 | u32 off; |
354 | }; |
355 | |
356 | struct cdns_sierra_vals { |
357 | const struct cdns_reg_pairs *reg_pairs; |
358 | u32 num_regs; |
359 | }; |
360 | |
361 | struct cdns_sierra_data { |
362 | u32 id_value; |
363 | u8 block_offset_shift; |
364 | u8 reg_offset_shift; |
365 | struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
366 | [NUM_SSC_MODE]; |
367 | struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
368 | [NUM_SSC_MODE]; |
369 | struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
370 | [NUM_SSC_MODE]; |
371 | struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] |
372 | [NUM_SSC_MODE]; |
373 | }; |
374 | |
375 | struct cdns_regmap_cdb_context { |
376 | struct device *dev; |
377 | void __iomem *base; |
378 | u8 reg_offset_shift; |
379 | }; |
380 | |
381 | struct cdns_sierra_phy { |
382 | struct device *dev; |
383 | const struct cdns_sierra_data *init_data; |
384 | struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; |
385 | struct reset_control *phy_rst; |
386 | struct reset_control *apb_rst; |
387 | struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; |
388 | struct regmap *regmap_phy_pcs_common_cdb; |
389 | struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; |
390 | struct regmap *regmap_phy_pma_common_cdb; |
391 | struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; |
392 | struct regmap *regmap_common_cdb; |
393 | struct regmap_field *macro_id_type; |
394 | struct regmap_field *phy_pll_cfg_1; |
395 | struct regmap_field *pma_cmn_ready; |
396 | struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; |
397 | struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; |
398 | struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; |
399 | struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; |
400 | struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; |
401 | struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; |
402 | int nsubnodes; |
403 | u32 num_lanes; |
404 | bool autoconf; |
405 | int already_configured; |
406 | struct clk *pll_clks[SIERRA_NUM_CMN_PLLC]; |
407 | struct clk_hw_onecell_data clk_data; |
408 | }; |
409 | |
410 | static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) |
411 | { |
412 | struct cdns_regmap_cdb_context *ctx = context; |
413 | u32 offset = reg << ctx->reg_offset_shift; |
414 | |
415 | writew(val, addr: ctx->base + offset); |
416 | |
417 | return 0; |
418 | } |
419 | |
420 | static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) |
421 | { |
422 | struct cdns_regmap_cdb_context *ctx = context; |
423 | u32 offset = reg << ctx->reg_offset_shift; |
424 | |
425 | *val = readw(addr: ctx->base + offset); |
426 | return 0; |
427 | } |
428 | |
429 | #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ |
430 | { \ |
431 | .name = "sierra_lane" n "_cdb", \ |
432 | .reg_stride = 1, \ |
433 | .fast_io = true, \ |
434 | .reg_write = cdns_regmap_write, \ |
435 | .reg_read = cdns_regmap_read, \ |
436 | } |
437 | |
438 | static const struct regmap_config cdns_sierra_lane_cdb_config[] = { |
439 | SIERRA_LANE_CDB_REGMAP_CONF("0" ), |
440 | SIERRA_LANE_CDB_REGMAP_CONF("1" ), |
441 | SIERRA_LANE_CDB_REGMAP_CONF("2" ), |
442 | SIERRA_LANE_CDB_REGMAP_CONF("3" ), |
443 | SIERRA_LANE_CDB_REGMAP_CONF("4" ), |
444 | SIERRA_LANE_CDB_REGMAP_CONF("5" ), |
445 | SIERRA_LANE_CDB_REGMAP_CONF("6" ), |
446 | SIERRA_LANE_CDB_REGMAP_CONF("7" ), |
447 | SIERRA_LANE_CDB_REGMAP_CONF("8" ), |
448 | SIERRA_LANE_CDB_REGMAP_CONF("9" ), |
449 | SIERRA_LANE_CDB_REGMAP_CONF("10" ), |
450 | SIERRA_LANE_CDB_REGMAP_CONF("11" ), |
451 | SIERRA_LANE_CDB_REGMAP_CONF("12" ), |
452 | SIERRA_LANE_CDB_REGMAP_CONF("13" ), |
453 | SIERRA_LANE_CDB_REGMAP_CONF("14" ), |
454 | SIERRA_LANE_CDB_REGMAP_CONF("15" ), |
455 | }; |
456 | |
457 | static const struct regmap_config cdns_sierra_common_cdb_config = { |
458 | .name = "sierra_common_cdb" , |
459 | .reg_stride = 1, |
460 | .fast_io = true, |
461 | .reg_write = cdns_regmap_write, |
462 | .reg_read = cdns_regmap_read, |
463 | }; |
464 | |
465 | static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = { |
466 | .name = "sierra_phy_pcs_cmn_cdb" , |
467 | .reg_stride = 1, |
468 | .fast_io = true, |
469 | .reg_write = cdns_regmap_write, |
470 | .reg_read = cdns_regmap_read, |
471 | }; |
472 | |
473 | #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ |
474 | { \ |
475 | .name = "sierra_phy_pcs_lane" n "_cdb", \ |
476 | .reg_stride = 1, \ |
477 | .fast_io = true, \ |
478 | .reg_write = cdns_regmap_write, \ |
479 | .reg_read = cdns_regmap_read, \ |
480 | } |
481 | |
482 | static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = { |
483 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0" ), |
484 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1" ), |
485 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2" ), |
486 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3" ), |
487 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4" ), |
488 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5" ), |
489 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6" ), |
490 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7" ), |
491 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8" ), |
492 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9" ), |
493 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10" ), |
494 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11" ), |
495 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12" ), |
496 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13" ), |
497 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14" ), |
498 | SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15" ), |
499 | }; |
500 | |
501 | static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = { |
502 | .name = "sierra_phy_pma_cmn_cdb" , |
503 | .reg_stride = 1, |
504 | .fast_io = true, |
505 | .reg_write = cdns_regmap_write, |
506 | .reg_read = cdns_regmap_read, |
507 | }; |
508 | |
509 | #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \ |
510 | { \ |
511 | .name = "sierra_phy_pma_lane" n "_cdb", \ |
512 | .reg_stride = 1, \ |
513 | .fast_io = true, \ |
514 | .reg_write = cdns_regmap_write, \ |
515 | .reg_read = cdns_regmap_read, \ |
516 | } |
517 | |
518 | static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = { |
519 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0" ), |
520 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1" ), |
521 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2" ), |
522 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3" ), |
523 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4" ), |
524 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5" ), |
525 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6" ), |
526 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7" ), |
527 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8" ), |
528 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9" ), |
529 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10" ), |
530 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11" ), |
531 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12" ), |
532 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13" ), |
533 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14" ), |
534 | SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15" ), |
535 | }; |
536 | |
537 | static int cdns_sierra_phy_init(struct phy *gphy) |
538 | { |
539 | struct cdns_sierra_inst *ins = phy_get_drvdata(phy: gphy); |
540 | struct cdns_sierra_phy *phy = dev_get_drvdata(dev: gphy->dev.parent); |
541 | const struct cdns_sierra_data *init_data = phy->init_data; |
542 | struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; |
543 | enum cdns_sierra_phy_type phy_type = ins->phy_type; |
544 | enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; |
545 | struct cdns_sierra_vals *phy_pma_ln_vals; |
546 | const struct cdns_reg_pairs *reg_pairs; |
547 | struct cdns_sierra_vals *pcs_cmn_vals; |
548 | struct regmap *regmap; |
549 | u32 num_regs; |
550 | int i, j; |
551 | |
552 | /* Initialise the PHY registers, unless auto configured */ |
553 | if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) |
554 | return 0; |
555 | |
556 | clk_set_rate(clk: phy->input_clks[CMN_REFCLK_DIG_DIV], rate: 25000000); |
557 | clk_set_rate(clk: phy->input_clks[CMN_REFCLK1_DIG_DIV], rate: 25000000); |
558 | |
559 | /* PHY PCS common registers configurations */ |
560 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; |
561 | if (pcs_cmn_vals) { |
562 | reg_pairs = pcs_cmn_vals->reg_pairs; |
563 | num_regs = pcs_cmn_vals->num_regs; |
564 | regmap = phy->regmap_phy_pcs_common_cdb; |
565 | for (i = 0; i < num_regs; i++) |
566 | regmap_write(map: regmap, reg: reg_pairs[i].off, val: reg_pairs[i].val); |
567 | } |
568 | |
569 | /* PHY PMA lane registers configurations */ |
570 | phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; |
571 | if (phy_pma_ln_vals) { |
572 | reg_pairs = phy_pma_ln_vals->reg_pairs; |
573 | num_regs = phy_pma_ln_vals->num_regs; |
574 | for (i = 0; i < ins->num_lanes; i++) { |
575 | regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; |
576 | for (j = 0; j < num_regs; j++) |
577 | regmap_write(map: regmap, reg: reg_pairs[j].off, val: reg_pairs[j].val); |
578 | } |
579 | } |
580 | |
581 | /* PMA common registers configurations */ |
582 | pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; |
583 | if (pma_cmn_vals) { |
584 | reg_pairs = pma_cmn_vals->reg_pairs; |
585 | num_regs = pma_cmn_vals->num_regs; |
586 | regmap = phy->regmap_common_cdb; |
587 | for (i = 0; i < num_regs; i++) |
588 | regmap_write(map: regmap, reg: reg_pairs[i].off, val: reg_pairs[i].val); |
589 | } |
590 | |
591 | /* PMA lane registers configurations */ |
592 | pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; |
593 | if (pma_ln_vals) { |
594 | reg_pairs = pma_ln_vals->reg_pairs; |
595 | num_regs = pma_ln_vals->num_regs; |
596 | for (i = 0; i < ins->num_lanes; i++) { |
597 | regmap = phy->regmap_lane_cdb[i + ins->mlane]; |
598 | for (j = 0; j < num_regs; j++) |
599 | regmap_write(map: regmap, reg: reg_pairs[j].off, val: reg_pairs[j].val); |
600 | } |
601 | } |
602 | |
603 | return 0; |
604 | } |
605 | |
606 | static int cdns_sierra_phy_on(struct phy *gphy) |
607 | { |
608 | struct cdns_sierra_phy *sp = dev_get_drvdata(dev: gphy->dev.parent); |
609 | struct cdns_sierra_inst *ins = phy_get_drvdata(phy: gphy); |
610 | struct device *dev = sp->dev; |
611 | u32 val; |
612 | int ret; |
613 | |
614 | if (sp->nsubnodes == 1) { |
615 | /* Take the PHY out of reset */ |
616 | ret = reset_control_deassert(rstc: sp->phy_rst); |
617 | if (ret) { |
618 | dev_err(dev, "Failed to take the PHY out of reset\n" ); |
619 | return ret; |
620 | } |
621 | } |
622 | |
623 | /* Take the PHY lane group out of reset */ |
624 | ret = reset_control_deassert(rstc: ins->lnk_rst); |
625 | if (ret) { |
626 | dev_err(dev, "Failed to take the PHY lane out of reset\n" ); |
627 | return ret; |
628 | } |
629 | |
630 | if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { |
631 | ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], |
632 | val, !val, 1000, PLL_LOCK_TIME); |
633 | if (ret) { |
634 | dev_err(dev, "Timeout waiting for PHY status ready\n" ); |
635 | return ret; |
636 | } |
637 | } |
638 | |
639 | /* |
640 | * Wait for cmn_ready assertion |
641 | * PHY_PMA_CMN_CTRL[0] == 1 |
642 | */ |
643 | ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, |
644 | 1000, PLL_LOCK_TIME); |
645 | if (ret) { |
646 | dev_err(dev, "Timeout waiting for CMN ready\n" ); |
647 | return ret; |
648 | } |
649 | |
650 | ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], |
651 | val, val, 1000, PLL_LOCK_TIME); |
652 | if (ret < 0) |
653 | dev_err(dev, "PLL lock of lane failed\n" ); |
654 | |
655 | return ret; |
656 | } |
657 | |
658 | static int cdns_sierra_phy_off(struct phy *gphy) |
659 | { |
660 | struct cdns_sierra_inst *ins = phy_get_drvdata(phy: gphy); |
661 | |
662 | return reset_control_assert(rstc: ins->lnk_rst); |
663 | } |
664 | |
665 | static int cdns_sierra_phy_reset(struct phy *gphy) |
666 | { |
667 | struct cdns_sierra_phy *sp = dev_get_drvdata(dev: gphy->dev.parent); |
668 | |
669 | reset_control_assert(rstc: sp->phy_rst); |
670 | reset_control_deassert(rstc: sp->phy_rst); |
671 | return 0; |
672 | }; |
673 | |
674 | static const struct phy_ops ops = { |
675 | .init = cdns_sierra_phy_init, |
676 | .power_on = cdns_sierra_phy_on, |
677 | .power_off = cdns_sierra_phy_off, |
678 | .reset = cdns_sierra_phy_reset, |
679 | .owner = THIS_MODULE, |
680 | }; |
681 | |
682 | static int cdns_sierra_noop_phy_on(struct phy *gphy) |
683 | { |
684 | usleep_range(min: 5000, max: 10000); |
685 | |
686 | return 0; |
687 | } |
688 | |
689 | static const struct phy_ops noop_ops = { |
690 | .power_on = cdns_sierra_noop_phy_on, |
691 | .owner = THIS_MODULE, |
692 | }; |
693 | |
694 | static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) |
695 | { |
696 | struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); |
697 | struct regmap_field *plllc1en_field = mux->plllc1en_field; |
698 | struct regmap_field *termen_field = mux->termen_field; |
699 | struct regmap_field *field = mux->pfdclk_sel_preg; |
700 | unsigned int val; |
701 | int index; |
702 | |
703 | regmap_field_read(field, val: &val); |
704 | |
705 | if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { |
706 | index = clk_mux_val_to_index(hw, table: cdns_sierra_pll_mux_table[CMN_PLLLC1], flags: 0, val); |
707 | if (index == 1) { |
708 | regmap_field_write(field: plllc1en_field, val: 1); |
709 | regmap_field_write(field: termen_field, val: 1); |
710 | } |
711 | } else { |
712 | index = clk_mux_val_to_index(hw, table: cdns_sierra_pll_mux_table[CMN_PLLLC], flags: 0, val); |
713 | } |
714 | |
715 | return index; |
716 | } |
717 | |
718 | static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) |
719 | { |
720 | struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); |
721 | struct regmap_field *plllc1en_field = mux->plllc1en_field; |
722 | struct regmap_field *termen_field = mux->termen_field; |
723 | struct regmap_field *field = mux->pfdclk_sel_preg; |
724 | int val, ret; |
725 | |
726 | ret = regmap_field_write(field: plllc1en_field, val: 0); |
727 | ret |= regmap_field_write(field: termen_field, val: 0); |
728 | if (index == 1) { |
729 | ret |= regmap_field_write(field: plllc1en_field, val: 1); |
730 | ret |= regmap_field_write(field: termen_field, val: 1); |
731 | } |
732 | |
733 | if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) |
734 | val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index]; |
735 | else |
736 | val = cdns_sierra_pll_mux_table[CMN_PLLLC][index]; |
737 | |
738 | ret |= regmap_field_write(field, val); |
739 | |
740 | return ret; |
741 | } |
742 | |
743 | static const struct clk_ops cdns_sierra_pll_mux_ops = { |
744 | .determine_rate = __clk_mux_determine_rate, |
745 | .set_parent = cdns_sierra_pll_mux_set_parent, |
746 | .get_parent = cdns_sierra_pll_mux_get_parent, |
747 | }; |
748 | |
749 | static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, |
750 | struct regmap_field *pfdclk1_sel_field, |
751 | struct regmap_field *plllc1en_field, |
752 | struct regmap_field *termen_field, |
753 | int clk_index) |
754 | { |
755 | struct cdns_sierra_pll_mux *mux; |
756 | struct device *dev = sp->dev; |
757 | struct clk_init_data *init; |
758 | char clk_name[100]; |
759 | int ret; |
760 | |
761 | mux = devm_kzalloc(dev, size: sizeof(*mux), GFP_KERNEL); |
762 | if (!mux) |
763 | return -ENOMEM; |
764 | |
765 | snprintf(buf: clk_name, size: sizeof(clk_name), fmt: "%s_%s" , dev_name(dev), clk_names[clk_index]); |
766 | |
767 | init = &mux->clk_data; |
768 | |
769 | init->ops = &cdns_sierra_pll_mux_ops; |
770 | init->flags = CLK_SET_RATE_NO_REPARENT; |
771 | init->parent_data = pll_mux_parent_data[clk_index]; |
772 | init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; |
773 | init->name = clk_name; |
774 | |
775 | mux->pfdclk_sel_preg = pfdclk1_sel_field; |
776 | mux->plllc1en_field = plllc1en_field; |
777 | mux->termen_field = termen_field; |
778 | mux->hw.init = init; |
779 | |
780 | ret = devm_clk_hw_register(dev, hw: &mux->hw); |
781 | if (ret) |
782 | return ret; |
783 | |
784 | sp->clk_data.hws[clk_index] = &mux->hw; |
785 | |
786 | sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, hw: &mux->hw, |
787 | con_id: clk_names[clk_index]); |
788 | |
789 | return 0; |
790 | } |
791 | |
792 | static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) |
793 | { |
794 | struct regmap_field *pfdclk1_sel_field; |
795 | struct regmap_field *plllc1en_field; |
796 | struct regmap_field *termen_field; |
797 | struct device *dev = sp->dev; |
798 | int ret = 0, i, clk_index; |
799 | |
800 | clk_index = CDNS_SIERRA_PLL_CMNLC; |
801 | for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { |
802 | pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; |
803 | plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; |
804 | termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; |
805 | |
806 | ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field, |
807 | termen_field, clk_index); |
808 | if (ret) { |
809 | dev_err(dev, "Fail to register cmn plllc mux\n" ); |
810 | return ret; |
811 | } |
812 | } |
813 | |
814 | return 0; |
815 | } |
816 | |
817 | static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw) |
818 | { |
819 | struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); |
820 | |
821 | regmap_field_write(field: derived_refclk->cmn_plllc_clk1_en_preg, val: 0x1); |
822 | |
823 | /* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */ |
824 | regmap_field_write(field: derived_refclk->cmn_plllc_clk1outdiv_preg, val: 0x2E); |
825 | |
826 | return 0; |
827 | } |
828 | |
829 | static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw) |
830 | { |
831 | struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); |
832 | |
833 | regmap_field_write(field: derived_refclk->cmn_plllc_clk1_en_preg, val: 0); |
834 | } |
835 | |
836 | static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw) |
837 | { |
838 | struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); |
839 | int val; |
840 | |
841 | regmap_field_read(field: derived_refclk->cmn_plllc_clk1_en_preg, val: &val); |
842 | |
843 | return !!val; |
844 | } |
845 | |
846 | static const struct clk_ops cdns_sierra_derived_refclk_ops = { |
847 | .enable = cdns_sierra_derived_refclk_enable, |
848 | .disable = cdns_sierra_derived_refclk_disable, |
849 | .is_enabled = cdns_sierra_derived_refclk_is_enabled, |
850 | }; |
851 | |
852 | static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp) |
853 | { |
854 | struct cdns_sierra_derived_refclk *derived_refclk; |
855 | struct device *dev = sp->dev; |
856 | struct regmap_field *field; |
857 | struct clk_init_data *init; |
858 | struct regmap *regmap; |
859 | char clk_name[100]; |
860 | int ret; |
861 | |
862 | derived_refclk = devm_kzalloc(dev, size: sizeof(*derived_refclk), GFP_KERNEL); |
863 | if (!derived_refclk) |
864 | return -ENOMEM; |
865 | |
866 | snprintf(buf: clk_name, size: sizeof(clk_name), fmt: "%s_%s" , dev_name(dev), |
867 | clk_names[CDNS_SIERRA_DERIVED_REFCLK]); |
868 | |
869 | init = &derived_refclk->clk_data; |
870 | |
871 | init->ops = &cdns_sierra_derived_refclk_ops; |
872 | init->flags = 0; |
873 | init->name = clk_name; |
874 | |
875 | regmap = sp->regmap_common_cdb; |
876 | |
877 | field = devm_regmap_field_alloc(dev, regmap, reg_field: cmn_plllc_clk1outdiv_preg); |
878 | if (IS_ERR(ptr: field)) { |
879 | dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n" ); |
880 | return PTR_ERR(ptr: field); |
881 | } |
882 | derived_refclk->cmn_plllc_clk1outdiv_preg = field; |
883 | |
884 | field = devm_regmap_field_alloc(dev, regmap, reg_field: cmn_plllc_clk1_en_preg); |
885 | if (IS_ERR(ptr: field)) { |
886 | dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n" ); |
887 | return PTR_ERR(ptr: field); |
888 | } |
889 | derived_refclk->cmn_plllc_clk1_en_preg = field; |
890 | |
891 | derived_refclk->hw.init = init; |
892 | |
893 | ret = devm_clk_hw_register(dev, hw: &derived_refclk->hw); |
894 | if (ret) |
895 | return ret; |
896 | |
897 | sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw; |
898 | |
899 | return 0; |
900 | } |
901 | |
902 | static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) |
903 | { |
904 | struct device *dev = sp->dev; |
905 | struct device_node *node = dev->of_node; |
906 | |
907 | of_clk_del_provider(np: node); |
908 | } |
909 | |
910 | static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) |
911 | { |
912 | struct device *dev = sp->dev; |
913 | struct device_node *node = dev->of_node; |
914 | int ret; |
915 | |
916 | ret = cdns_sierra_phy_register_pll_mux(sp); |
917 | if (ret) { |
918 | dev_err(dev, "Failed to pll mux clocks\n" ); |
919 | return ret; |
920 | } |
921 | |
922 | ret = cdns_sierra_derived_refclk_register(sp); |
923 | if (ret) { |
924 | dev_err(dev, "Failed to register derived refclk\n" ); |
925 | return ret; |
926 | } |
927 | |
928 | sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS; |
929 | ret = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, |
930 | data: &sp->clk_data); |
931 | if (ret) |
932 | dev_err(dev, "Failed to add clock provider: %s\n" , node->name); |
933 | |
934 | return ret; |
935 | } |
936 | |
937 | static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, |
938 | struct device_node *child) |
939 | { |
940 | u32 phy_type; |
941 | |
942 | if (of_property_read_u32(np: child, propname: "reg" , out_value: &inst->mlane)) |
943 | return -EINVAL; |
944 | |
945 | if (of_property_read_u32(np: child, propname: "cdns,num-lanes" , out_value: &inst->num_lanes)) |
946 | return -EINVAL; |
947 | |
948 | if (of_property_read_u32(np: child, propname: "cdns,phy-type" , out_value: &phy_type)) |
949 | return -EINVAL; |
950 | |
951 | switch (phy_type) { |
952 | case PHY_TYPE_PCIE: |
953 | inst->phy_type = TYPE_PCIE; |
954 | break; |
955 | case PHY_TYPE_USB3: |
956 | inst->phy_type = TYPE_USB; |
957 | break; |
958 | case PHY_TYPE_SGMII: |
959 | inst->phy_type = TYPE_SGMII; |
960 | break; |
961 | case PHY_TYPE_QSGMII: |
962 | inst->phy_type = TYPE_QSGMII; |
963 | break; |
964 | default: |
965 | return -EINVAL; |
966 | } |
967 | |
968 | inst->ssc_mode = EXTERNAL_SSC; |
969 | of_property_read_u32(np: child, propname: "cdns,ssc-mode" , out_value: &inst->ssc_mode); |
970 | |
971 | return 0; |
972 | } |
973 | |
974 | static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, |
975 | u32 block_offset, u8 reg_offset_shift, |
976 | const struct regmap_config *config) |
977 | { |
978 | struct cdns_regmap_cdb_context *ctx; |
979 | |
980 | ctx = devm_kzalloc(dev, size: sizeof(*ctx), GFP_KERNEL); |
981 | if (!ctx) |
982 | return ERR_PTR(error: -ENOMEM); |
983 | |
984 | ctx->dev = dev; |
985 | ctx->base = base + block_offset; |
986 | ctx->reg_offset_shift = reg_offset_shift; |
987 | |
988 | return devm_regmap_init(dev, NULL, ctx, config); |
989 | } |
990 | |
991 | static int cdns_regfield_init(struct cdns_sierra_phy *sp) |
992 | { |
993 | struct device *dev = sp->dev; |
994 | struct regmap_field *field; |
995 | struct reg_field reg_field; |
996 | struct regmap *regmap; |
997 | int i; |
998 | |
999 | regmap = sp->regmap_common_cdb; |
1000 | field = devm_regmap_field_alloc(dev, regmap, reg_field: macro_id_type); |
1001 | if (IS_ERR(ptr: field)) { |
1002 | dev_err(dev, "MACRO_ID_TYPE reg field init failed\n" ); |
1003 | return PTR_ERR(ptr: field); |
1004 | } |
1005 | sp->macro_id_type = field; |
1006 | |
1007 | for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { |
1008 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; |
1009 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
1010 | if (IS_ERR(ptr: field)) { |
1011 | dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n" , i); |
1012 | return PTR_ERR(ptr: field); |
1013 | } |
1014 | sp->cmn_plllc_pfdclk1_sel_preg[i] = field; |
1015 | |
1016 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; |
1017 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
1018 | if (IS_ERR(ptr: field)) { |
1019 | dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n" , i); |
1020 | return PTR_ERR(ptr: field); |
1021 | } |
1022 | sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; |
1023 | |
1024 | reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; |
1025 | field = devm_regmap_field_alloc(dev, regmap, reg_field); |
1026 | if (IS_ERR(ptr: field)) { |
1027 | dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n" , i); |
1028 | return PTR_ERR(ptr: field); |
1029 | } |
1030 | sp->cmn_refrcv_refclk_termen_preg[i] = field; |
1031 | } |
1032 | |
1033 | regmap = sp->regmap_phy_pcs_common_cdb; |
1034 | field = devm_regmap_field_alloc(dev, regmap, reg_field: phy_pll_cfg_1); |
1035 | if (IS_ERR(ptr: field)) { |
1036 | dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n" ); |
1037 | return PTR_ERR(ptr: field); |
1038 | } |
1039 | sp->phy_pll_cfg_1 = field; |
1040 | |
1041 | regmap = sp->regmap_phy_pma_common_cdb; |
1042 | field = devm_regmap_field_alloc(dev, regmap, reg_field: pma_cmn_ready); |
1043 | if (IS_ERR(ptr: field)) { |
1044 | dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n" ); |
1045 | return PTR_ERR(ptr: field); |
1046 | } |
1047 | sp->pma_cmn_ready = field; |
1048 | |
1049 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
1050 | regmap = sp->regmap_lane_cdb[i]; |
1051 | field = devm_regmap_field_alloc(dev, regmap, reg_field: pllctrl_lock); |
1052 | if (IS_ERR(ptr: field)) { |
1053 | dev_err(dev, "P%d_ENABLE reg field init failed\n" , i); |
1054 | return PTR_ERR(ptr: field); |
1055 | } |
1056 | sp->pllctrl_lock[i] = field; |
1057 | } |
1058 | |
1059 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
1060 | regmap = sp->regmap_phy_pcs_lane_cdb[i]; |
1061 | field = devm_regmap_field_alloc(dev, regmap, reg_field: phy_iso_link_ctrl_1); |
1062 | if (IS_ERR(ptr: field)) { |
1063 | dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n" , i); |
1064 | return PTR_ERR(ptr: field); |
1065 | } |
1066 | sp->phy_iso_link_ctrl_1[i] = field; |
1067 | } |
1068 | |
1069 | return 0; |
1070 | } |
1071 | |
1072 | static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, |
1073 | void __iomem *base, u8 block_offset_shift, |
1074 | u8 reg_offset_shift) |
1075 | { |
1076 | struct device *dev = sp->dev; |
1077 | struct regmap *regmap; |
1078 | u32 block_offset; |
1079 | int i; |
1080 | |
1081 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
1082 | block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, |
1083 | reg_offset_shift); |
1084 | regmap = cdns_regmap_init(dev, base, block_offset, |
1085 | reg_offset_shift, |
1086 | config: &cdns_sierra_lane_cdb_config[i]); |
1087 | if (IS_ERR(ptr: regmap)) { |
1088 | dev_err(dev, "Failed to init lane CDB regmap\n" ); |
1089 | return PTR_ERR(ptr: regmap); |
1090 | } |
1091 | sp->regmap_lane_cdb[i] = regmap; |
1092 | } |
1093 | |
1094 | regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, |
1095 | reg_offset_shift, |
1096 | config: &cdns_sierra_common_cdb_config); |
1097 | if (IS_ERR(ptr: regmap)) { |
1098 | dev_err(dev, "Failed to init common CDB regmap\n" ); |
1099 | return PTR_ERR(ptr: regmap); |
1100 | } |
1101 | sp->regmap_common_cdb = regmap; |
1102 | |
1103 | block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift); |
1104 | regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, |
1105 | config: &cdns_sierra_phy_pcs_cmn_cdb_config); |
1106 | if (IS_ERR(ptr: regmap)) { |
1107 | dev_err(dev, "Failed to init PHY PCS common CDB regmap\n" ); |
1108 | return PTR_ERR(ptr: regmap); |
1109 | } |
1110 | sp->regmap_phy_pcs_common_cdb = regmap; |
1111 | |
1112 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
1113 | block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, |
1114 | reg_offset_shift); |
1115 | regmap = cdns_regmap_init(dev, base, block_offset, |
1116 | reg_offset_shift, |
1117 | config: &cdns_sierra_phy_pcs_lane_cdb_config[i]); |
1118 | if (IS_ERR(ptr: regmap)) { |
1119 | dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n" ); |
1120 | return PTR_ERR(ptr: regmap); |
1121 | } |
1122 | sp->regmap_phy_pcs_lane_cdb[i] = regmap; |
1123 | } |
1124 | |
1125 | block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift); |
1126 | regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, |
1127 | config: &cdns_sierra_phy_pma_cmn_cdb_config); |
1128 | if (IS_ERR(ptr: regmap)) { |
1129 | dev_err(dev, "Failed to init PHY PMA common CDB regmap\n" ); |
1130 | return PTR_ERR(ptr: regmap); |
1131 | } |
1132 | sp->regmap_phy_pma_common_cdb = regmap; |
1133 | |
1134 | for (i = 0; i < SIERRA_MAX_LANES; i++) { |
1135 | block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift, |
1136 | reg_offset_shift); |
1137 | regmap = cdns_regmap_init(dev, base, block_offset, |
1138 | reg_offset_shift, |
1139 | config: &cdns_sierra_phy_pma_lane_cdb_config[i]); |
1140 | if (IS_ERR(ptr: regmap)) { |
1141 | dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n" ); |
1142 | return PTR_ERR(ptr: regmap); |
1143 | } |
1144 | sp->regmap_phy_pma_lane_cdb[i] = regmap; |
1145 | } |
1146 | |
1147 | return 0; |
1148 | } |
1149 | |
1150 | static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, |
1151 | struct device *dev) |
1152 | { |
1153 | struct clk *clk; |
1154 | int ret; |
1155 | |
1156 | clk = devm_clk_get_optional(dev, id: "cmn_refclk_dig_div" ); |
1157 | if (IS_ERR(ptr: clk)) { |
1158 | dev_err(dev, "cmn_refclk_dig_div clock not found\n" ); |
1159 | ret = PTR_ERR(ptr: clk); |
1160 | return ret; |
1161 | } |
1162 | sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; |
1163 | |
1164 | clk = devm_clk_get_optional(dev, id: "cmn_refclk1_dig_div" ); |
1165 | if (IS_ERR(ptr: clk)) { |
1166 | dev_err(dev, "cmn_refclk1_dig_div clock not found\n" ); |
1167 | ret = PTR_ERR(ptr: clk); |
1168 | return ret; |
1169 | } |
1170 | sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; |
1171 | |
1172 | return 0; |
1173 | } |
1174 | |
1175 | static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) |
1176 | { |
1177 | struct device *dev = sp->dev; |
1178 | struct clk *clk; |
1179 | int ret; |
1180 | |
1181 | clk = devm_clk_get_optional(dev, id: "phy_clk" ); |
1182 | if (IS_ERR(ptr: clk)) { |
1183 | dev_err(dev, "failed to get clock phy_clk\n" ); |
1184 | return PTR_ERR(ptr: clk); |
1185 | } |
1186 | sp->input_clks[PHY_CLK] = clk; |
1187 | |
1188 | ret = clk_prepare_enable(clk: sp->input_clks[PHY_CLK]); |
1189 | if (ret) |
1190 | return ret; |
1191 | |
1192 | return 0; |
1193 | } |
1194 | |
1195 | static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) |
1196 | { |
1197 | int ret; |
1198 | |
1199 | ret = clk_prepare_enable(clk: sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); |
1200 | if (ret) |
1201 | return ret; |
1202 | |
1203 | ret = clk_prepare_enable(clk: sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); |
1204 | if (ret) |
1205 | goto err_pll_cmnlc1; |
1206 | |
1207 | return 0; |
1208 | |
1209 | err_pll_cmnlc1: |
1210 | clk_disable_unprepare(clk: sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); |
1211 | |
1212 | return ret; |
1213 | } |
1214 | |
1215 | static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) |
1216 | { |
1217 | clk_disable_unprepare(clk: sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); |
1218 | clk_disable_unprepare(clk: sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); |
1219 | if (!sp->already_configured) |
1220 | clk_disable_unprepare(clk: sp->input_clks[PHY_CLK]); |
1221 | } |
1222 | |
1223 | static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, |
1224 | struct device *dev) |
1225 | { |
1226 | struct reset_control *rst; |
1227 | |
1228 | rst = devm_reset_control_get_exclusive(dev, id: "sierra_reset" ); |
1229 | if (IS_ERR(ptr: rst)) { |
1230 | dev_err(dev, "failed to get reset\n" ); |
1231 | return PTR_ERR(ptr: rst); |
1232 | } |
1233 | sp->phy_rst = rst; |
1234 | |
1235 | rst = devm_reset_control_get_optional_exclusive(dev, id: "sierra_apb" ); |
1236 | if (IS_ERR(ptr: rst)) { |
1237 | dev_err(dev, "failed to get apb reset\n" ); |
1238 | return PTR_ERR(ptr: rst); |
1239 | } |
1240 | sp->apb_rst = rst; |
1241 | |
1242 | return 0; |
1243 | } |
1244 | |
1245 | static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) |
1246 | { |
1247 | const struct cdns_sierra_data *init_data = sp->init_data; |
1248 | struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; |
1249 | enum cdns_sierra_phy_type phy_t1, phy_t2; |
1250 | struct cdns_sierra_vals *phy_pma_ln_vals; |
1251 | const struct cdns_reg_pairs *reg_pairs; |
1252 | struct cdns_sierra_vals *pcs_cmn_vals; |
1253 | int i, j, node, mlane, num_lanes, ret; |
1254 | enum cdns_sierra_ssc_mode ssc; |
1255 | struct regmap *regmap; |
1256 | u32 num_regs; |
1257 | |
1258 | /* Maximum 2 links (subnodes) are supported */ |
1259 | if (sp->nsubnodes != 2) |
1260 | return -EINVAL; |
1261 | |
1262 | clk_set_rate(clk: sp->input_clks[CMN_REFCLK_DIG_DIV], rate: 25000000); |
1263 | clk_set_rate(clk: sp->input_clks[CMN_REFCLK1_DIG_DIV], rate: 25000000); |
1264 | |
1265 | /* PHY configured to use both PLL LC and LC1 */ |
1266 | regmap_field_write(field: sp->phy_pll_cfg_1, val: 0x1); |
1267 | |
1268 | phy_t1 = sp->phys[0].phy_type; |
1269 | phy_t2 = sp->phys[1].phy_type; |
1270 | |
1271 | /* |
1272 | * PHY configuration for multi-link operation is done in two steps. |
1273 | * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. |
1274 | * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe |
1275 | * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. |
1276 | * |
1277 | * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII |
1278 | * So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. |
1279 | * This will configure PHY registers associated for PCIe (i.e. first protocol) |
1280 | * involving PLLLC registers and registers for first 2 lanes of PHY. |
1281 | * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now, |
1282 | * phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as |
1283 | * [TYPE_QSGMII][TYPE_PCIE][ssc]. |
1284 | * This will configure PHY registers associated for QSGMII (i.e. second protocol) |
1285 | * involving PLLLC1 registers and registers for other 2 lanes of PHY. |
1286 | * |
1287 | * This completes the PHY configuration for multilink operation. This approach enables |
1288 | * dividing the large number of PHY register configurations into protocol specific |
1289 | * smaller groups. |
1290 | */ |
1291 | for (node = 0; node < sp->nsubnodes; node++) { |
1292 | if (node == 1) { |
1293 | /* |
1294 | * If first link with phy_t1 is configured, then configure the PHY for |
1295 | * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc]. |
1296 | */ |
1297 | swap(phy_t1, phy_t2); |
1298 | } |
1299 | |
1300 | mlane = sp->phys[node].mlane; |
1301 | ssc = sp->phys[node].ssc_mode; |
1302 | num_lanes = sp->phys[node].num_lanes; |
1303 | |
1304 | /* PHY PCS common registers configurations */ |
1305 | pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; |
1306 | if (pcs_cmn_vals) { |
1307 | reg_pairs = pcs_cmn_vals->reg_pairs; |
1308 | num_regs = pcs_cmn_vals->num_regs; |
1309 | regmap = sp->regmap_phy_pcs_common_cdb; |
1310 | for (i = 0; i < num_regs; i++) |
1311 | regmap_write(map: regmap, reg: reg_pairs[i].off, val: reg_pairs[i].val); |
1312 | } |
1313 | |
1314 | /* PHY PMA lane registers configurations */ |
1315 | phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; |
1316 | if (phy_pma_ln_vals) { |
1317 | reg_pairs = phy_pma_ln_vals->reg_pairs; |
1318 | num_regs = phy_pma_ln_vals->num_regs; |
1319 | for (i = 0; i < num_lanes; i++) { |
1320 | regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; |
1321 | for (j = 0; j < num_regs; j++) |
1322 | regmap_write(map: regmap, reg: reg_pairs[j].off, val: reg_pairs[j].val); |
1323 | } |
1324 | } |
1325 | |
1326 | /* PMA common registers configurations */ |
1327 | pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; |
1328 | if (pma_cmn_vals) { |
1329 | reg_pairs = pma_cmn_vals->reg_pairs; |
1330 | num_regs = pma_cmn_vals->num_regs; |
1331 | regmap = sp->regmap_common_cdb; |
1332 | for (i = 0; i < num_regs; i++) |
1333 | regmap_write(map: regmap, reg: reg_pairs[i].off, val: reg_pairs[i].val); |
1334 | } |
1335 | |
1336 | /* PMA lane registers configurations */ |
1337 | pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; |
1338 | if (pma_ln_vals) { |
1339 | reg_pairs = pma_ln_vals->reg_pairs; |
1340 | num_regs = pma_ln_vals->num_regs; |
1341 | for (i = 0; i < num_lanes; i++) { |
1342 | regmap = sp->regmap_lane_cdb[i + mlane]; |
1343 | for (j = 0; j < num_regs; j++) |
1344 | regmap_write(map: regmap, reg: reg_pairs[j].off, val: reg_pairs[j].val); |
1345 | } |
1346 | } |
1347 | |
1348 | if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII) |
1349 | reset_control_deassert(rstc: sp->phys[node].lnk_rst); |
1350 | } |
1351 | |
1352 | /* Take the PHY out of reset */ |
1353 | ret = reset_control_deassert(rstc: sp->phy_rst); |
1354 | if (ret) |
1355 | return ret; |
1356 | |
1357 | return 0; |
1358 | } |
1359 | |
1360 | static int cdns_sierra_phy_probe(struct platform_device *pdev) |
1361 | { |
1362 | struct cdns_sierra_phy *sp; |
1363 | struct phy_provider *phy_provider; |
1364 | struct device *dev = &pdev->dev; |
1365 | const struct cdns_sierra_data *data; |
1366 | unsigned int id_value; |
1367 | int ret, node = 0; |
1368 | void __iomem *base; |
1369 | struct device_node *dn = dev->of_node, *child; |
1370 | |
1371 | if (of_get_child_count(np: dn) == 0) |
1372 | return -ENODEV; |
1373 | |
1374 | /* Get init data for this PHY */ |
1375 | data = of_device_get_match_data(dev); |
1376 | if (!data) |
1377 | return -EINVAL; |
1378 | |
1379 | sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws, |
1380 | CDNS_SIERRA_OUTPUT_CLOCKS), |
1381 | GFP_KERNEL); |
1382 | if (!sp) |
1383 | return -ENOMEM; |
1384 | dev_set_drvdata(dev, data: sp); |
1385 | sp->dev = dev; |
1386 | sp->init_data = data; |
1387 | |
1388 | base = devm_platform_ioremap_resource(pdev, index: 0); |
1389 | if (IS_ERR(ptr: base)) { |
1390 | dev_err(dev, "missing \"reg\"\n" ); |
1391 | return PTR_ERR(ptr: base); |
1392 | } |
1393 | |
1394 | ret = cdns_regmap_init_blocks(sp, base, block_offset_shift: data->block_offset_shift, |
1395 | reg_offset_shift: data->reg_offset_shift); |
1396 | if (ret) |
1397 | return ret; |
1398 | |
1399 | ret = cdns_regfield_init(sp); |
1400 | if (ret) |
1401 | return ret; |
1402 | |
1403 | platform_set_drvdata(pdev, data: sp); |
1404 | |
1405 | ret = cdns_sierra_phy_get_clocks(sp, dev); |
1406 | if (ret) |
1407 | return ret; |
1408 | |
1409 | ret = cdns_sierra_clk_register(sp); |
1410 | if (ret) |
1411 | return ret; |
1412 | |
1413 | ret = cdns_sierra_phy_enable_clocks(sp); |
1414 | if (ret) |
1415 | goto unregister_clk; |
1416 | |
1417 | regmap_field_read(field: sp->pma_cmn_ready, val: &sp->already_configured); |
1418 | |
1419 | if (!sp->already_configured) { |
1420 | ret = cdns_sierra_phy_clk(sp); |
1421 | if (ret) |
1422 | goto clk_disable; |
1423 | |
1424 | ret = cdns_sierra_phy_get_resets(sp, dev); |
1425 | if (ret) |
1426 | goto clk_disable; |
1427 | |
1428 | /* Enable APB */ |
1429 | reset_control_deassert(rstc: sp->apb_rst); |
1430 | } |
1431 | |
1432 | /* Check that PHY is present */ |
1433 | regmap_field_read(field: sp->macro_id_type, val: &id_value); |
1434 | if (sp->init_data->id_value != id_value) { |
1435 | ret = -EINVAL; |
1436 | goto ctrl_assert; |
1437 | } |
1438 | |
1439 | sp->autoconf = of_property_read_bool(np: dn, propname: "cdns,autoconf" ); |
1440 | |
1441 | for_each_available_child_of_node(dn, child) { |
1442 | struct phy *gphy; |
1443 | |
1444 | if (!(of_node_name_eq(np: child, name: "phy" ) || |
1445 | of_node_name_eq(np: child, name: "link" ))) |
1446 | continue; |
1447 | |
1448 | sp->phys[node].lnk_rst = |
1449 | of_reset_control_array_get_exclusive(node: child); |
1450 | |
1451 | if (IS_ERR(ptr: sp->phys[node].lnk_rst)) { |
1452 | dev_err(dev, "failed to get reset %s\n" , |
1453 | child->full_name); |
1454 | ret = PTR_ERR(ptr: sp->phys[node].lnk_rst); |
1455 | of_node_put(node: child); |
1456 | goto put_control; |
1457 | } |
1458 | |
1459 | if (!sp->autoconf) { |
1460 | ret = cdns_sierra_get_optional(inst: &sp->phys[node], child); |
1461 | if (ret) { |
1462 | dev_err(dev, "missing property in node %s\n" , |
1463 | child->name); |
1464 | of_node_put(node: child); |
1465 | reset_control_put(rstc: sp->phys[node].lnk_rst); |
1466 | goto put_control; |
1467 | } |
1468 | } |
1469 | |
1470 | sp->num_lanes += sp->phys[node].num_lanes; |
1471 | |
1472 | if (!sp->already_configured) |
1473 | gphy = devm_phy_create(dev, node: child, ops: &ops); |
1474 | else |
1475 | gphy = devm_phy_create(dev, node: child, ops: &noop_ops); |
1476 | if (IS_ERR(ptr: gphy)) { |
1477 | ret = PTR_ERR(ptr: gphy); |
1478 | of_node_put(node: child); |
1479 | reset_control_put(rstc: sp->phys[node].lnk_rst); |
1480 | goto put_control; |
1481 | } |
1482 | sp->phys[node].phy = gphy; |
1483 | phy_set_drvdata(phy: gphy, data: &sp->phys[node]); |
1484 | |
1485 | node++; |
1486 | } |
1487 | sp->nsubnodes = node; |
1488 | |
1489 | if (sp->num_lanes > SIERRA_MAX_LANES) { |
1490 | ret = -EINVAL; |
1491 | dev_err(dev, "Invalid lane configuration\n" ); |
1492 | goto put_control; |
1493 | } |
1494 | |
1495 | /* If more than one subnode, configure the PHY as multilink */ |
1496 | if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) { |
1497 | ret = cdns_sierra_phy_configure_multilink(sp); |
1498 | if (ret) |
1499 | goto put_control; |
1500 | } |
1501 | |
1502 | pm_runtime_enable(dev); |
1503 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
1504 | if (IS_ERR(ptr: phy_provider)) { |
1505 | ret = PTR_ERR(ptr: phy_provider); |
1506 | goto put_control; |
1507 | } |
1508 | |
1509 | return 0; |
1510 | |
1511 | put_control: |
1512 | while (--node >= 0) |
1513 | reset_control_put(rstc: sp->phys[node].lnk_rst); |
1514 | ctrl_assert: |
1515 | if (!sp->already_configured) |
1516 | reset_control_assert(rstc: sp->apb_rst); |
1517 | clk_disable: |
1518 | cdns_sierra_phy_disable_clocks(sp); |
1519 | unregister_clk: |
1520 | cdns_sierra_clk_unregister(sp); |
1521 | return ret; |
1522 | } |
1523 | |
1524 | static void cdns_sierra_phy_remove(struct platform_device *pdev) |
1525 | { |
1526 | struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); |
1527 | int i; |
1528 | |
1529 | reset_control_assert(rstc: phy->phy_rst); |
1530 | reset_control_assert(rstc: phy->apb_rst); |
1531 | pm_runtime_disable(dev: &pdev->dev); |
1532 | |
1533 | cdns_sierra_phy_disable_clocks(sp: phy); |
1534 | /* |
1535 | * The device level resets will be put automatically. |
1536 | * Need to put the subnode resets here though. |
1537 | */ |
1538 | for (i = 0; i < phy->nsubnodes; i++) { |
1539 | reset_control_assert(rstc: phy->phys[i].lnk_rst); |
1540 | reset_control_put(rstc: phy->phys[i].lnk_rst); |
1541 | } |
1542 | |
1543 | cdns_sierra_clk_unregister(sp: phy); |
1544 | } |
1545 | |
1546 | /* SGMII PHY PMA lane configuration */ |
1547 | static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = { |
1548 | {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} |
1549 | }; |
1550 | |
1551 | static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = { |
1552 | .reg_pairs = sgmii_phy_pma_ln_regs, |
1553 | .num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs), |
1554 | }; |
1555 | |
1556 | /* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */ |
1557 | static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = { |
1558 | {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, |
1559 | {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, |
1560 | {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, |
1561 | {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, |
1562 | {0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} |
1563 | }; |
1564 | |
1565 | static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = { |
1566 | {0x688E, SIERRA_DET_STANDEC_D_PREG}, |
1567 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1568 | {0x0FFE, SIERRA_PSC_RX_A0_PREG}, |
1569 | {0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, |
1570 | {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, |
1571 | {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, |
1572 | {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, |
1573 | {0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG }, |
1574 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
1575 | {0x9702, SIERRA_DRVCTRL_BOOST_PREG}, |
1576 | {0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1577 | {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
1578 | {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
1579 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
1580 | {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, |
1581 | {0x0186, SIERRA_DEQ_GLUT0}, |
1582 | {0x0186, SIERRA_DEQ_GLUT1}, |
1583 | {0x0186, SIERRA_DEQ_GLUT2}, |
1584 | {0x0186, SIERRA_DEQ_GLUT3}, |
1585 | {0x0186, SIERRA_DEQ_GLUT4}, |
1586 | {0x0861, SIERRA_DEQ_ALUT0}, |
1587 | {0x07E0, SIERRA_DEQ_ALUT1}, |
1588 | {0x079E, SIERRA_DEQ_ALUT2}, |
1589 | {0x071D, SIERRA_DEQ_ALUT3}, |
1590 | {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, |
1591 | {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, |
1592 | {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1593 | {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1594 | {0x0033, SIERRA_DEQ_PICTRL_PREG}, |
1595 | {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
1596 | {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, |
1597 | {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1598 | {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} |
1599 | }; |
1600 | |
1601 | static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = { |
1602 | .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs, |
1603 | .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs), |
1604 | }; |
1605 | |
1606 | static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = { |
1607 | .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs, |
1608 | .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs), |
1609 | }; |
1610 | |
1611 | /* QSGMII PHY PMA lane configuration */ |
1612 | static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { |
1613 | {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} |
1614 | }; |
1615 | |
1616 | static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { |
1617 | .reg_pairs = qsgmii_phy_pma_ln_regs, |
1618 | .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), |
1619 | }; |
1620 | |
1621 | /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ |
1622 | static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { |
1623 | {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, |
1624 | {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, |
1625 | {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} |
1626 | }; |
1627 | |
1628 | static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { |
1629 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1630 | {0x0252, SIERRA_DET_STANDEC_E_PREG}, |
1631 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1632 | {0x0FFE, SIERRA_PSC_RX_A0_PREG}, |
1633 | {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, |
1634 | {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, |
1635 | {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, |
1636 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
1637 | {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1638 | {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
1639 | {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
1640 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
1641 | {0x8422, SIERRA_CTLELUT_CTRL_PREG}, |
1642 | {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, |
1643 | {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, |
1644 | {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, |
1645 | {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, |
1646 | {0x0186, SIERRA_DEQ_GLUT0}, |
1647 | {0x0186, SIERRA_DEQ_GLUT1}, |
1648 | {0x0186, SIERRA_DEQ_GLUT2}, |
1649 | {0x0186, SIERRA_DEQ_GLUT3}, |
1650 | {0x0186, SIERRA_DEQ_GLUT4}, |
1651 | {0x0861, SIERRA_DEQ_ALUT0}, |
1652 | {0x07E0, SIERRA_DEQ_ALUT1}, |
1653 | {0x079E, SIERRA_DEQ_ALUT2}, |
1654 | {0x071D, SIERRA_DEQ_ALUT3}, |
1655 | {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, |
1656 | {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, |
1657 | {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1658 | {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1659 | {0x0033, SIERRA_DEQ_PICTRL_PREG}, |
1660 | {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, |
1661 | {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
1662 | {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, |
1663 | {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1664 | {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} |
1665 | }; |
1666 | |
1667 | static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { |
1668 | .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, |
1669 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), |
1670 | }; |
1671 | |
1672 | static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { |
1673 | .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, |
1674 | .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), |
1675 | }; |
1676 | |
1677 | /* PCIE PHY PCS common configuration */ |
1678 | static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { |
1679 | {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} |
1680 | }; |
1681 | |
1682 | static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { |
1683 | .reg_pairs = pcie_phy_pcs_cmn_regs, |
1684 | .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), |
1685 | }; |
1686 | |
1687 | /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
1688 | static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { |
1689 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
1690 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
1691 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
1692 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} |
1693 | }; |
1694 | |
1695 | /* |
1696 | * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, |
1697 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
1698 | */ |
1699 | static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { |
1700 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1701 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
1702 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
1703 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
1704 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1705 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
1706 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
1707 | {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
1708 | {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
1709 | {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
1710 | {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1711 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
1712 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
1713 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
1714 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
1715 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
1716 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
1717 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
1718 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
1719 | {0x0041, SIERRA_DEQ_GLUT0}, |
1720 | {0x0082, SIERRA_DEQ_GLUT1}, |
1721 | {0x00C3, SIERRA_DEQ_GLUT2}, |
1722 | {0x0145, SIERRA_DEQ_GLUT3}, |
1723 | {0x0186, SIERRA_DEQ_GLUT4}, |
1724 | {0x09E7, SIERRA_DEQ_ALUT0}, |
1725 | {0x09A6, SIERRA_DEQ_ALUT1}, |
1726 | {0x0965, SIERRA_DEQ_ALUT2}, |
1727 | {0x08E3, SIERRA_DEQ_ALUT3}, |
1728 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
1729 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
1730 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
1731 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
1732 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
1733 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
1734 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
1735 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
1736 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1737 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1738 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1739 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
1740 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1741 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1742 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
1743 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1744 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
1745 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
1746 | }; |
1747 | |
1748 | static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { |
1749 | .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, |
1750 | .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), |
1751 | }; |
1752 | |
1753 | static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { |
1754 | .reg_pairs = ml_pcie_100_no_ssc_ln_regs, |
1755 | .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), |
1756 | }; |
1757 | |
1758 | /* |
1759 | * TI J721E: |
1760 | * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, |
1761 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
1762 | */ |
1763 | static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { |
1764 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1765 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
1766 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
1767 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
1768 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1769 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
1770 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
1771 | {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
1772 | {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
1773 | {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
1774 | {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1775 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
1776 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
1777 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
1778 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
1779 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
1780 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
1781 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
1782 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
1783 | {0x0041, SIERRA_DEQ_GLUT0}, |
1784 | {0x0082, SIERRA_DEQ_GLUT1}, |
1785 | {0x00C3, SIERRA_DEQ_GLUT2}, |
1786 | {0x0145, SIERRA_DEQ_GLUT3}, |
1787 | {0x0186, SIERRA_DEQ_GLUT4}, |
1788 | {0x09E7, SIERRA_DEQ_ALUT0}, |
1789 | {0x09A6, SIERRA_DEQ_ALUT1}, |
1790 | {0x0965, SIERRA_DEQ_ALUT2}, |
1791 | {0x08E3, SIERRA_DEQ_ALUT3}, |
1792 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
1793 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
1794 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
1795 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
1796 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
1797 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
1798 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
1799 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
1800 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1801 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1802 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1803 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
1804 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1805 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1806 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
1807 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1808 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
1809 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, |
1810 | {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} |
1811 | }; |
1812 | |
1813 | static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = { |
1814 | .reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs, |
1815 | .num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs), |
1816 | }; |
1817 | |
1818 | /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
1819 | static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { |
1820 | {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, |
1821 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
1822 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
1823 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
1824 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
1825 | {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, |
1826 | {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, |
1827 | {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, |
1828 | {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, |
1829 | {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, |
1830 | {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} |
1831 | }; |
1832 | |
1833 | /* |
1834 | * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, |
1835 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
1836 | */ |
1837 | static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { |
1838 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1839 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
1840 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
1841 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
1842 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1843 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
1844 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
1845 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
1846 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
1847 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
1848 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
1849 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1850 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
1851 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
1852 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
1853 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
1854 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
1855 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
1856 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
1857 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
1858 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
1859 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
1860 | {0x0041, SIERRA_DEQ_GLUT0}, |
1861 | {0x0082, SIERRA_DEQ_GLUT1}, |
1862 | {0x00C3, SIERRA_DEQ_GLUT2}, |
1863 | {0x0145, SIERRA_DEQ_GLUT3}, |
1864 | {0x0186, SIERRA_DEQ_GLUT4}, |
1865 | {0x09E7, SIERRA_DEQ_ALUT0}, |
1866 | {0x09A6, SIERRA_DEQ_ALUT1}, |
1867 | {0x0965, SIERRA_DEQ_ALUT2}, |
1868 | {0x08E3, SIERRA_DEQ_ALUT3}, |
1869 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
1870 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
1871 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
1872 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
1873 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
1874 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
1875 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
1876 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
1877 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1878 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1879 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1880 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
1881 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1882 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1883 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
1884 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1885 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
1886 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
1887 | }; |
1888 | |
1889 | static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { |
1890 | .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, |
1891 | .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), |
1892 | }; |
1893 | |
1894 | static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { |
1895 | .reg_pairs = ml_pcie_100_int_ssc_ln_regs, |
1896 | .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), |
1897 | }; |
1898 | |
1899 | /* |
1900 | * TI J721E: |
1901 | * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, |
1902 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
1903 | */ |
1904 | static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { |
1905 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1906 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
1907 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
1908 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
1909 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1910 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
1911 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
1912 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
1913 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
1914 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
1915 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
1916 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1917 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
1918 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
1919 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
1920 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
1921 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
1922 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
1923 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
1924 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
1925 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
1926 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
1927 | {0x0041, SIERRA_DEQ_GLUT0}, |
1928 | {0x0082, SIERRA_DEQ_GLUT1}, |
1929 | {0x00C3, SIERRA_DEQ_GLUT2}, |
1930 | {0x0145, SIERRA_DEQ_GLUT3}, |
1931 | {0x0186, SIERRA_DEQ_GLUT4}, |
1932 | {0x09E7, SIERRA_DEQ_ALUT0}, |
1933 | {0x09A6, SIERRA_DEQ_ALUT1}, |
1934 | {0x0965, SIERRA_DEQ_ALUT2}, |
1935 | {0x08E3, SIERRA_DEQ_ALUT3}, |
1936 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
1937 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
1938 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
1939 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
1940 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
1941 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
1942 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
1943 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
1944 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
1945 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
1946 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
1947 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
1948 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
1949 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
1950 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
1951 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
1952 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
1953 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, |
1954 | {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} |
1955 | }; |
1956 | |
1957 | static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = { |
1958 | .reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs, |
1959 | .num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs), |
1960 | }; |
1961 | |
1962 | /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ |
1963 | static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { |
1964 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
1965 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
1966 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
1967 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
1968 | {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
1969 | }; |
1970 | |
1971 | /* |
1972 | * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, |
1973 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
1974 | */ |
1975 | static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { |
1976 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
1977 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
1978 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
1979 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
1980 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
1981 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
1982 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
1983 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
1984 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
1985 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
1986 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
1987 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
1988 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
1989 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
1990 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
1991 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
1992 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
1993 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
1994 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
1995 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
1996 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
1997 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
1998 | {0x0041, SIERRA_DEQ_GLUT0}, |
1999 | {0x0082, SIERRA_DEQ_GLUT1}, |
2000 | {0x00C3, SIERRA_DEQ_GLUT2}, |
2001 | {0x0145, SIERRA_DEQ_GLUT3}, |
2002 | {0x0186, SIERRA_DEQ_GLUT4}, |
2003 | {0x09E7, SIERRA_DEQ_ALUT0}, |
2004 | {0x09A6, SIERRA_DEQ_ALUT1}, |
2005 | {0x0965, SIERRA_DEQ_ALUT2}, |
2006 | {0x08E3, SIERRA_DEQ_ALUT3}, |
2007 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
2008 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
2009 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
2010 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
2011 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
2012 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
2013 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
2014 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
2015 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2016 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2017 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2018 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2019 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2020 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2021 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
2022 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2023 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2024 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
2025 | }; |
2026 | |
2027 | static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { |
2028 | .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, |
2029 | .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), |
2030 | }; |
2031 | |
2032 | static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { |
2033 | .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, |
2034 | .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), |
2035 | }; |
2036 | |
2037 | /* |
2038 | * TI J721E: |
2039 | * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, |
2040 | * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz |
2041 | */ |
2042 | static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { |
2043 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
2044 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
2045 | {0x0004, SIERRA_PSC_LN_A3_PREG}, |
2046 | {0x0004, SIERRA_PSC_LN_A4_PREG}, |
2047 | {0x0004, SIERRA_PSC_LN_IDLE_PREG}, |
2048 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
2049 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
2050 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
2051 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
2052 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
2053 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
2054 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2055 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
2056 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
2057 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
2058 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
2059 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2060 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
2061 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
2062 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
2063 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
2064 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
2065 | {0x0041, SIERRA_DEQ_GLUT0}, |
2066 | {0x0082, SIERRA_DEQ_GLUT1}, |
2067 | {0x00C3, SIERRA_DEQ_GLUT2}, |
2068 | {0x0145, SIERRA_DEQ_GLUT3}, |
2069 | {0x0186, SIERRA_DEQ_GLUT4}, |
2070 | {0x09E7, SIERRA_DEQ_ALUT0}, |
2071 | {0x09A6, SIERRA_DEQ_ALUT1}, |
2072 | {0x0965, SIERRA_DEQ_ALUT2}, |
2073 | {0x08E3, SIERRA_DEQ_ALUT3}, |
2074 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
2075 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
2076 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
2077 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
2078 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
2079 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
2080 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
2081 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
2082 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2083 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2084 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2085 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2086 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2087 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2088 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
2089 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2090 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2091 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, |
2092 | {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} |
2093 | }; |
2094 | |
2095 | static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = { |
2096 | .reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs, |
2097 | .num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs), |
2098 | }; |
2099 | |
2100 | /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ |
2101 | static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { |
2102 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
2103 | {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
2104 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
2105 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} |
2106 | }; |
2107 | |
2108 | /* refclk100MHz_32b_PCIe_ln_no_ssc */ |
2109 | static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { |
2110 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
2111 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
2112 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
2113 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
2114 | {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
2115 | {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
2116 | {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
2117 | {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2118 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
2119 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
2120 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2121 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
2122 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
2123 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
2124 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
2125 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
2126 | {0x0041, SIERRA_DEQ_GLUT0}, |
2127 | {0x0082, SIERRA_DEQ_GLUT1}, |
2128 | {0x00C3, SIERRA_DEQ_GLUT2}, |
2129 | {0x0145, SIERRA_DEQ_GLUT3}, |
2130 | {0x0186, SIERRA_DEQ_GLUT4}, |
2131 | {0x09E7, SIERRA_DEQ_ALUT0}, |
2132 | {0x09A6, SIERRA_DEQ_ALUT1}, |
2133 | {0x0965, SIERRA_DEQ_ALUT2}, |
2134 | {0x08E3, SIERRA_DEQ_ALUT3}, |
2135 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
2136 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
2137 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
2138 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
2139 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
2140 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
2141 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
2142 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
2143 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2144 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2145 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2146 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2147 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2148 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2149 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
2150 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2151 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2152 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
2153 | }; |
2154 | |
2155 | static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { |
2156 | .reg_pairs = cdns_pcie_cmn_regs_no_ssc, |
2157 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), |
2158 | }; |
2159 | |
2160 | static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { |
2161 | .reg_pairs = cdns_pcie_ln_regs_no_ssc, |
2162 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), |
2163 | }; |
2164 | |
2165 | /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ |
2166 | static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { |
2167 | {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, |
2168 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
2169 | {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
2170 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
2171 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
2172 | {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, |
2173 | {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, |
2174 | {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, |
2175 | {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, |
2176 | {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, |
2177 | {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} |
2178 | }; |
2179 | |
2180 | /* refclk100MHz_32b_PCIe_ln_int_ssc */ |
2181 | static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { |
2182 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
2183 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
2184 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
2185 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
2186 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
2187 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
2188 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
2189 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
2190 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2191 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
2192 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
2193 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
2194 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
2195 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2196 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
2197 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
2198 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
2199 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
2200 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
2201 | {0x0041, SIERRA_DEQ_GLUT0}, |
2202 | {0x0082, SIERRA_DEQ_GLUT1}, |
2203 | {0x00C3, SIERRA_DEQ_GLUT2}, |
2204 | {0x0145, SIERRA_DEQ_GLUT3}, |
2205 | {0x0186, SIERRA_DEQ_GLUT4}, |
2206 | {0x09E7, SIERRA_DEQ_ALUT0}, |
2207 | {0x09A6, SIERRA_DEQ_ALUT1}, |
2208 | {0x0965, SIERRA_DEQ_ALUT2}, |
2209 | {0x08E3, SIERRA_DEQ_ALUT3}, |
2210 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
2211 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
2212 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
2213 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
2214 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
2215 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
2216 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
2217 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
2218 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2219 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2220 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2221 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2222 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2223 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2224 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
2225 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2226 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2227 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
2228 | }; |
2229 | |
2230 | static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { |
2231 | .reg_pairs = cdns_pcie_cmn_regs_int_ssc, |
2232 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), |
2233 | }; |
2234 | |
2235 | static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { |
2236 | .reg_pairs = cdns_pcie_ln_regs_int_ssc, |
2237 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), |
2238 | }; |
2239 | |
2240 | /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ |
2241 | static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { |
2242 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
2243 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
2244 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, |
2245 | {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
2246 | {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
2247 | }; |
2248 | |
2249 | /* refclk100MHz_32b_PCIe_ln_ext_ssc */ |
2250 | static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { |
2251 | {0xFC08, SIERRA_DET_STANDEC_A_PREG}, |
2252 | {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, |
2253 | {0x1555, SIERRA_DFE_BIASTRIM_PREG}, |
2254 | {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, |
2255 | {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
2256 | {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, |
2257 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, |
2258 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
2259 | {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2260 | {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, |
2261 | {0x9800, SIERRA_RX_CTLE_CAL_PREG}, |
2262 | {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
2263 | {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
2264 | {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2265 | {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
2266 | {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
2267 | {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
2268 | {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
2269 | {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, |
2270 | {0x0041, SIERRA_DEQ_GLUT0}, |
2271 | {0x0082, SIERRA_DEQ_GLUT1}, |
2272 | {0x00C3, SIERRA_DEQ_GLUT2}, |
2273 | {0x0145, SIERRA_DEQ_GLUT3}, |
2274 | {0x0186, SIERRA_DEQ_GLUT4}, |
2275 | {0x09E7, SIERRA_DEQ_ALUT0}, |
2276 | {0x09A6, SIERRA_DEQ_ALUT1}, |
2277 | {0x0965, SIERRA_DEQ_ALUT2}, |
2278 | {0x08E3, SIERRA_DEQ_ALUT3}, |
2279 | {0x00FA, SIERRA_DEQ_DFETAP0}, |
2280 | {0x00FA, SIERRA_DEQ_DFETAP1}, |
2281 | {0x00FA, SIERRA_DEQ_DFETAP2}, |
2282 | {0x00FA, SIERRA_DEQ_DFETAP3}, |
2283 | {0x00FA, SIERRA_DEQ_DFETAP4}, |
2284 | {0x000F, SIERRA_DEQ_PRECUR_PREG}, |
2285 | {0x0280, SIERRA_DEQ_POSTCUR_PREG}, |
2286 | {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, |
2287 | {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2288 | {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2289 | {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, |
2290 | {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2291 | {0x002B, SIERRA_CPI_TRIM_PREG}, |
2292 | {0x0003, SIERRA_EPI_CTRL_PREG}, |
2293 | {0x803F, SIERRA_SDFILT_H2L_A_PREG}, |
2294 | {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2295 | {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2296 | {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} |
2297 | }; |
2298 | |
2299 | static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { |
2300 | .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, |
2301 | .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), |
2302 | }; |
2303 | |
2304 | static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { |
2305 | .reg_pairs = cdns_pcie_ln_regs_ext_ssc, |
2306 | .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), |
2307 | }; |
2308 | |
2309 | /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ |
2310 | static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { |
2311 | {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, |
2312 | {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
2313 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
2314 | {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} |
2315 | }; |
2316 | |
2317 | /* refclk100MHz_20b_USB_ln_ext_ssc */ |
2318 | static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { |
2319 | {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, |
2320 | {0x000F, SIERRA_DET_STANDEC_B_PREG}, |
2321 | {0x55A5, SIERRA_DET_STANDEC_C_PREG}, |
2322 | {0x69ad, SIERRA_DET_STANDEC_D_PREG}, |
2323 | {0x0241, SIERRA_DET_STANDEC_E_PREG}, |
2324 | {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, |
2325 | {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, |
2326 | {0xCF00, SIERRA_PSM_DIAG_PREG}, |
2327 | {0x001F, SIERRA_PSC_TX_A0_PREG}, |
2328 | {0x0007, SIERRA_PSC_TX_A1_PREG}, |
2329 | {0x0003, SIERRA_PSC_TX_A2_PREG}, |
2330 | {0x0003, SIERRA_PSC_TX_A3_PREG}, |
2331 | {0x0FFF, SIERRA_PSC_RX_A0_PREG}, |
2332 | {0x0003, SIERRA_PSC_RX_A1_PREG}, |
2333 | {0x0003, SIERRA_PSC_RX_A2_PREG}, |
2334 | {0x0001, SIERRA_PSC_RX_A3_PREG}, |
2335 | {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, |
2336 | {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, |
2337 | {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, |
2338 | {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, |
2339 | {0x2512, SIERRA_DFE_BIASTRIM_PREG}, |
2340 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
2341 | {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, |
2342 | {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, |
2343 | {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2344 | {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
2345 | {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, |
2346 | {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
2347 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
2348 | {0x0000, SIERRA_CREQ_SPARE_PREG}, |
2349 | {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, |
2350 | {0x8452, SIERRA_CTLELUT_CTRL_PREG}, |
2351 | {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, |
2352 | {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, |
2353 | {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, |
2354 | {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, |
2355 | {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2356 | {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, |
2357 | {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, |
2358 | {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, |
2359 | {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, |
2360 | {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, |
2361 | {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, |
2362 | {0x0014, SIERRA_DEQ_GLUT0}, |
2363 | {0x0014, SIERRA_DEQ_GLUT1}, |
2364 | {0x0014, SIERRA_DEQ_GLUT2}, |
2365 | {0x0014, SIERRA_DEQ_GLUT3}, |
2366 | {0x0014, SIERRA_DEQ_GLUT4}, |
2367 | {0x0014, SIERRA_DEQ_GLUT5}, |
2368 | {0x0014, SIERRA_DEQ_GLUT6}, |
2369 | {0x0014, SIERRA_DEQ_GLUT7}, |
2370 | {0x0014, SIERRA_DEQ_GLUT8}, |
2371 | {0x0014, SIERRA_DEQ_GLUT9}, |
2372 | {0x0014, SIERRA_DEQ_GLUT10}, |
2373 | {0x0014, SIERRA_DEQ_GLUT11}, |
2374 | {0x0014, SIERRA_DEQ_GLUT12}, |
2375 | {0x0014, SIERRA_DEQ_GLUT13}, |
2376 | {0x0014, SIERRA_DEQ_GLUT14}, |
2377 | {0x0014, SIERRA_DEQ_GLUT15}, |
2378 | {0x0014, SIERRA_DEQ_GLUT16}, |
2379 | {0x0BAE, SIERRA_DEQ_ALUT0}, |
2380 | {0x0AEB, SIERRA_DEQ_ALUT1}, |
2381 | {0x0A28, SIERRA_DEQ_ALUT2}, |
2382 | {0x0965, SIERRA_DEQ_ALUT3}, |
2383 | {0x08A2, SIERRA_DEQ_ALUT4}, |
2384 | {0x07DF, SIERRA_DEQ_ALUT5}, |
2385 | {0x071C, SIERRA_DEQ_ALUT6}, |
2386 | {0x0659, SIERRA_DEQ_ALUT7}, |
2387 | {0x0596, SIERRA_DEQ_ALUT8}, |
2388 | {0x0514, SIERRA_DEQ_ALUT9}, |
2389 | {0x0492, SIERRA_DEQ_ALUT10}, |
2390 | {0x0410, SIERRA_DEQ_ALUT11}, |
2391 | {0x038E, SIERRA_DEQ_ALUT12}, |
2392 | {0x030C, SIERRA_DEQ_ALUT13}, |
2393 | {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, |
2394 | {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, |
2395 | {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, |
2396 | {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, |
2397 | {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2398 | {0x0033, SIERRA_DEQ_PICTRL_PREG}, |
2399 | {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, |
2400 | {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, |
2401 | {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, |
2402 | {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
2403 | {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, |
2404 | {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, |
2405 | {0x000F, SIERRA_LFPSFILT_NS_PREG}, |
2406 | {0x0009, SIERRA_LFPSFILT_RD_PREG}, |
2407 | {0x0001, SIERRA_LFPSFILT_MP_PREG}, |
2408 | {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, |
2409 | {0x8013, SIERRA_SDFILT_H2L_A_PREG}, |
2410 | {0x8009, SIERRA_SDFILT_L2H_PREG}, |
2411 | {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, |
2412 | {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, |
2413 | {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} |
2414 | }; |
2415 | |
2416 | static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { |
2417 | .reg_pairs = cdns_usb_cmn_regs_ext_ssc, |
2418 | .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), |
2419 | }; |
2420 | |
2421 | static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { |
2422 | .reg_pairs = cdns_usb_ln_regs_ext_ssc, |
2423 | .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), |
2424 | }; |
2425 | |
2426 | /* SGMII PHY common configuration */ |
2427 | static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = { |
2428 | {0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG}, |
2429 | {0x6000, SIERRA_CMN_REFRCV_PREG}, |
2430 | {0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG}, |
2431 | {0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG}, |
2432 | {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, |
2433 | {0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG}, |
2434 | {0x8103, SIERRA_CMN_PLLLC_CLK0_PREG}, |
2435 | {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, |
2436 | {0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG}, |
2437 | {0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG}, |
2438 | {0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, |
2439 | {0x0000, SIERRA_CMN_PLLLC_INIT_PREG}, |
2440 | {0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG}, |
2441 | {0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG}, |
2442 | {0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG}, |
2443 | {0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG}, |
2444 | }; |
2445 | |
2446 | static struct cdns_sierra_vals sgmii_cmn_vals = { |
2447 | .reg_pairs = sgmii_pma_cmn_vals, |
2448 | .num_regs = ARRAY_SIZE(sgmii_pma_cmn_vals), |
2449 | }; |
2450 | |
2451 | /* SGMII PHY lane configuration */ |
2452 | static const struct cdns_reg_pairs sgmii_ln_regs[] = { |
2453 | {0x691E, SIERRA_DET_STANDEC_D_PREG}, |
2454 | {0x0FFE, SIERRA_PSC_RX_A0_PREG}, |
2455 | {0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, |
2456 | {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, |
2457 | {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, |
2458 | {0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, |
2459 | {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, |
2460 | {0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, |
2461 | {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, |
2462 | {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, |
2463 | {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, |
2464 | {0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG}, |
2465 | {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, |
2466 | {0x15A2, SIERRA_LN_SPARE_REG_PREG}, |
2467 | {0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG}, |
2468 | {0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG}, |
2469 | {0x2206, SIERRA_DEQ_TAU_CTRL2_PREG}, |
2470 | {0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG}, |
2471 | {0x8001, SIERRA_CREQ_SPARE_PREG}, |
2472 | {0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG}, |
2473 | {0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG}, |
2474 | {0x0101, SIERRA_DEQ_GLUT9}, |
2475 | {0x0101, SIERRA_DEQ_GLUT10}, |
2476 | {0x0101, SIERRA_DEQ_GLUT11}, |
2477 | {0x0101, SIERRA_DEQ_GLUT12}, |
2478 | {0x0000, SIERRA_DEQ_GLUT13}, |
2479 | {0x0000, SIERRA_DEQ_GLUT16}, |
2480 | {0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG}, |
2481 | {0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG}, |
2482 | {0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG}, |
2483 | {0x0101, SIERRA_DEQ_ALUT8}, |
2484 | {0x0101, SIERRA_DEQ_ALUT9}, |
2485 | {0x0100, SIERRA_DEQ_ALUT10}, |
2486 | {0x0000, SIERRA_OEPH_EN_CTRL_PREG}, |
2487 | {0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG}, |
2488 | {0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, |
2489 | {0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG}, |
2490 | }; |
2491 | |
2492 | static struct cdns_sierra_vals sgmii_pma_ln_vals = { |
2493 | .reg_pairs = sgmii_ln_regs, |
2494 | .num_regs = ARRAY_SIZE(sgmii_ln_regs), |
2495 | }; |
2496 | |
2497 | static const struct cdns_sierra_data cdns_map_sierra = { |
2498 | .id_value = SIERRA_MACRO_ID, |
2499 | .block_offset_shift = 0x2, |
2500 | .reg_offset_shift = 0x2, |
2501 | .pcs_cmn_vals = { |
2502 | [TYPE_PCIE] = { |
2503 | [TYPE_NONE] = { |
2504 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2505 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2506 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2507 | }, |
2508 | [TYPE_SGMII] = { |
2509 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2510 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2511 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2512 | }, |
2513 | [TYPE_QSGMII] = { |
2514 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2515 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2516 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2517 | }, |
2518 | }, |
2519 | }, |
2520 | .pma_cmn_vals = { |
2521 | [TYPE_PCIE] = { |
2522 | [TYPE_NONE] = { |
2523 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
2524 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, |
2525 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
2526 | }, |
2527 | [TYPE_SGMII] = { |
2528 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
2529 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
2530 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
2531 | }, |
2532 | [TYPE_QSGMII] = { |
2533 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
2534 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
2535 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
2536 | }, |
2537 | }, |
2538 | [TYPE_USB] = { |
2539 | [TYPE_NONE] = { |
2540 | [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, |
2541 | }, |
2542 | }, |
2543 | [TYPE_SGMII] = { |
2544 | [TYPE_NONE] = { |
2545 | [NO_SSC] = &sgmii_cmn_vals, |
2546 | }, |
2547 | [TYPE_PCIE] = { |
2548 | [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2549 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2550 | [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2551 | }, |
2552 | }, |
2553 | [TYPE_QSGMII] = { |
2554 | [TYPE_PCIE] = { |
2555 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2556 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2557 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2558 | }, |
2559 | }, |
2560 | }, |
2561 | .pma_ln_vals = { |
2562 | [TYPE_PCIE] = { |
2563 | [TYPE_NONE] = { |
2564 | [NO_SSC] = &pcie_100_no_ssc_ln_vals, |
2565 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, |
2566 | [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, |
2567 | }, |
2568 | [TYPE_SGMII] = { |
2569 | [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, |
2570 | [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, |
2571 | [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, |
2572 | }, |
2573 | [TYPE_QSGMII] = { |
2574 | [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, |
2575 | [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, |
2576 | [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, |
2577 | }, |
2578 | }, |
2579 | [TYPE_USB] = { |
2580 | [TYPE_NONE] = { |
2581 | [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, |
2582 | }, |
2583 | }, |
2584 | [TYPE_SGMII] = { |
2585 | [TYPE_NONE] = { |
2586 | [NO_SSC] = &sgmii_pma_ln_vals, |
2587 | }, |
2588 | [TYPE_PCIE] = { |
2589 | [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2590 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2591 | [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2592 | }, |
2593 | }, |
2594 | [TYPE_QSGMII] = { |
2595 | [TYPE_PCIE] = { |
2596 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2597 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2598 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2599 | }, |
2600 | }, |
2601 | }, |
2602 | }; |
2603 | |
2604 | static const struct cdns_sierra_data cdns_ti_map_sierra = { |
2605 | .id_value = SIERRA_MACRO_ID, |
2606 | .block_offset_shift = 0x0, |
2607 | .reg_offset_shift = 0x1, |
2608 | .pcs_cmn_vals = { |
2609 | [TYPE_PCIE] = { |
2610 | [TYPE_NONE] = { |
2611 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2612 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2613 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2614 | }, |
2615 | [TYPE_SGMII] = { |
2616 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2617 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2618 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2619 | }, |
2620 | [TYPE_QSGMII] = { |
2621 | [NO_SSC] = &pcie_phy_pcs_cmn_vals, |
2622 | [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2623 | [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, |
2624 | }, |
2625 | }, |
2626 | }, |
2627 | .phy_pma_ln_vals = { |
2628 | [TYPE_SGMII] = { |
2629 | [TYPE_PCIE] = { |
2630 | [NO_SSC] = &sgmii_phy_pma_ln_vals, |
2631 | [EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals, |
2632 | [INTERNAL_SSC] = &sgmii_phy_pma_ln_vals, |
2633 | }, |
2634 | }, |
2635 | [TYPE_QSGMII] = { |
2636 | [TYPE_PCIE] = { |
2637 | [NO_SSC] = &qsgmii_phy_pma_ln_vals, |
2638 | [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, |
2639 | [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, |
2640 | }, |
2641 | }, |
2642 | }, |
2643 | .pma_cmn_vals = { |
2644 | [TYPE_PCIE] = { |
2645 | [TYPE_NONE] = { |
2646 | [NO_SSC] = &pcie_100_no_ssc_cmn_vals, |
2647 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, |
2648 | [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, |
2649 | }, |
2650 | [TYPE_SGMII] = { |
2651 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
2652 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
2653 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
2654 | }, |
2655 | [TYPE_QSGMII] = { |
2656 | [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, |
2657 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, |
2658 | [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, |
2659 | }, |
2660 | }, |
2661 | [TYPE_USB] = { |
2662 | [TYPE_NONE] = { |
2663 | [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, |
2664 | }, |
2665 | }, |
2666 | [TYPE_SGMII] = { |
2667 | [TYPE_PCIE] = { |
2668 | [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2669 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2670 | [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, |
2671 | }, |
2672 | }, |
2673 | [TYPE_QSGMII] = { |
2674 | [TYPE_PCIE] = { |
2675 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2676 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2677 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, |
2678 | }, |
2679 | }, |
2680 | }, |
2681 | .pma_ln_vals = { |
2682 | [TYPE_PCIE] = { |
2683 | [TYPE_NONE] = { |
2684 | [NO_SSC] = &pcie_100_no_ssc_ln_vals, |
2685 | [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, |
2686 | [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, |
2687 | }, |
2688 | [TYPE_SGMII] = { |
2689 | [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, |
2690 | [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, |
2691 | [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, |
2692 | }, |
2693 | [TYPE_QSGMII] = { |
2694 | [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, |
2695 | [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, |
2696 | [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, |
2697 | }, |
2698 | }, |
2699 | [TYPE_USB] = { |
2700 | [TYPE_NONE] = { |
2701 | [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, |
2702 | }, |
2703 | }, |
2704 | [TYPE_SGMII] = { |
2705 | [TYPE_PCIE] = { |
2706 | [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2707 | [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2708 | [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, |
2709 | }, |
2710 | }, |
2711 | [TYPE_QSGMII] = { |
2712 | [TYPE_PCIE] = { |
2713 | [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2714 | [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2715 | [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, |
2716 | }, |
2717 | }, |
2718 | }, |
2719 | }; |
2720 | |
2721 | static const struct of_device_id cdns_sierra_id_table[] = { |
2722 | { |
2723 | .compatible = "cdns,sierra-phy-t0" , |
2724 | .data = &cdns_map_sierra, |
2725 | }, |
2726 | { |
2727 | .compatible = "ti,sierra-phy-t0" , |
2728 | .data = &cdns_ti_map_sierra, |
2729 | }, |
2730 | {} |
2731 | }; |
2732 | MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); |
2733 | |
2734 | static struct platform_driver cdns_sierra_driver = { |
2735 | .probe = cdns_sierra_phy_probe, |
2736 | .remove_new = cdns_sierra_phy_remove, |
2737 | .driver = { |
2738 | .name = "cdns-sierra-phy" , |
2739 | .of_match_table = cdns_sierra_id_table, |
2740 | }, |
2741 | }; |
2742 | module_platform_driver(cdns_sierra_driver); |
2743 | |
2744 | MODULE_ALIAS("platform:cdns_sierra" ); |
2745 | MODULE_AUTHOR("Cadence Design Systems" ); |
2746 | MODULE_DESCRIPTION("CDNS sierra phy driver" ); |
2747 | MODULE_LICENSE("GPL v2" ); |
2748 | |