1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2022 MediaTek Inc. |
4 | * Copyright (c) 2022 BayLibre, SAS |
5 | */ |
6 | |
7 | #ifndef _MTK_HDMI_PHY_8195_H |
8 | #define _MTK_HDMI_PHY_8195_H |
9 | |
10 | #include <linux/clk.h> |
11 | #include <linux/clk-provider.h> |
12 | #include <linux/types.h> |
13 | |
14 | #define PCW_DECIMAL_WIDTH 24 |
15 | #define PLL_PREDIV 1 |
16 | #define PLL_FBKDIV_HS3 1 |
17 | |
18 | #define HDMI20_CLK_CFG 0x70 |
19 | #define REG_TXC_DIV GENMASK(31, 30) |
20 | |
21 | #define HDMI_1_CFG_0 0x00 |
22 | #define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5) |
23 | #define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20) |
24 | #define RG_HDMITX21_DRV_EN GENMASK(27, 24) |
25 | #define RG_HDMITX21_SER_EN GENMASK(31, 28) |
26 | |
27 | #define HDMI_1_CFG_1 0x04 |
28 | #define RG_HDMITX21_DRV_IBIAS_D0 GENMASK(19, 14) |
29 | #define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20) |
30 | #define RG_HDMITX21_DRV_IBIAS_D2 GENMASK(31, 26) |
31 | |
32 | #define HDMI_1_CFG_10 0x40 |
33 | #define RG_HDMITXPLL_REF_CK_SEL GENMASK(2, 1) |
34 | #define RG_HDMITX21_VREF_SEL BIT(4) |
35 | #define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10) |
36 | #define RG_HDMITX21_BIAS_PE_BG_VREF_SEL GENMASK(16, 15) |
37 | #define RG_HDMITX21_BG_PWD BIT(20) |
38 | |
39 | #define HDMI_1_CFG_2 0x08 |
40 | #define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8) |
41 | #define RG_HDMITX21_DRV_IMP_D1_EN1 GENMASK(19, 14) |
42 | #define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20) |
43 | #define RG_HDMITX21_DRV_IMP_CLK_EN1 GENMASK(31, 26) |
44 | |
45 | #define HDMI_1_CFG_3 0x0c |
46 | #define RG_HDMITX21_CKLDO_EN BIT(3) |
47 | #define RG_HDMITX21_SLDOLPF_EN BIT(7) |
48 | #define RG_HDMITX21_SLDO_EN GENMASK(11, 8) |
49 | |
50 | #define HDMI_1_CFG_6 0x18 |
51 | #define RG_HDMITX21_D2_DRV_OP_EN BIT(8) |
52 | #define RG_HDMITX21_D1_DRV_OP_EN BIT(9) |
53 | #define RG_HDMITX21_D0_DRV_OP_EN BIT(10) |
54 | #define RG_HDMITX21_CK_DRV_OP_EN BIT(11) |
55 | #define RG_HDMITX21_FRL_EN BIT(12) |
56 | #define RG_HDMITX21_FRL_CK_EN BIT(13) |
57 | #define RG_HDMITX21_FRL_D0_EN BIT(14) |
58 | #define RG_HDMITX21_FRL_D1_EN BIT(15) |
59 | #define RG_HDMITX21_FRL_D2_EN BIT(16) |
60 | #define RG_HDMITX21_INTR_CAL GENMASK(22, 18) |
61 | #define RG_HDMITX21_TX_POSDIV GENMASK(27, 26) |
62 | #define RG_HDMITX21_TX_POSDIV_EN BIT(28) |
63 | #define RG_HDMITX21_BIAS_EN BIT(29) |
64 | |
65 | #define HDMI_1_CFG_9 0x24 |
66 | #define RG_HDMITX21_SLDO_VREF_SEL GENMASK(5, 4) |
67 | |
68 | #define HDMI_1_PLL_CFG_0 0x44 |
69 | #define RG_HDMITXPLL_HREN GENMASK(13, 12) |
70 | #define RG_HDMITXPLL_IBAND_FIX_EN BIT(24) |
71 | #define RG_HDMITXPLL_LVR_SEL GENMASK(27, 26) |
72 | #define RG_HDMITXPLL_BP2 BIT(30) |
73 | #define RG_HDMITXPLL_TCL_EN BIT(31) |
74 | |
75 | #define HDMI_1_PLL_CFG_1 0x48 |
76 | #define RG_HDMITXPLL_RESERVE_BIT1_0 GENMASK(1, 0) |
77 | #define RG_HDMITXPLL_RESERVE_BIT3_2 GENMASK(3, 2) |
78 | #define RG_HDMITXPLL_RESERVE_BIT12_11 GENMASK(12, 11) |
79 | #define RG_HDMITXPLL_RESERVE_BIT13 BIT(13) |
80 | #define RG_HDMITXPLL_RESERVE_BIT14 BIT(14) |
81 | |
82 | #define HDMI_1_PLL_CFG_2 0x4c |
83 | #define RG_HDMITXPLL_BC GENMASK(28, 27) |
84 | #define RG_HDMITXPLL_IC GENMASK(26, 22) |
85 | #define RG_HDMITXPLL_BR GENMASK(21, 19) |
86 | #define RG_HDMITXPLL_IR GENMASK(18, 14) |
87 | #define RG_HDMITXPLL_BP GENMASK(13, 10) |
88 | #define RG_HDMITXPLL_HIKVCO BIT(29) |
89 | #define RG_HDMITXPLL_PWD BIT(31) |
90 | |
91 | #define HDMI_1_PLL_CFG_3 0x50 |
92 | #define RG_HDMITXPLL_FBKDIV_LOW GENMASK(31, 0) |
93 | |
94 | #define HDMI_1_PLL_CFG_4 0x54 |
95 | #define DA_HDMITXPLL_ISO_EN BIT(1) |
96 | #define DA_HDMITXPLL_PWR_ON BIT(2) |
97 | #define RG_HDMITXPLL_POSDIV_DIV3_CTRL BIT(21) |
98 | #define RG_HDMITXPLL_POSDIV GENMASK(23, 22) |
99 | #define RG_HDMITXPLL_DIV_CTRL GENMASK(25, 24) |
100 | #define RG_HDMITXPLL_PREDIV GENMASK(29, 28) |
101 | #define RG_HDMITXPLL_FBKDIV_HIGH BIT(31) |
102 | |
103 | #define HDMI_ANA_CTL 0x7c |
104 | #define REG_ANA_HDMI20_FIFO_EN BIT(16) |
105 | |
106 | #define HDMI_CTL_3 0xcc |
107 | #define REG_HDMITXPLL_DIV GENMASK(4, 0) |
108 | #define REG_HDMITX_REF_XTAL_SEL BIT(7) |
109 | #define REG_HDMITX_REF_RESPLL_SEL BIT(9) |
110 | #define REG_PIXEL_CLOCK_SEL BIT(10) |
111 | #define REG_HDMITX_PIXEL_CLOCK BIT(23) |
112 | |
113 | #endif /* MTK_HDMI_PHY_8195_H */ |
114 | |