1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | /* |
3 | * Copyright (c) 2019 MediaTek Inc. |
4 | * Author: Jitao Shi <jitao.shi@mediatek.com> |
5 | */ |
6 | |
7 | #ifndef _MTK_MIPI_TX_H |
8 | #define _MTK_MIPI_TX_H |
9 | |
10 | #include <linux/clk.h> |
11 | #include <linux/clk-provider.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/module.h> |
14 | #include <linux/nvmem-consumer.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/phy/phy.h> |
17 | #include <linux/slab.h> |
18 | |
19 | struct mtk_mipitx_data { |
20 | const u32 mppll_preserve; |
21 | const struct clk_ops *mipi_tx_clk_ops; |
22 | void (*mipi_tx_enable_signal)(struct phy *phy); |
23 | void (*mipi_tx_disable_signal)(struct phy *phy); |
24 | }; |
25 | |
26 | struct mtk_mipi_tx { |
27 | struct device *dev; |
28 | void __iomem *regs; |
29 | u32 data_rate; |
30 | u32 mipitx_drive; |
31 | u32 rt_code[5]; |
32 | const struct mtk_mipitx_data *driver_data; |
33 | struct clk_hw pll_hw; |
34 | }; |
35 | |
36 | struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw); |
37 | int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
38 | unsigned long parent_rate); |
39 | unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, |
40 | unsigned long parent_rate); |
41 | |
42 | extern const struct mtk_mipitx_data mt2701_mipitx_data; |
43 | extern const struct mtk_mipitx_data mt8173_mipitx_data; |
44 | extern const struct mtk_mipitx_data mt8183_mipitx_data; |
45 | |
46 | #endif |
47 |