1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/delay.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/regulator/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include "xusb.h"
19
20/* FUSE USB_CALIB registers */
21#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22#define HS_CURR_LEVEL_PAD_MASK 0x3f
23#define HS_TERM_RANGE_ADJ_SHIFT 7
24#define HS_TERM_RANGE_ADJ_MASK 0xf
25#define HS_SQUELCH_SHIFT 29
26#define HS_SQUELCH_MASK 0x7
27
28#define RPD_CTRL_SHIFT 0
29#define RPD_CTRL_MASK 0x1f
30
31/* XUSB PADCTL registers */
32#define XUSB_PADCTL_USB2_PAD_MUX 0x4
33#define USB2_PORT_SHIFT(x) ((x) * 2)
34#define USB2_PORT_MASK 0x3
35#define PORT_XUSB 1
36#define HSIC_PORT_SHIFT(x) ((x) + 20)
37#define HSIC_PORT_MASK 0x1
38#define PORT_HSIC 0
39
40#define XUSB_PADCTL_USB2_PORT_CAP 0x8
41#define XUSB_PADCTL_SS_PORT_CAP 0xc
42#define PORTX_CAP_SHIFT(x) ((x) * 4)
43#define PORT_CAP_MASK 0x3
44#define PORT_CAP_DISABLED 0x0
45#define PORT_CAP_HOST 0x1
46#define PORT_CAP_DEVICE 0x2
47#define PORT_CAP_OTG 0x3
48
49#define XUSB_PADCTL_ELPG_PROGRAM 0x20
50#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56#define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
61
62#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63#define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64#define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65#define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66#define XUSB_PADCTL_SS_PORT_CFG 0x2c
67#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68#define PORTX_SPEED_SUPPORT_MASK (0x3)
69#define PORT_SPEED_SUPPORT_GEN1 (0x0)
70
71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72#define HS_CURR_LEVEL(x) ((x) & 0x3f)
73#define TERM_SEL BIT(25)
74#define USB2_OTG_PD BIT(26)
75#define USB2_OTG_PD2 BIT(27)
76#define USB2_OTG_PD2_OVRD_EN BIT(28)
77#define USB2_OTG_PD_ZI BIT(29)
78
79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80#define USB2_OTG_PD_DR BIT(2)
81#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82#define RPD_CTRL(x) (((x) & 0x1f) << 26)
83
84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85#define BIAS_PAD_PD BIT(11)
86#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
87
88#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91#define USB2_PD_TRK BIT(26)
92#define USB2_TRK_COMPLETED BIT(31)
93
94#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c
95#define USB2_TRK_HW_MODE BIT(0)
96#define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31)
97
98#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
99#define HSIC_PD_TX_DATA0 BIT(1)
100#define HSIC_PD_TX_STROBE BIT(3)
101#define HSIC_PD_RX_DATA0 BIT(4)
102#define HSIC_PD_RX_STROBE BIT(6)
103#define HSIC_PD_ZI_DATA0 BIT(7)
104#define HSIC_PD_ZI_STROBE BIT(9)
105#define HSIC_RPD_DATA0 BIT(13)
106#define HSIC_RPD_STROBE BIT(15)
107#define HSIC_RPU_DATA0 BIT(16)
108#define HSIC_RPU_STROBE BIT(18)
109
110#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
111#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
112#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
113#define HSIC_PD_TRK BIT(19)
114
115#define USB2_VBUS_ID 0x360
116#define VBUS_OVERRIDE BIT(14)
117#define ID_OVERRIDE(x) (((x) & 0xf) << 18)
118#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
119#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
120
121/* XUSB AO registers */
122#define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
123#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
124#define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
125
126#define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
127#define CLR_WALK_PTR BIT(0)
128#define CAP_CFG BIT(1)
129#define CLR_WAKE_ALARM BIT(3)
130
131#define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
132#define HSIC_CLR_WALK_PTR BIT(0)
133#define HSIC_CLR_WAKE_ALARM BIT(3)
134#define HSIC_CAP_CFG BIT(4)
135
136#define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
137#define SPEED(x) ((x) & 0x3)
138#define UTMI_HS SPEED(0)
139#define UTMI_FS SPEED(1)
140#define UTMI_LS SPEED(2)
141#define UTMI_RST SPEED(3)
142
143#define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
144#define MODE(x) ((x) & 0x1)
145#define MODE_HS MODE(0)
146#define MODE_RST MODE(1)
147
148#define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4)
149
150#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
151#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
152#define FAKE_USBOP_VAL BIT(0)
153#define FAKE_USBON_VAL BIT(1)
154#define FAKE_USBOP_EN BIT(2)
155#define FAKE_USBON_EN BIT(3)
156#define FAKE_STROBE_VAL BIT(0)
157#define FAKE_DATA_VAL BIT(1)
158#define FAKE_STROBE_EN BIT(2)
159#define FAKE_DATA_EN BIT(3)
160#define WAKE_WALK_EN BIT(14)
161#define MASTER_ENABLE BIT(15)
162#define LINEVAL_WALK_EN BIT(16)
163#define WAKE_VAL(x) (((x) & 0xf) << 17)
164#define WAKE_VAL_NONE WAKE_VAL(12)
165#define WAKE_VAL_ANY WAKE_VAL(15)
166#define WAKE_VAL_DS10 WAKE_VAL(2)
167#define LINE_WAKEUP_EN BIT(21)
168#define MASTER_CFG_SEL BIT(22)
169
170#define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
171/* phase A */
172#define USBOP_RPD_A BIT(0)
173#define USBON_RPD_A BIT(1)
174#define AP_A BIT(4)
175#define AN_A BIT(5)
176#define HIGHZ_A BIT(6)
177#define MASTER_ENABLE_A BIT(7)
178/* phase B */
179#define USBOP_RPD_B BIT(8)
180#define USBON_RPD_B BIT(9)
181#define AP_B BIT(12)
182#define AN_B BIT(13)
183#define HIGHZ_B BIT(14)
184#define MASTER_ENABLE_B BIT(15)
185/* phase C */
186#define USBOP_RPD_C BIT(16)
187#define USBON_RPD_C BIT(17)
188#define AP_C BIT(20)
189#define AN_C BIT(21)
190#define HIGHZ_C BIT(22)
191#define MASTER_ENABLE_C BIT(23)
192/* phase D */
193#define USBOP_RPD_D BIT(24)
194#define USBON_RPD_D BIT(25)
195#define AP_D BIT(28)
196#define AN_D BIT(29)
197#define HIGHZ_D BIT(30)
198#define MASTER_ENABLE_D BIT(31)
199#define MASTER_ENABLE_B_C_D \
200 (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
201
202#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
203/* phase A */
204#define RPD_STROBE_A BIT(0)
205#define RPD_DATA0_A BIT(1)
206#define RPU_STROBE_A BIT(2)
207#define RPU_DATA0_A BIT(3)
208/* phase B */
209#define RPD_STROBE_B BIT(8)
210#define RPD_DATA0_B BIT(9)
211#define RPU_STROBE_B BIT(10)
212#define RPU_DATA0_B BIT(11)
213/* phase C */
214#define RPD_STROBE_C BIT(16)
215#define RPD_DATA0_C BIT(17)
216#define RPU_STROBE_C BIT(18)
217#define RPU_DATA0_C BIT(19)
218/* phase D */
219#define RPD_STROBE_D BIT(24)
220#define RPD_DATA0_D BIT(25)
221#define RPU_STROBE_D BIT(26)
222#define RPU_DATA0_D BIT(27)
223
224#define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
225#define FSLS_USE_XUSB_AO BIT(3)
226#define TRK_CTRL_USE_XUSB_AO BIT(4)
227#define RPD_CTRL_USE_XUSB_AO BIT(5)
228#define RPU_USE_XUSB_AO BIT(6)
229#define VREG_USE_XUSB_AO BIT(7)
230#define USBOP_VAL_PD BIT(8)
231#define USBON_VAL_PD BIT(9)
232#define E_DPD_OVRD_EN BIT(10)
233#define E_DPD_OVRD_VAL BIT(11)
234
235#define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
236#define STROBE_VAL_PD BIT(0)
237#define DATA0_VAL_PD BIT(1)
238#define USE_XUSB_AO BIT(4)
239
240#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
241 { \
242 .name = _name, \
243 .offset = _offset, \
244 .shift = _shift, \
245 .mask = _mask, \
246 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
247 .funcs = tegra186_##_type##_functions, \
248 }
249
250struct tegra_xusb_fuse_calibration {
251 u32 *hs_curr_level;
252 u32 hs_squelch;
253 u32 hs_term_range_adj;
254 u32 rpd_ctrl;
255};
256
257struct tegra186_xusb_padctl_context {
258 u32 vbus_id;
259 u32 usb2_pad_mux;
260 u32 usb2_port_cap;
261 u32 ss_port_cap;
262};
263
264struct tegra186_xusb_padctl {
265 struct tegra_xusb_padctl base;
266 void __iomem *ao_regs;
267
268 struct tegra_xusb_fuse_calibration calib;
269
270 /* UTMI bias and tracking */
271 struct clk *usb2_trk_clk;
272 unsigned int bias_pad_enable;
273
274 /* padctl context */
275 struct tegra186_xusb_padctl_context context;
276};
277
278static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
279{
280 writel(val: value, addr: priv->ao_regs + offset);
281}
282
283static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
284{
285 return readl(addr: priv->ao_regs + offset);
286}
287
288static inline struct tegra186_xusb_padctl *
289to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
290{
291 return container_of(padctl, struct tegra186_xusb_padctl, base);
292}
293
294/* USB 2.0 UTMI PHY support */
295static struct tegra_xusb_lane *
296tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
297 unsigned int index)
298{
299 struct tegra_xusb_usb2_lane *usb2;
300 int err;
301
302 usb2 = kzalloc(size: sizeof(*usb2), GFP_KERNEL);
303 if (!usb2)
304 return ERR_PTR(error: -ENOMEM);
305
306 INIT_LIST_HEAD(list: &usb2->base.list);
307 usb2->base.soc = &pad->soc->lanes[index];
308 usb2->base.index = index;
309 usb2->base.pad = pad;
310 usb2->base.np = np;
311
312 err = tegra_xusb_lane_parse_dt(lane: &usb2->base, np);
313 if (err < 0) {
314 kfree(objp: usb2);
315 return ERR_PTR(error: err);
316 }
317
318 return &usb2->base;
319}
320
321static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
322{
323 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
324
325 kfree(objp: usb2);
326}
327
328static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
329 enum usb_device_speed speed)
330{
331 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
332 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
333 unsigned int index = lane->index;
334 u32 value;
335
336 mutex_lock(&padctl->lock);
337
338 /* ensure sleepwalk logic is disabled */
339 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
340 value &= ~MASTER_ENABLE;
341 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
342
343 /* ensure sleepwalk logics are in low power mode */
344 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
345 value |= MASTER_CFG_SEL;
346 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
347
348 /* set debounce time */
349 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
350 value &= ~UTMIP_LINE_DEB_CNT(~0);
351 value |= UTMIP_LINE_DEB_CNT(1);
352 ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
353
354 /* ensure fake events of sleepwalk logic are desiabled */
355 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
356 value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
357 FAKE_USBOP_EN | FAKE_USBON_EN);
358 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
359
360 /* ensure wake events of sleepwalk logic are not latched */
361 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
362 value &= ~LINE_WAKEUP_EN;
363 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
364
365 /* disable wake event triggers of sleepwalk logic */
366 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
367 value &= ~WAKE_VAL(~0);
368 value |= WAKE_VAL_NONE;
369 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
370
371 /* power down the line state detectors of the pad */
372 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
373 value |= (USBOP_VAL_PD | USBON_VAL_PD);
374 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
375
376 /* save state per speed */
377 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
378 value &= ~SPEED(~0);
379
380 switch (speed) {
381 case USB_SPEED_HIGH:
382 value |= UTMI_HS;
383 break;
384
385 case USB_SPEED_FULL:
386 value |= UTMI_FS;
387 break;
388
389 case USB_SPEED_LOW:
390 value |= UTMI_LS;
391 break;
392
393 default:
394 value |= UTMI_RST;
395 break;
396 }
397
398 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
399
400 /* enable the trigger of the sleepwalk logic */
401 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
402 value |= LINEVAL_WALK_EN;
403 value &= ~WAKE_WALK_EN;
404 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
405
406 /* reset the walk pointer and clear the alarm of the sleepwalk logic,
407 * as well as capture the configuration of the USB2.0 pad
408 */
409 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
410 value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
411 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
412
413 /* setup the pull-ups and pull-downs of the signals during the four
414 * stages of sleepwalk.
415 * if device is connected, program sleepwalk logic to maintain a J and
416 * keep driving K upon seeing remote wake.
417 */
418 value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
419 value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
420
421 switch (speed) {
422 case USB_SPEED_HIGH:
423 case USB_SPEED_FULL:
424 /* J state: D+/D- = high/low, K state: D+/D- = low/high */
425 value |= HIGHZ_A;
426 value |= AP_A;
427 value |= AN_B | AN_C | AN_D;
428 if (padctl->soc->supports_lp_cfg_en)
429 value |= MASTER_ENABLE_B_C_D;
430 break;
431
432 case USB_SPEED_LOW:
433 /* J state: D+/D- = low/high, K state: D+/D- = high/low */
434 value |= HIGHZ_A;
435 value |= AN_A;
436 value |= AP_B | AP_C | AP_D;
437 if (padctl->soc->supports_lp_cfg_en)
438 value |= MASTER_ENABLE_B_C_D;
439 break;
440
441 default:
442 value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
443 break;
444 }
445
446 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
447
448 /* power up the line state detectors of the pad */
449 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
450 value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
451 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
452
453 usleep_range(min: 150, max: 200);
454
455 /* switch the electric control of the USB2.0 pad to XUSB_AO */
456 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
457 value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
458 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
459 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
460
461 /* set the wake signaling trigger events */
462 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
463 value &= ~WAKE_VAL(~0);
464 value |= WAKE_VAL_ANY;
465 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
466
467 /* enable the wake detection */
468 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
469 value |= MASTER_ENABLE | LINE_WAKEUP_EN;
470 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471
472 mutex_unlock(lock: &padctl->lock);
473
474 return 0;
475}
476
477static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
478{
479 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
480 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
481 unsigned int index = lane->index;
482 u32 value;
483
484 mutex_lock(&padctl->lock);
485
486 /* disable the wake detection */
487 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
488 value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
489 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
490
491 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */
492 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
493 value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
494 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
495 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
496
497 /* disable wake event triggers of sleepwalk logic */
498 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
499 value &= ~WAKE_VAL(~0);
500 value |= WAKE_VAL_NONE;
501 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
502
503 if (padctl->soc->supports_lp_cfg_en) {
504 /* disable the four stages of sleepwalk */
505 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index));
506 value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D);
507 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
508 }
509
510 /* power down the line state detectors of the port */
511 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
512 value |= USBOP_VAL_PD | USBON_VAL_PD;
513 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
514
515 /* clear alarm of the sleepwalk logic */
516 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
517 value |= CLR_WAKE_ALARM;
518 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
519
520 mutex_unlock(lock: &padctl->lock);
521
522 return 0;
523}
524
525static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
526{
527 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
528 unsigned int index = lane->index;
529 u32 value;
530
531 mutex_lock(&padctl->lock);
532
533 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
534 value &= ~ALL_WAKE_EVENTS;
535 value |= USB2_PORT_WAKEUP_EVENT(index);
536 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
537
538 usleep_range(min: 10, max: 20);
539
540 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
541 value &= ~ALL_WAKE_EVENTS;
542 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
543 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
544
545 mutex_unlock(lock: &padctl->lock);
546
547 return 0;
548}
549
550static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
551{
552 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
553 unsigned int index = lane->index;
554 u32 value;
555
556 mutex_lock(&padctl->lock);
557
558 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
559 value &= ~ALL_WAKE_EVENTS;
560 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
561 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
562
563 usleep_range(min: 10, max: 20);
564
565 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
566 value &= ~ALL_WAKE_EVENTS;
567 value |= USB2_PORT_WAKEUP_EVENT(index);
568 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
569
570 mutex_unlock(lock: &padctl->lock);
571
572 return 0;
573}
574
575static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
576{
577 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
578 unsigned int index = lane->index;
579 u32 value;
580
581 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
582 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
583 (value & USB2_PORT_WAKEUP_EVENT(index)))
584 return true;
585
586 return false;
587}
588
589static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
590 .probe = tegra186_usb2_lane_probe,
591 .remove = tegra186_usb2_lane_remove,
592 .enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
593 .disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
594 .enable_phy_wake = tegra186_utmi_enable_phy_wake,
595 .disable_phy_wake = tegra186_utmi_disable_phy_wake,
596 .remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
597};
598
599static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
600{
601 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
602 struct device *dev = padctl->dev;
603 u32 value;
604 int err;
605
606 mutex_lock(&padctl->lock);
607
608 if (priv->bias_pad_enable++ > 0) {
609 mutex_unlock(lock: &padctl->lock);
610 return;
611 }
612
613 err = clk_prepare_enable(clk: priv->usb2_trk_clk);
614 if (err < 0)
615 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
616
617 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
618 value &= ~USB2_TRK_START_TIMER(~0);
619 value |= USB2_TRK_START_TIMER(0x1e);
620 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
621 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
622 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
623
624 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
625 value &= ~BIAS_PAD_PD;
626 value &= ~HS_SQUELCH_LEVEL(~0);
627 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
628 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
629
630 udelay(1);
631
632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 value &= ~USB2_PD_TRK;
634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
635
636 if (padctl->soc->poll_trk_completed) {
637 err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
638 USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, us: 100);
639 if (err) {
640 /* The failure with polling on trk complete will not
641 * cause the failure of powering on the bias pad.
642 */
643 dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err);
644 }
645
646 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
647 value |= USB2_TRK_COMPLETED;
648 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
649 } else {
650 udelay(100);
651 }
652
653 if (padctl->soc->trk_hw_mode) {
654 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
655 value |= USB2_TRK_HW_MODE;
656 value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE;
657 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
658 } else {
659 clk_disable_unprepare(clk: priv->usb2_trk_clk);
660 }
661
662 mutex_unlock(lock: &padctl->lock);
663}
664
665static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
666{
667 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
668 u32 value;
669
670 mutex_lock(&padctl->lock);
671
672 if (WARN_ON(priv->bias_pad_enable == 0)) {
673 mutex_unlock(lock: &padctl->lock);
674 return;
675 }
676
677 if (--priv->bias_pad_enable > 0) {
678 mutex_unlock(lock: &padctl->lock);
679 return;
680 }
681
682 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
683 value |= USB2_PD_TRK;
684 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
685
686 if (padctl->soc->trk_hw_mode) {
687 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
688 value &= ~USB2_TRK_HW_MODE;
689 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
690 clk_disable_unprepare(clk: priv->usb2_trk_clk);
691 }
692
693 mutex_unlock(lock: &padctl->lock);
694}
695
696static void tegra186_utmi_pad_power_on(struct phy *phy)
697{
698 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
699 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
700 struct tegra_xusb_usb2_port *port;
701 struct device *dev = padctl->dev;
702 unsigned int index = lane->index;
703 u32 value;
704
705 if (!phy)
706 return;
707
708 port = tegra_xusb_find_usb2_port(padctl, index);
709 if (!port) {
710 dev_err(dev, "no port found for USB2 lane %u\n", index);
711 return;
712 }
713
714 dev_dbg(dev, "power on UTMI pad %u\n", index);
715
716 tegra186_utmi_bias_pad_power_on(padctl);
717
718 udelay(2);
719
720 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
721 value &= ~USB2_OTG_PD;
722 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
723
724 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
725 value &= ~USB2_OTG_PD_DR;
726 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
727}
728
729static void tegra186_utmi_pad_power_down(struct phy *phy)
730{
731 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
732 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
733 unsigned int index = lane->index;
734 u32 value;
735
736 if (!phy)
737 return;
738
739 dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
740
741 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
742 value |= USB2_OTG_PD;
743 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
744
745 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
746 value |= USB2_OTG_PD_DR;
747 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
748
749 udelay(2);
750
751 tegra186_utmi_bias_pad_power_off(padctl);
752}
753
754static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
755 bool status)
756{
757 u32 value;
758
759 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
760
761 value = padctl_readl(padctl, USB2_VBUS_ID);
762
763 if (status) {
764 value |= VBUS_OVERRIDE;
765 value &= ~ID_OVERRIDE(~0);
766 value |= ID_OVERRIDE_FLOATING;
767 } else {
768 value &= ~VBUS_OVERRIDE;
769 }
770
771 padctl_writel(padctl, value, USB2_VBUS_ID);
772
773 return 0;
774}
775
776static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
777 bool status)
778{
779 u32 value;
780
781 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
782
783 value = padctl_readl(padctl, USB2_VBUS_ID);
784
785 if (status) {
786 if (value & VBUS_OVERRIDE) {
787 value &= ~VBUS_OVERRIDE;
788 padctl_writel(padctl, value, USB2_VBUS_ID);
789 usleep_range(min: 1000, max: 2000);
790
791 value = padctl_readl(padctl, USB2_VBUS_ID);
792 }
793
794 value &= ~ID_OVERRIDE(~0);
795 value |= ID_OVERRIDE_GROUNDED;
796 } else {
797 value &= ~ID_OVERRIDE(~0);
798 value |= ID_OVERRIDE_FLOATING;
799 }
800
801 padctl_writel(padctl, value, USB2_VBUS_ID);
802
803 return 0;
804}
805
806static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
807 int submode)
808{
809 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
810 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
811 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
812 index: lane->index);
813 int err = 0;
814
815 mutex_lock(&padctl->lock);
816
817 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
818
819 if (mode == PHY_MODE_USB_OTG) {
820 if (submode == USB_ROLE_HOST) {
821 tegra186_xusb_padctl_id_override(padctl, status: true);
822
823 err = regulator_enable(regulator: port->supply);
824 } else if (submode == USB_ROLE_DEVICE) {
825 tegra186_xusb_padctl_vbus_override(padctl, status: true);
826 } else if (submode == USB_ROLE_NONE) {
827 /*
828 * When port is peripheral only or role transitions to
829 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
830 * enabled.
831 */
832 if (regulator_is_enabled(regulator: port->supply))
833 regulator_disable(regulator: port->supply);
834
835 tegra186_xusb_padctl_id_override(padctl, status: false);
836 tegra186_xusb_padctl_vbus_override(padctl, status: false);
837 }
838 }
839
840 mutex_unlock(lock: &padctl->lock);
841
842 return err;
843}
844
845static int tegra186_utmi_phy_power_on(struct phy *phy)
846{
847 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
848 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
849 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
850 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
851 struct tegra_xusb_usb2_port *port;
852 unsigned int index = lane->index;
853 struct device *dev = padctl->dev;
854 u32 value;
855
856 port = tegra_xusb_find_usb2_port(padctl, index);
857 if (!port) {
858 dev_err(dev, "no port found for USB2 lane %u\n", index);
859 return -ENODEV;
860 }
861
862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
863 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
864 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
865 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
866
867 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
868 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
869
870 if (port->mode == USB_DR_MODE_UNKNOWN)
871 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
872 else if (port->mode == USB_DR_MODE_PERIPHERAL)
873 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
874 else if (port->mode == USB_DR_MODE_HOST)
875 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
876 else if (port->mode == USB_DR_MODE_OTG)
877 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
878
879 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
880
881 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
882 value &= ~USB2_OTG_PD_ZI;
883 value |= TERM_SEL;
884 value &= ~HS_CURR_LEVEL(~0);
885
886 if (usb2->hs_curr_level_offset) {
887 int hs_current_level;
888
889 hs_current_level = (int)priv->calib.hs_curr_level[index] +
890 usb2->hs_curr_level_offset;
891
892 if (hs_current_level < 0)
893 hs_current_level = 0;
894 if (hs_current_level > 0x3f)
895 hs_current_level = 0x3f;
896
897 value |= HS_CURR_LEVEL(hs_current_level);
898 } else {
899 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
900 }
901
902 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
903
904 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
905 value &= ~TERM_RANGE_ADJ(~0);
906 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
907 value &= ~RPD_CTRL(~0);
908 value |= RPD_CTRL(priv->calib.rpd_ctrl);
909 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
910
911 tegra186_utmi_pad_power_on(phy);
912
913 return 0;
914}
915
916static int tegra186_utmi_phy_power_off(struct phy *phy)
917{
918 tegra186_utmi_pad_power_down(phy);
919
920 return 0;
921}
922
923static int tegra186_utmi_phy_init(struct phy *phy)
924{
925 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
926 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
927 struct tegra_xusb_usb2_port *port;
928 unsigned int index = lane->index;
929 struct device *dev = padctl->dev;
930 int err;
931
932 port = tegra_xusb_find_usb2_port(padctl, index);
933 if (!port) {
934 dev_err(dev, "no port found for USB2 lane %u\n", index);
935 return -ENODEV;
936 }
937
938 if (port->supply && port->mode == USB_DR_MODE_HOST) {
939 err = regulator_enable(regulator: port->supply);
940 if (err) {
941 dev_err(dev, "failed to enable port %u VBUS: %d\n",
942 index, err);
943 return err;
944 }
945 }
946
947 return 0;
948}
949
950static int tegra186_utmi_phy_exit(struct phy *phy)
951{
952 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
953 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
954 struct tegra_xusb_usb2_port *port;
955 unsigned int index = lane->index;
956 struct device *dev = padctl->dev;
957 int err;
958
959 port = tegra_xusb_find_usb2_port(padctl, index);
960 if (!port) {
961 dev_err(dev, "no port found for USB2 lane %u\n", index);
962 return -ENODEV;
963 }
964
965 if (port->supply && port->mode == USB_DR_MODE_HOST) {
966 err = regulator_disable(regulator: port->supply);
967 if (err) {
968 dev_err(dev, "failed to disable port %u VBUS: %d\n",
969 index, err);
970 return err;
971 }
972 }
973
974 return 0;
975}
976
977static const struct phy_ops utmi_phy_ops = {
978 .init = tegra186_utmi_phy_init,
979 .exit = tegra186_utmi_phy_exit,
980 .power_on = tegra186_utmi_phy_power_on,
981 .power_off = tegra186_utmi_phy_power_off,
982 .set_mode = tegra186_utmi_phy_set_mode,
983 .owner = THIS_MODULE,
984};
985
986static struct tegra_xusb_pad *
987tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
988 const struct tegra_xusb_pad_soc *soc,
989 struct device_node *np)
990{
991 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
992 struct tegra_xusb_usb2_pad *usb2;
993 struct tegra_xusb_pad *pad;
994 int err;
995
996 usb2 = kzalloc(size: sizeof(*usb2), GFP_KERNEL);
997 if (!usb2)
998 return ERR_PTR(error: -ENOMEM);
999
1000 pad = &usb2->base;
1001 pad->ops = &tegra186_usb2_lane_ops;
1002 pad->soc = soc;
1003
1004 err = tegra_xusb_pad_init(pad, padctl, np);
1005 if (err < 0) {
1006 kfree(objp: usb2);
1007 goto out;
1008 }
1009
1010 priv->usb2_trk_clk = devm_clk_get(dev: &pad->dev, id: "trk");
1011 if (IS_ERR(ptr: priv->usb2_trk_clk)) {
1012 err = PTR_ERR(ptr: priv->usb2_trk_clk);
1013 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
1014 goto unregister;
1015 }
1016
1017 err = tegra_xusb_pad_register(pad, ops: &utmi_phy_ops);
1018 if (err < 0)
1019 goto unregister;
1020
1021 dev_set_drvdata(dev: &pad->dev, data: pad);
1022
1023 return pad;
1024
1025unregister:
1026 device_unregister(dev: &pad->dev);
1027out:
1028 return ERR_PTR(error: err);
1029}
1030
1031static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
1032{
1033 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1034
1035 kfree(objp: usb2);
1036}
1037
1038static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
1039 .probe = tegra186_usb2_pad_probe,
1040 .remove = tegra186_usb2_pad_remove,
1041};
1042
1043static const char * const tegra186_usb2_functions[] = {
1044 "xusb",
1045};
1046
1047static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
1048{
1049 return 0;
1050}
1051
1052static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
1053{
1054}
1055
1056static struct tegra_xusb_lane *
1057tegra186_usb2_port_map(struct tegra_xusb_port *port)
1058{
1059 return tegra_xusb_find_lane(padctl: port->padctl, name: "usb2", index: port->index);
1060}
1061
1062static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1063 .release = tegra_xusb_usb2_port_release,
1064 .remove = tegra_xusb_usb2_port_remove,
1065 .enable = tegra186_usb2_port_enable,
1066 .disable = tegra186_usb2_port_disable,
1067 .map = tegra186_usb2_port_map,
1068};
1069
1070/* SuperSpeed PHY support */
1071static struct tegra_xusb_lane *
1072tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1073 unsigned int index)
1074{
1075 struct tegra_xusb_usb3_lane *usb3;
1076 int err;
1077
1078 usb3 = kzalloc(size: sizeof(*usb3), GFP_KERNEL);
1079 if (!usb3)
1080 return ERR_PTR(error: -ENOMEM);
1081
1082 INIT_LIST_HEAD(list: &usb3->base.list);
1083 usb3->base.soc = &pad->soc->lanes[index];
1084 usb3->base.index = index;
1085 usb3->base.pad = pad;
1086 usb3->base.np = np;
1087
1088 err = tegra_xusb_lane_parse_dt(lane: &usb3->base, np);
1089 if (err < 0) {
1090 kfree(objp: usb3);
1091 return ERR_PTR(error: err);
1092 }
1093
1094 return &usb3->base;
1095}
1096
1097static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1098{
1099 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1100
1101 kfree(objp: usb3);
1102}
1103
1104static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1105 enum usb_device_speed speed)
1106{
1107 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1108 unsigned int index = lane->index;
1109 u32 value;
1110
1111 mutex_lock(&padctl->lock);
1112
1113 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1114 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1115 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1116
1117 usleep_range(min: 100, max: 200);
1118
1119 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1120 value |= SSPX_ELPG_CLAMP_EN(index);
1121 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1122
1123 usleep_range(min: 250, max: 350);
1124
1125 mutex_unlock(lock: &padctl->lock);
1126
1127 return 0;
1128}
1129
1130static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1131{
1132 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1133 unsigned int index = lane->index;
1134 u32 value;
1135
1136 mutex_lock(&padctl->lock);
1137
1138 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1139 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1141
1142 usleep_range(min: 100, max: 200);
1143
1144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1145 value &= ~SSPX_ELPG_CLAMP_EN(index);
1146 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1147
1148 mutex_unlock(lock: &padctl->lock);
1149
1150 return 0;
1151}
1152
1153static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1154{
1155 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1156 unsigned int index = lane->index;
1157 u32 value;
1158
1159 mutex_lock(&padctl->lock);
1160
1161 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1162 value &= ~ALL_WAKE_EVENTS;
1163 value |= SS_PORT_WAKEUP_EVENT(index);
1164 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1165
1166 usleep_range(min: 10, max: 20);
1167
1168 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1169 value &= ~ALL_WAKE_EVENTS;
1170 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1171 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1172
1173 mutex_unlock(lock: &padctl->lock);
1174
1175 return 0;
1176}
1177
1178static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1179{
1180 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1181 unsigned int index = lane->index;
1182 u32 value;
1183
1184 mutex_lock(&padctl->lock);
1185
1186 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1187 value &= ~ALL_WAKE_EVENTS;
1188 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1189 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1190
1191 usleep_range(min: 10, max: 20);
1192
1193 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1194 value &= ~ALL_WAKE_EVENTS;
1195 value |= SS_PORT_WAKEUP_EVENT(index);
1196 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1197
1198 mutex_unlock(lock: &padctl->lock);
1199
1200 return 0;
1201}
1202
1203static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1204{
1205 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1206 unsigned int index = lane->index;
1207 u32 value;
1208
1209 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1210 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1211 return true;
1212
1213 return false;
1214}
1215
1216static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1217 .probe = tegra186_usb3_lane_probe,
1218 .remove = tegra186_usb3_lane_remove,
1219 .enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1220 .disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1221 .enable_phy_wake = tegra186_usb3_enable_phy_wake,
1222 .disable_phy_wake = tegra186_usb3_disable_phy_wake,
1223 .remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1224};
1225
1226static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1227{
1228 return 0;
1229}
1230
1231static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1232{
1233}
1234
1235static struct tegra_xusb_lane *
1236tegra186_usb3_port_map(struct tegra_xusb_port *port)
1237{
1238 return tegra_xusb_find_lane(padctl: port->padctl, name: "usb3", index: port->index);
1239}
1240
1241static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1242 .release = tegra_xusb_usb3_port_release,
1243 .enable = tegra186_usb3_port_enable,
1244 .disable = tegra186_usb3_port_disable,
1245 .map = tegra186_usb3_port_map,
1246};
1247
1248static int tegra186_usb3_phy_power_on(struct phy *phy)
1249{
1250 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1251 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1252 struct tegra_xusb_usb3_port *port;
1253 struct tegra_xusb_usb2_port *usb2;
1254 unsigned int index = lane->index;
1255 struct device *dev = padctl->dev;
1256 u32 value;
1257
1258 port = tegra_xusb_find_usb3_port(padctl, index);
1259 if (!port) {
1260 dev_err(dev, "no port found for USB3 lane %u\n", index);
1261 return -ENODEV;
1262 }
1263
1264 usb2 = tegra_xusb_find_usb2_port(padctl, index: port->port);
1265 if (!usb2) {
1266 dev_err(dev, "no companion port found for USB3 lane %u\n",
1267 index);
1268 return -ENODEV;
1269 }
1270
1271 mutex_lock(&padctl->lock);
1272
1273 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1274 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1275
1276 if (usb2->mode == USB_DR_MODE_UNKNOWN)
1277 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1278 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1279 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1280 else if (usb2->mode == USB_DR_MODE_HOST)
1281 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1282 else if (usb2->mode == USB_DR_MODE_OTG)
1283 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1284
1285 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1286
1287 if (padctl->soc->supports_gen2 && port->disable_gen2) {
1288 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1289 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1290 PORTX_SPEED_SUPPORT_SHIFT(index));
1291 value |= (PORT_SPEED_SUPPORT_GEN1 <<
1292 PORTX_SPEED_SUPPORT_SHIFT(index));
1293 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1294 }
1295
1296 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1297 value &= ~SSPX_ELPG_VCORE_DOWN(index);
1298 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1299
1300 usleep_range(min: 100, max: 200);
1301
1302 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1303 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1305
1306 usleep_range(min: 100, max: 200);
1307
1308 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1309 value &= ~SSPX_ELPG_CLAMP_EN(index);
1310 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1311
1312 mutex_unlock(lock: &padctl->lock);
1313
1314 return 0;
1315}
1316
1317static int tegra186_usb3_phy_power_off(struct phy *phy)
1318{
1319 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1320 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1321 struct tegra_xusb_usb3_port *port;
1322 unsigned int index = lane->index;
1323 struct device *dev = padctl->dev;
1324 u32 value;
1325
1326 port = tegra_xusb_find_usb3_port(padctl, index);
1327 if (!port) {
1328 dev_err(dev, "no port found for USB3 lane %u\n", index);
1329 return -ENODEV;
1330 }
1331
1332 mutex_lock(&padctl->lock);
1333
1334 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1335 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1336 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1337
1338 usleep_range(min: 100, max: 200);
1339
1340 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1341 value |= SSPX_ELPG_CLAMP_EN(index);
1342 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1343
1344 usleep_range(min: 250, max: 350);
1345
1346 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1347 value |= SSPX_ELPG_VCORE_DOWN(index);
1348 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1349
1350 mutex_unlock(lock: &padctl->lock);
1351
1352 return 0;
1353}
1354
1355static int tegra186_usb3_phy_init(struct phy *phy)
1356{
1357 return 0;
1358}
1359
1360static int tegra186_usb3_phy_exit(struct phy *phy)
1361{
1362 return 0;
1363}
1364
1365static const struct phy_ops usb3_phy_ops = {
1366 .init = tegra186_usb3_phy_init,
1367 .exit = tegra186_usb3_phy_exit,
1368 .power_on = tegra186_usb3_phy_power_on,
1369 .power_off = tegra186_usb3_phy_power_off,
1370 .owner = THIS_MODULE,
1371};
1372
1373static struct tegra_xusb_pad *
1374tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1375 const struct tegra_xusb_pad_soc *soc,
1376 struct device_node *np)
1377{
1378 struct tegra_xusb_usb3_pad *usb3;
1379 struct tegra_xusb_pad *pad;
1380 int err;
1381
1382 usb3 = kzalloc(size: sizeof(*usb3), GFP_KERNEL);
1383 if (!usb3)
1384 return ERR_PTR(error: -ENOMEM);
1385
1386 pad = &usb3->base;
1387 pad->ops = &tegra186_usb3_lane_ops;
1388 pad->soc = soc;
1389
1390 err = tegra_xusb_pad_init(pad, padctl, np);
1391 if (err < 0) {
1392 kfree(objp: usb3);
1393 goto out;
1394 }
1395
1396 err = tegra_xusb_pad_register(pad, ops: &usb3_phy_ops);
1397 if (err < 0)
1398 goto unregister;
1399
1400 dev_set_drvdata(dev: &pad->dev, data: pad);
1401
1402 return pad;
1403
1404unregister:
1405 device_unregister(dev: &pad->dev);
1406out:
1407 return ERR_PTR(error: err);
1408}
1409
1410static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1411{
1412 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1413
1414 kfree(objp: usb2);
1415}
1416
1417static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1418 .probe = tegra186_usb3_pad_probe,
1419 .remove = tegra186_usb3_pad_remove,
1420};
1421
1422static const char * const tegra186_usb3_functions[] = {
1423 "xusb",
1424};
1425
1426static int
1427tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1428{
1429 struct device *dev = padctl->base.dev;
1430 unsigned int i, count;
1431 u32 value, *level;
1432 int err;
1433
1434 count = padctl->base.soc->ports.usb2.count;
1435
1436 level = devm_kcalloc(dev, n: count, size: sizeof(u32), GFP_KERNEL);
1437 if (!level)
1438 return -ENOMEM;
1439
1440 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, value: &value);
1441 if (err)
1442 return dev_err_probe(dev, err,
1443 fmt: "failed to read calibration fuse\n");
1444
1445 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1446
1447 for (i = 0; i < count; i++)
1448 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1449 HS_CURR_LEVEL_PAD_MASK;
1450
1451 padctl->calib.hs_curr_level = level;
1452
1453 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1454 HS_SQUELCH_MASK;
1455 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1456 HS_TERM_RANGE_ADJ_MASK;
1457
1458 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, value: &value);
1459 if (err) {
1460 dev_err(dev, "failed to read calibration fuse: %d\n", err);
1461 return err;
1462 }
1463
1464 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1465
1466 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1467
1468 return 0;
1469}
1470
1471static struct tegra_xusb_padctl *
1472tegra186_xusb_padctl_probe(struct device *dev,
1473 const struct tegra_xusb_padctl_soc *soc)
1474{
1475 struct platform_device *pdev = to_platform_device(dev);
1476 struct tegra186_xusb_padctl *priv;
1477 struct resource *res;
1478 int err;
1479
1480 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
1481 if (!priv)
1482 return ERR_PTR(error: -ENOMEM);
1483
1484 priv->base.dev = dev;
1485 priv->base.soc = soc;
1486
1487 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1488 priv->ao_regs = devm_ioremap_resource(dev, res);
1489 if (IS_ERR(ptr: priv->ao_regs))
1490 return ERR_CAST(ptr: priv->ao_regs);
1491
1492 err = tegra186_xusb_read_fuse_calibration(padctl: priv);
1493 if (err < 0)
1494 return ERR_PTR(error: err);
1495
1496 return &priv->base;
1497}
1498
1499static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1500{
1501 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1502
1503 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1504 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1505 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1506 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1507}
1508
1509static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1510{
1511 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1512
1513 padctl_writel(padctl, value: priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1514 padctl_writel(padctl, value: priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1515 padctl_writel(padctl, value: priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1516 padctl_writel(padctl, value: priv->context.vbus_id, USB2_VBUS_ID);
1517}
1518
1519static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1520{
1521 tegra186_xusb_padctl_save(padctl);
1522
1523 return 0;
1524}
1525
1526static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1527{
1528 tegra186_xusb_padctl_restore(padctl);
1529
1530 return 0;
1531}
1532
1533static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1534{
1535}
1536
1537static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1538 .probe = tegra186_xusb_padctl_probe,
1539 .remove = tegra186_xusb_padctl_remove,
1540 .suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1541 .resume_noirq = tegra186_xusb_padctl_resume_noirq,
1542 .vbus_override = tegra186_xusb_padctl_vbus_override,
1543 .utmi_pad_power_on = tegra186_utmi_pad_power_on,
1544 .utmi_pad_power_down = tegra186_utmi_pad_power_down,
1545};
1546
1547#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1548static const char * const tegra186_xusb_padctl_supply_names[] = {
1549 "avdd-pll-erefeut",
1550 "avdd-usb",
1551 "vclamp-usb",
1552 "vddio-hsic",
1553};
1554
1555static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1556 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1557 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1558 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1559};
1560
1561static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1562 .name = "usb2",
1563 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1564 .lanes = tegra186_usb2_lanes,
1565 .ops = &tegra186_usb2_pad_ops,
1566};
1567
1568static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1569 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1570 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1571 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1572};
1573
1574static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1575 .name = "usb3",
1576 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1577 .lanes = tegra186_usb3_lanes,
1578 .ops = &tegra186_usb3_pad_ops,
1579};
1580
1581static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1582 &tegra186_usb2_pad,
1583 &tegra186_usb3_pad,
1584#if 0 /* TODO implement */
1585 &tegra186_hsic_pad,
1586#endif
1587};
1588
1589const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1590 .num_pads = ARRAY_SIZE(tegra186_pads),
1591 .pads = tegra186_pads,
1592 .ports = {
1593 .usb2 = {
1594 .ops = &tegra186_usb2_port_ops,
1595 .count = 3,
1596 },
1597#if 0 /* TODO implement */
1598 .hsic = {
1599 .ops = &tegra186_hsic_port_ops,
1600 .count = 1,
1601 },
1602#endif
1603 .usb3 = {
1604 .ops = &tegra186_usb3_port_ops,
1605 .count = 3,
1606 },
1607 },
1608 .ops = &tegra186_xusb_padctl_ops,
1609 .supply_names = tegra186_xusb_padctl_supply_names,
1610 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1611};
1612EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1613#endif
1614
1615#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
1616 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
1617static const char * const tegra194_xusb_padctl_supply_names[] = {
1618 "avdd-usb",
1619 "vclamp-usb",
1620};
1621
1622static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1623 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1624 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1625 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1626 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1627};
1628
1629static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1630 .name = "usb2",
1631 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1632 .lanes = tegra194_usb2_lanes,
1633 .ops = &tegra186_usb2_pad_ops,
1634};
1635
1636static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1637 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1638 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1639 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1640 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1641};
1642
1643static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1644 .name = "usb3",
1645 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1646 .lanes = tegra194_usb3_lanes,
1647 .ops = &tegra186_usb3_pad_ops,
1648};
1649
1650static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1651 &tegra194_usb2_pad,
1652 &tegra194_usb3_pad,
1653};
1654
1655const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1656 .num_pads = ARRAY_SIZE(tegra194_pads),
1657 .pads = tegra194_pads,
1658 .ports = {
1659 .usb2 = {
1660 .ops = &tegra186_usb2_port_ops,
1661 .count = 4,
1662 },
1663 .usb3 = {
1664 .ops = &tegra186_usb3_port_ops,
1665 .count = 4,
1666 },
1667 },
1668 .ops = &tegra186_xusb_padctl_ops,
1669 .supply_names = tegra194_xusb_padctl_supply_names,
1670 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1671 .supports_gen2 = true,
1672 .poll_trk_completed = true,
1673};
1674EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1675
1676const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
1677 .num_pads = ARRAY_SIZE(tegra194_pads),
1678 .pads = tegra194_pads,
1679 .ports = {
1680 .usb2 = {
1681 .ops = &tegra186_usb2_port_ops,
1682 .count = 4,
1683 },
1684 .usb3 = {
1685 .ops = &tegra186_usb3_port_ops,
1686 .count = 4,
1687 },
1688 },
1689 .ops = &tegra186_xusb_padctl_ops,
1690 .supply_names = tegra194_xusb_padctl_supply_names,
1691 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1692 .supports_gen2 = true,
1693 .poll_trk_completed = true,
1694 .trk_hw_mode = true,
1695 .supports_lp_cfg_en = true,
1696};
1697EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
1698#endif
1699
1700MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1701MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1702MODULE_LICENSE("GPL v2");
1703

source code of linux/drivers/phy/tegra/xusb-tegra186.c