1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2019 MediaTek Inc. |
4 | * Author: Min.Guo <min.guo@mediatek.com> |
5 | */ |
6 | |
7 | #include <dt-bindings/pinctrl/mt65xx.h> |
8 | #include <linux/of.h> |
9 | #include <linux/module.h> |
10 | #include <linux/pinctrl/pinctrl.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/regmap.h> |
13 | |
14 | #include "pinctrl-mtk-common.h" |
15 | #include "pinctrl-mtk-mt8516.h" |
16 | |
17 | static const struct mtk_drv_group_desc mt8516_drv_grp[] = { |
18 | /* 0E4E8SR 4/8/12/16 */ |
19 | MTK_DRV_GRP(4, 16, 1, 2, 4), |
20 | /* 0E2E4SR 2/4/6/8 */ |
21 | MTK_DRV_GRP(2, 8, 1, 2, 2), |
22 | /* E8E4E2 2/4/6/8/10/12/14/16 */ |
23 | MTK_DRV_GRP(2, 16, 0, 2, 2) |
24 | }; |
25 | |
26 | static const struct mtk_pin_drv_grp mt8516_pin_drv[] = { |
27 | MTK_PIN_DRV_GRP(0, 0xd00, 0, 0), |
28 | MTK_PIN_DRV_GRP(1, 0xd00, 0, 0), |
29 | MTK_PIN_DRV_GRP(2, 0xd00, 0, 0), |
30 | MTK_PIN_DRV_GRP(3, 0xd00, 0, 0), |
31 | MTK_PIN_DRV_GRP(4, 0xd00, 0, 0), |
32 | |
33 | MTK_PIN_DRV_GRP(5, 0xd00, 4, 0), |
34 | MTK_PIN_DRV_GRP(6, 0xd00, 4, 0), |
35 | MTK_PIN_DRV_GRP(7, 0xd00, 4, 0), |
36 | MTK_PIN_DRV_GRP(8, 0xd00, 4, 0), |
37 | MTK_PIN_DRV_GRP(9, 0xd00, 4, 0), |
38 | MTK_PIN_DRV_GRP(10, 0xd00, 4, 0), |
39 | |
40 | MTK_PIN_DRV_GRP(11, 0xd00, 8, 0), |
41 | MTK_PIN_DRV_GRP(12, 0xd00, 8, 0), |
42 | MTK_PIN_DRV_GRP(13, 0xd00, 8, 0), |
43 | |
44 | MTK_PIN_DRV_GRP(14, 0xd00, 12, 2), |
45 | MTK_PIN_DRV_GRP(15, 0xd00, 12, 2), |
46 | MTK_PIN_DRV_GRP(16, 0xd00, 12, 2), |
47 | MTK_PIN_DRV_GRP(17, 0xd00, 12, 2), |
48 | |
49 | MTK_PIN_DRV_GRP(18, 0xd10, 0, 0), |
50 | MTK_PIN_DRV_GRP(19, 0xd10, 0, 0), |
51 | MTK_PIN_DRV_GRP(20, 0xd10, 0, 0), |
52 | |
53 | MTK_PIN_DRV_GRP(21, 0xd00, 12, 2), |
54 | MTK_PIN_DRV_GRP(22, 0xd00, 12, 2), |
55 | MTK_PIN_DRV_GRP(23, 0xd00, 12, 2), |
56 | |
57 | MTK_PIN_DRV_GRP(24, 0xd00, 8, 0), |
58 | MTK_PIN_DRV_GRP(25, 0xd00, 8, 0), |
59 | |
60 | MTK_PIN_DRV_GRP(26, 0xd10, 4, 1), |
61 | MTK_PIN_DRV_GRP(27, 0xd10, 4, 1), |
62 | MTK_PIN_DRV_GRP(28, 0xd10, 4, 1), |
63 | MTK_PIN_DRV_GRP(29, 0xd10, 4, 1), |
64 | MTK_PIN_DRV_GRP(30, 0xd10, 4, 1), |
65 | |
66 | MTK_PIN_DRV_GRP(31, 0xd10, 8, 1), |
67 | MTK_PIN_DRV_GRP(32, 0xd10, 8, 1), |
68 | MTK_PIN_DRV_GRP(33, 0xd10, 8, 1), |
69 | |
70 | MTK_PIN_DRV_GRP(34, 0xd10, 12, 0), |
71 | MTK_PIN_DRV_GRP(35, 0xd10, 12, 0), |
72 | |
73 | MTK_PIN_DRV_GRP(36, 0xd20, 0, 0), |
74 | MTK_PIN_DRV_GRP(37, 0xd20, 0, 0), |
75 | MTK_PIN_DRV_GRP(38, 0xd20, 0, 0), |
76 | MTK_PIN_DRV_GRP(39, 0xd20, 0, 0), |
77 | |
78 | MTK_PIN_DRV_GRP(40, 0xd20, 4, 1), |
79 | |
80 | MTK_PIN_DRV_GRP(41, 0xd20, 8, 1), |
81 | MTK_PIN_DRV_GRP(42, 0xd20, 8, 1), |
82 | MTK_PIN_DRV_GRP(43, 0xd20, 8, 1), |
83 | |
84 | MTK_PIN_DRV_GRP(44, 0xd20, 12, 1), |
85 | MTK_PIN_DRV_GRP(45, 0xd20, 12, 1), |
86 | MTK_PIN_DRV_GRP(46, 0xd20, 12, 1), |
87 | MTK_PIN_DRV_GRP(47, 0xd20, 12, 1), |
88 | |
89 | MTK_PIN_DRV_GRP(48, 0xd30, 0, 1), |
90 | MTK_PIN_DRV_GRP(49, 0xd30, 0, 1), |
91 | MTK_PIN_DRV_GRP(50, 0xd30, 0, 1), |
92 | MTK_PIN_DRV_GRP(51, 0xd30, 0, 1), |
93 | |
94 | MTK_PIN_DRV_GRP(54, 0xd30, 8, 1), |
95 | |
96 | MTK_PIN_DRV_GRP(55, 0xd30, 12, 1), |
97 | MTK_PIN_DRV_GRP(56, 0xd30, 12, 1), |
98 | MTK_PIN_DRV_GRP(57, 0xd30, 12, 1), |
99 | |
100 | MTK_PIN_DRV_GRP(62, 0xd40, 8, 1), |
101 | MTK_PIN_DRV_GRP(63, 0xd40, 8, 1), |
102 | MTK_PIN_DRV_GRP(64, 0xd40, 8, 1), |
103 | MTK_PIN_DRV_GRP(65, 0xd40, 8, 1), |
104 | MTK_PIN_DRV_GRP(66, 0xd40, 8, 1), |
105 | MTK_PIN_DRV_GRP(67, 0xd40, 8, 1), |
106 | |
107 | MTK_PIN_DRV_GRP(68, 0xd40, 12, 2), |
108 | |
109 | MTK_PIN_DRV_GRP(69, 0xd50, 0, 2), |
110 | |
111 | MTK_PIN_DRV_GRP(70, 0xd50, 4, 2), |
112 | MTK_PIN_DRV_GRP(71, 0xd50, 4, 2), |
113 | MTK_PIN_DRV_GRP(72, 0xd50, 4, 2), |
114 | MTK_PIN_DRV_GRP(73, 0xd50, 4, 2), |
115 | |
116 | MTK_PIN_DRV_GRP(100, 0xd50, 8, 1), |
117 | MTK_PIN_DRV_GRP(101, 0xd50, 8, 1), |
118 | MTK_PIN_DRV_GRP(102, 0xd50, 8, 1), |
119 | MTK_PIN_DRV_GRP(103, 0xd50, 8, 1), |
120 | |
121 | MTK_PIN_DRV_GRP(104, 0xd50, 12, 2), |
122 | |
123 | MTK_PIN_DRV_GRP(105, 0xd60, 0, 2), |
124 | |
125 | MTK_PIN_DRV_GRP(106, 0xd60, 4, 2), |
126 | MTK_PIN_DRV_GRP(107, 0xd60, 4, 2), |
127 | MTK_PIN_DRV_GRP(108, 0xd60, 4, 2), |
128 | MTK_PIN_DRV_GRP(109, 0xd60, 4, 2), |
129 | |
130 | MTK_PIN_DRV_GRP(110, 0xd70, 0, 2), |
131 | MTK_PIN_DRV_GRP(111, 0xd70, 0, 2), |
132 | MTK_PIN_DRV_GRP(112, 0xd70, 0, 2), |
133 | MTK_PIN_DRV_GRP(113, 0xd70, 0, 2), |
134 | |
135 | MTK_PIN_DRV_GRP(114, 0xd70, 4, 2), |
136 | |
137 | MTK_PIN_DRV_GRP(115, 0xd60, 12, 2), |
138 | |
139 | MTK_PIN_DRV_GRP(116, 0xd60, 8, 2), |
140 | |
141 | MTK_PIN_DRV_GRP(117, 0xd70, 0, 2), |
142 | MTK_PIN_DRV_GRP(118, 0xd70, 0, 2), |
143 | MTK_PIN_DRV_GRP(119, 0xd70, 0, 2), |
144 | MTK_PIN_DRV_GRP(120, 0xd70, 0, 2), |
145 | }; |
146 | |
147 | static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = { |
148 | MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12), |
149 | MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0), |
150 | MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4), |
151 | MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8), |
152 | |
153 | MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12), |
154 | MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0), |
155 | MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4), |
156 | |
157 | MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0), |
158 | MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4), |
159 | MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0), |
160 | MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4), |
161 | |
162 | MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8), |
163 | MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4), |
164 | MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4), |
165 | MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8), |
166 | MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12), |
167 | MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0), |
168 | |
169 | MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0), |
170 | MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12), |
171 | MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12), |
172 | MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0), |
173 | MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4), |
174 | MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8), |
175 | MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12), |
176 | MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8), |
177 | MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4), |
178 | MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0), |
179 | MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8), |
180 | MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0), |
181 | MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4), |
182 | MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12), |
183 | MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8), |
184 | MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4), |
185 | MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), |
186 | }; |
187 | |
188 | static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = { |
189 | MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), |
190 | MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), |
191 | MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12), |
192 | MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13), |
193 | MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10), |
194 | MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13), |
195 | MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12), |
196 | MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0), |
197 | MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1), |
198 | MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2), |
199 | MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11), |
200 | MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10), |
201 | MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11), |
202 | MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14), |
203 | MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0), |
204 | MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2), |
205 | MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4), |
206 | MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15), |
207 | MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1), |
208 | MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5), |
209 | MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6), |
210 | MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2), |
211 | MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1), |
212 | MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6), |
213 | MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5), |
214 | MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4), |
215 | MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3), |
216 | MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7), |
217 | MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12), |
218 | MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11), |
219 | MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0), |
220 | MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15), |
221 | MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14), |
222 | MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13), |
223 | MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9), |
224 | MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8), |
225 | MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7), |
226 | MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6), |
227 | MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10), |
228 | MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1), |
229 | MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0), |
230 | MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5), |
231 | MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4), |
232 | MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3), |
233 | MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2), |
234 | MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9), |
235 | }; |
236 | |
237 | static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { |
238 | MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2), |
239 | MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3), |
240 | MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12), |
241 | MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13), |
242 | MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10), |
243 | MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13), |
244 | MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12), |
245 | MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0), |
246 | MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1), |
247 | MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2), |
248 | MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11), |
249 | MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10), |
250 | MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11), |
251 | MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14), |
252 | MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0), |
253 | MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2), |
254 | MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4), |
255 | MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15), |
256 | MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1), |
257 | MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5), |
258 | MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6), |
259 | MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2), |
260 | MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1), |
261 | MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3), |
262 | MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4), |
263 | MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5), |
264 | MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6), |
265 | |
266 | MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7), |
267 | MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12), |
268 | MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11), |
269 | MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13), |
270 | MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14), |
271 | MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15), |
272 | MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0), |
273 | MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9), |
274 | MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8), |
275 | MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7), |
276 | MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6), |
277 | MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10), |
278 | MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1), |
279 | MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0), |
280 | MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5), |
281 | MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4), |
282 | MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3), |
283 | MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2), |
284 | MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), |
285 | }; |
286 | |
287 | static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { |
288 | .pins = mtk_pins_mt8516, |
289 | .npins = ARRAY_SIZE(mtk_pins_mt8516), |
290 | .grp_desc = mt8516_drv_grp, |
291 | .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp), |
292 | .pin_drv_grp = mt8516_pin_drv, |
293 | .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv), |
294 | .spec_ies = mt8516_ies_set, |
295 | .n_spec_ies = ARRAY_SIZE(mt8516_ies_set), |
296 | .spec_pupd = mt8516_spec_pupd, |
297 | .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd), |
298 | .spec_smt = mt8516_smt_set, |
299 | .n_spec_smt = ARRAY_SIZE(mt8516_smt_set), |
300 | .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, |
301 | .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, |
302 | .dir_offset = 0x0000, |
303 | .pullen_offset = 0x0500, |
304 | .pullsel_offset = 0x0600, |
305 | .dout_offset = 0x0100, |
306 | .din_offset = 0x0200, |
307 | .pinmux_offset = 0x0300, |
308 | .type1_start = 125, |
309 | .type1_end = 125, |
310 | .port_shf = 4, |
311 | .port_mask = 0xf, |
312 | .port_align = 4, |
313 | .mode_mask = 0xf, |
314 | .mode_per_reg = 5, |
315 | .mode_shf = 4, |
316 | .eint_hw = { |
317 | .port_mask = 7, |
318 | .ports = 6, |
319 | .ap_num = 169, |
320 | .db_cnt = 64, |
321 | .db_time = debounce_time_mt6795, |
322 | }, |
323 | }; |
324 | |
325 | static const struct of_device_id mt8516_pctrl_match[] = { |
326 | { .compatible = "mediatek,mt8516-pinctrl" , .data = &mt8516_pinctrl_data }, |
327 | {} |
328 | }; |
329 | |
330 | MODULE_DEVICE_TABLE(of, mt8516_pctrl_match); |
331 | |
332 | static struct platform_driver mtk_pinctrl_driver = { |
333 | .probe = mtk_pctrl_common_probe, |
334 | .driver = { |
335 | .name = "mediatek-mt8516-pinctrl" , |
336 | .of_match_table = mt8516_pctrl_match, |
337 | .pm = pm_sleep_ptr(&mtk_eint_pm_ops), |
338 | }, |
339 | }; |
340 | |
341 | static int __init mtk_pinctrl_init(void) |
342 | { |
343 | return platform_driver_register(&mtk_pinctrl_driver); |
344 | } |
345 | arch_initcall(mtk_pinctrl_init); |
346 | |