1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin |
4 | * bindings for MediaTek SoC. |
5 | * |
6 | * Copyright (C) 2018 MediaTek Inc. |
7 | * Author: Sean Wang <sean.wang@mediatek.com> |
8 | * Zhiyong Tao <zhiyong.tao@mediatek.com> |
9 | * Hongzhou.Yang <hongzhou.yang@mediatek.com> |
10 | */ |
11 | |
12 | #include <linux/gpio/driver.h> |
13 | #include <linux/module.h> |
14 | #include <linux/seq_file.h> |
15 | |
16 | #include <linux/pinctrl/consumer.h> |
17 | |
18 | #include <dt-bindings/pinctrl/mt65xx.h> |
19 | |
20 | #include "pinctrl-paris.h" |
21 | |
22 | #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME |
23 | |
24 | /* Custom pinconf parameters */ |
25 | #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) |
26 | #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) |
27 | #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) |
28 | #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) |
29 | #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5) |
30 | |
31 | static const struct pinconf_generic_params mtk_custom_bindings[] = { |
32 | {"mediatek,tdsel" , MTK_PIN_CONFIG_TDSEL, 0}, |
33 | {"mediatek,rdsel" , MTK_PIN_CONFIG_RDSEL, 0}, |
34 | {"mediatek,pull-up-adv" , MTK_PIN_CONFIG_PU_ADV, 1}, |
35 | {"mediatek,pull-down-adv" , MTK_PIN_CONFIG_PD_ADV, 1}, |
36 | {"mediatek,drive-strength-adv" , MTK_PIN_CONFIG_DRV_ADV, 2}, |
37 | }; |
38 | |
39 | #ifdef CONFIG_DEBUG_FS |
40 | static const struct pin_config_item mtk_conf_items[] = { |
41 | PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel" , NULL, true), |
42 | PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel" , NULL, true), |
43 | PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv" , NULL, true), |
44 | PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv" , NULL, true), |
45 | PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv" , NULL, true), |
46 | }; |
47 | #endif |
48 | |
49 | static const char * const mtk_gpio_functions[] = { |
50 | "func0" , "func1" , "func2" , "func3" , |
51 | "func4" , "func5" , "func6" , "func7" , |
52 | "func8" , "func9" , "func10" , "func11" , |
53 | "func12" , "func13" , "func14" , "func15" , |
54 | }; |
55 | |
56 | /* |
57 | * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV |
58 | * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs. |
59 | * |
60 | * The custom value encodes three hardware bits as follows: |
61 | * |
62 | * | Bits | |
63 | * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA) |
64 | * ------------------------------------------------ |
65 | * | x | x | 0 | disabled, use standard drive strength |
66 | * ------------------------------------- |
67 | * | 0 | 0 | 1 | 125 uA |
68 | * | 0 | 1 | 1 | 250 uA |
69 | * | 1 | 0 | 1 | 500 uA |
70 | * | 1 | 1 | 1 | 1000 uA |
71 | */ |
72 | static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 }; |
73 | |
74 | static int mtk_drv_adv_to_uA(int val) |
75 | { |
76 | /* This should never happen. */ |
77 | if (WARN_ON_ONCE(val < 0 || val > 7)) |
78 | return -EINVAL; |
79 | |
80 | /* Bit 0 simply enables this hardware part */ |
81 | if (!(val & BIT(0))) |
82 | return -EINVAL; |
83 | |
84 | return mtk_drv_adv_uA[(val >> 1)]; |
85 | } |
86 | |
87 | static int mtk_drv_uA_to_adv(int val) |
88 | { |
89 | switch (val) { |
90 | case 125: |
91 | return 0x1; |
92 | case 250: |
93 | return 0x3; |
94 | case 500: |
95 | return 0x5; |
96 | case 1000: |
97 | return 0x7; |
98 | } |
99 | |
100 | return -EINVAL; |
101 | } |
102 | |
103 | static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, |
104 | struct pinctrl_gpio_range *range, |
105 | unsigned int pin) |
106 | { |
107 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
108 | const struct mtk_pin_desc *desc; |
109 | |
110 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; |
111 | |
112 | return mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_MODE, |
113 | value: hw->soc->gpio_m); |
114 | } |
115 | |
116 | static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, |
117 | struct pinctrl_gpio_range *range, |
118 | unsigned int pin, bool input) |
119 | { |
120 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
121 | const struct mtk_pin_desc *desc; |
122 | |
123 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; |
124 | |
125 | /* hardware would take 0 as input direction */ |
126 | return mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DIR, value: !input); |
127 | } |
128 | |
129 | static int mtk_pinconf_get(struct pinctrl_dev *pctldev, |
130 | unsigned int pin, unsigned long *config) |
131 | { |
132 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
133 | u32 param = pinconf_to_config_param(config: *config); |
134 | int pullup, reg, err = -ENOTSUPP, ret = 1; |
135 | const struct mtk_pin_desc *desc; |
136 | |
137 | if (pin >= hw->soc->npins) |
138 | return -EINVAL; |
139 | |
140 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; |
141 | |
142 | switch (param) { |
143 | case PIN_CONFIG_BIAS_DISABLE: |
144 | case PIN_CONFIG_BIAS_PULL_UP: |
145 | case PIN_CONFIG_BIAS_PULL_DOWN: |
146 | if (!hw->soc->bias_get_combo) |
147 | break; |
148 | err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); |
149 | if (err) |
150 | break; |
151 | if (ret == MTK_PUPD_SET_R1R0_00) |
152 | ret = MTK_DISABLE; |
153 | if (param == PIN_CONFIG_BIAS_DISABLE) { |
154 | if (ret != MTK_DISABLE) |
155 | err = -EINVAL; |
156 | } else if (param == PIN_CONFIG_BIAS_PULL_UP) { |
157 | if (!pullup || ret == MTK_DISABLE) |
158 | err = -EINVAL; |
159 | } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { |
160 | if (pullup || ret == MTK_DISABLE) |
161 | err = -EINVAL; |
162 | } |
163 | break; |
164 | case PIN_CONFIG_SLEW_RATE: |
165 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_SR, value: &ret); |
166 | break; |
167 | case PIN_CONFIG_INPUT_ENABLE: |
168 | case PIN_CONFIG_OUTPUT_ENABLE: |
169 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_DIR, value: &ret); |
170 | if (err) |
171 | break; |
172 | /* CONFIG Current direction return value |
173 | * ------------- ----------------- ---------------------- |
174 | * OUTPUT_ENABLE output 1 (= HW value) |
175 | * input 0 (= HW value) |
176 | * INPUT_ENABLE output 0 (= reverse HW value) |
177 | * input 1 (= reverse HW value) |
178 | */ |
179 | if (param == PIN_CONFIG_INPUT_ENABLE) |
180 | ret = !ret; |
181 | |
182 | break; |
183 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
184 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_DIR, value: &ret); |
185 | if (err) |
186 | break; |
187 | /* return error when in output mode |
188 | * because schmitt trigger only work in input mode |
189 | */ |
190 | if (ret) { |
191 | err = -EINVAL; |
192 | break; |
193 | } |
194 | |
195 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_SMT, value: &ret); |
196 | break; |
197 | case PIN_CONFIG_DRIVE_STRENGTH: |
198 | if (!hw->soc->drive_get) |
199 | break; |
200 | |
201 | if (hw->soc->adv_drive_get) { |
202 | err = hw->soc->adv_drive_get(hw, desc, &ret); |
203 | if (!err) { |
204 | err = mtk_drv_adv_to_uA(val: ret); |
205 | if (err > 0) { |
206 | /* PIN_CONFIG_DRIVE_STRENGTH_UA used */ |
207 | err = -EINVAL; |
208 | break; |
209 | } |
210 | } |
211 | } |
212 | |
213 | err = hw->soc->drive_get(hw, desc, &ret); |
214 | break; |
215 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
216 | if (!hw->soc->adv_drive_get) |
217 | break; |
218 | |
219 | err = hw->soc->adv_drive_get(hw, desc, &ret); |
220 | if (err) |
221 | break; |
222 | err = mtk_drv_adv_to_uA(val: ret); |
223 | if (err < 0) |
224 | break; |
225 | |
226 | ret = err; |
227 | err = 0; |
228 | break; |
229 | case MTK_PIN_CONFIG_TDSEL: |
230 | case MTK_PIN_CONFIG_RDSEL: |
231 | reg = (param == MTK_PIN_CONFIG_TDSEL) ? |
232 | PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; |
233 | err = mtk_hw_get_value(hw, desc, field: reg, value: &ret); |
234 | break; |
235 | case MTK_PIN_CONFIG_PU_ADV: |
236 | case MTK_PIN_CONFIG_PD_ADV: |
237 | if (!hw->soc->adv_pull_get) |
238 | break; |
239 | pullup = param == MTK_PIN_CONFIG_PU_ADV; |
240 | err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); |
241 | break; |
242 | case MTK_PIN_CONFIG_DRV_ADV: |
243 | if (!hw->soc->adv_drive_get) |
244 | break; |
245 | err = hw->soc->adv_drive_get(hw, desc, &ret); |
246 | break; |
247 | } |
248 | |
249 | if (!err) |
250 | *config = pinconf_to_config_packed(param, argument: ret); |
251 | |
252 | return err; |
253 | } |
254 | |
255 | static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, |
256 | enum pin_config_param param, u32 arg) |
257 | { |
258 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
259 | const struct mtk_pin_desc *desc; |
260 | int err = -ENOTSUPP; |
261 | u32 reg; |
262 | |
263 | if (pin >= hw->soc->npins) |
264 | return -EINVAL; |
265 | |
266 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; |
267 | |
268 | switch ((u32)param) { |
269 | case PIN_CONFIG_BIAS_DISABLE: |
270 | if (!hw->soc->bias_set_combo) |
271 | break; |
272 | err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); |
273 | break; |
274 | case PIN_CONFIG_BIAS_PULL_UP: |
275 | if (!hw->soc->bias_set_combo) |
276 | break; |
277 | err = hw->soc->bias_set_combo(hw, desc, 1, arg); |
278 | break; |
279 | case PIN_CONFIG_BIAS_PULL_DOWN: |
280 | if (!hw->soc->bias_set_combo) |
281 | break; |
282 | err = hw->soc->bias_set_combo(hw, desc, 0, arg); |
283 | break; |
284 | case PIN_CONFIG_OUTPUT_ENABLE: |
285 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_SMT, |
286 | MTK_DISABLE); |
287 | /* Keep set direction to consider the case that a GPIO pin |
288 | * does not have SMT control |
289 | */ |
290 | if (err != -ENOTSUPP) |
291 | break; |
292 | |
293 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DIR, |
294 | MTK_OUTPUT); |
295 | break; |
296 | case PIN_CONFIG_INPUT_ENABLE: |
297 | /* regard all non-zero value as enable */ |
298 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_IES, value: !!arg); |
299 | if (err) |
300 | break; |
301 | |
302 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DIR, |
303 | MTK_INPUT); |
304 | break; |
305 | case PIN_CONFIG_SLEW_RATE: |
306 | /* regard all non-zero value as enable */ |
307 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_SR, value: !!arg); |
308 | break; |
309 | case PIN_CONFIG_OUTPUT: |
310 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DO, |
311 | value: arg); |
312 | if (err) |
313 | break; |
314 | |
315 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DIR, |
316 | MTK_OUTPUT); |
317 | break; |
318 | case PIN_CONFIG_INPUT_SCHMITT: |
319 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
320 | /* arg = 1: Input mode & SMT enable ; |
321 | * arg = 0: Output mode & SMT disable |
322 | */ |
323 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DIR, value: !arg); |
324 | if (err) |
325 | break; |
326 | |
327 | err = mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_SMT, value: !!arg); |
328 | break; |
329 | case PIN_CONFIG_DRIVE_STRENGTH: |
330 | if (!hw->soc->drive_set) |
331 | break; |
332 | err = hw->soc->drive_set(hw, desc, arg); |
333 | break; |
334 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
335 | if (!hw->soc->adv_drive_set) |
336 | break; |
337 | |
338 | err = mtk_drv_uA_to_adv(val: arg); |
339 | if (err < 0) |
340 | break; |
341 | err = hw->soc->adv_drive_set(hw, desc, err); |
342 | break; |
343 | case MTK_PIN_CONFIG_TDSEL: |
344 | case MTK_PIN_CONFIG_RDSEL: |
345 | reg = (param == MTK_PIN_CONFIG_TDSEL) ? |
346 | PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; |
347 | err = mtk_hw_set_value(hw, desc, field: reg, value: arg); |
348 | break; |
349 | case MTK_PIN_CONFIG_PU_ADV: |
350 | case MTK_PIN_CONFIG_PD_ADV: |
351 | if (!hw->soc->adv_pull_set) |
352 | break; |
353 | err = hw->soc->adv_pull_set(hw, desc, |
354 | (param == MTK_PIN_CONFIG_PU_ADV), |
355 | arg); |
356 | break; |
357 | case MTK_PIN_CONFIG_DRV_ADV: |
358 | if (!hw->soc->adv_drive_set) |
359 | break; |
360 | err = hw->soc->adv_drive_set(hw, desc, arg); |
361 | break; |
362 | } |
363 | |
364 | return err; |
365 | } |
366 | |
367 | static struct mtk_pinctrl_group * |
368 | mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin) |
369 | { |
370 | int i; |
371 | |
372 | for (i = 0; i < hw->soc->ngrps; i++) { |
373 | struct mtk_pinctrl_group *grp = hw->groups + i; |
374 | |
375 | if (grp->pin == pin) |
376 | return grp; |
377 | } |
378 | |
379 | return NULL; |
380 | } |
381 | |
382 | static const struct mtk_func_desc * |
383 | mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum) |
384 | { |
385 | const struct mtk_pin_desc *pin = hw->soc->pins + pin_num; |
386 | const struct mtk_func_desc *func = pin->funcs; |
387 | |
388 | while (func && func->name) { |
389 | if (func->muxval == fnum) |
390 | return func; |
391 | func++; |
392 | } |
393 | |
394 | return NULL; |
395 | } |
396 | |
397 | static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num, |
398 | u32 fnum) |
399 | { |
400 | int i; |
401 | |
402 | for (i = 0; i < hw->soc->npins; i++) { |
403 | const struct mtk_pin_desc *pin = hw->soc->pins + i; |
404 | |
405 | if (pin->number == pin_num) { |
406 | const struct mtk_func_desc *func = pin->funcs; |
407 | |
408 | while (func && func->name) { |
409 | if (func->muxval == fnum) |
410 | return true; |
411 | func++; |
412 | } |
413 | |
414 | break; |
415 | } |
416 | } |
417 | |
418 | return false; |
419 | } |
420 | |
421 | static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, |
422 | u32 pin, u32 fnum, |
423 | struct mtk_pinctrl_group *grp, |
424 | struct pinctrl_map **map, |
425 | unsigned *reserved_maps, |
426 | unsigned *num_maps) |
427 | { |
428 | bool ret; |
429 | |
430 | if (*num_maps == *reserved_maps) |
431 | return -ENOSPC; |
432 | |
433 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; |
434 | (*map)[*num_maps].data.mux.group = grp->name; |
435 | |
436 | ret = mtk_pctrl_is_function_valid(hw: pctl, pin_num: pin, fnum); |
437 | if (!ret) { |
438 | dev_err(pctl->dev, "invalid function %d on pin %d .\n" , |
439 | fnum, pin); |
440 | return -EINVAL; |
441 | } |
442 | |
443 | (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; |
444 | (*num_maps)++; |
445 | |
446 | return 0; |
447 | } |
448 | |
449 | static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
450 | struct device_node *node, |
451 | struct pinctrl_map **map, |
452 | unsigned *reserved_maps, |
453 | unsigned *num_maps) |
454 | { |
455 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
456 | int num_pins, num_funcs, maps_per_pin, i, err; |
457 | struct mtk_pinctrl_group *grp; |
458 | unsigned int num_configs; |
459 | bool has_config = false; |
460 | unsigned long *configs; |
461 | u32 pinfunc, pin, func; |
462 | struct property *pins; |
463 | unsigned reserve = 0; |
464 | |
465 | pins = of_find_property(np: node, name: "pinmux" , NULL); |
466 | if (!pins) { |
467 | dev_err(hw->dev, "missing pins property in node %pOFn .\n" , |
468 | node); |
469 | return -EINVAL; |
470 | } |
471 | |
472 | err = pinconf_generic_parse_dt_config(np: node, pctldev, configs: &configs, |
473 | nconfigs: &num_configs); |
474 | if (err) |
475 | return err; |
476 | |
477 | if (num_configs) |
478 | has_config = true; |
479 | |
480 | num_pins = pins->length / sizeof(u32); |
481 | num_funcs = num_pins; |
482 | maps_per_pin = 0; |
483 | if (num_funcs) |
484 | maps_per_pin++; |
485 | if (has_config && num_pins >= 1) |
486 | maps_per_pin++; |
487 | |
488 | if (!num_pins || !maps_per_pin) { |
489 | err = -EINVAL; |
490 | goto exit; |
491 | } |
492 | |
493 | reserve = num_pins * maps_per_pin; |
494 | |
495 | err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, |
496 | reserve); |
497 | if (err < 0) |
498 | goto exit; |
499 | |
500 | for (i = 0; i < num_pins; i++) { |
501 | err = of_property_read_u32_index(np: node, propname: "pinmux" , index: i, out_value: &pinfunc); |
502 | if (err) |
503 | goto exit; |
504 | |
505 | pin = MTK_GET_PIN_NO(pinfunc); |
506 | func = MTK_GET_PIN_FUNC(pinfunc); |
507 | |
508 | if (pin >= hw->soc->npins || |
509 | func >= ARRAY_SIZE(mtk_gpio_functions)) { |
510 | dev_err(hw->dev, "invalid pins value.\n" ); |
511 | err = -EINVAL; |
512 | goto exit; |
513 | } |
514 | |
515 | grp = mtk_pctrl_find_group_by_pin(hw, pin); |
516 | if (!grp) { |
517 | dev_err(hw->dev, "unable to match pin %d to group\n" , |
518 | pin); |
519 | err = -EINVAL; |
520 | goto exit; |
521 | } |
522 | |
523 | err = mtk_pctrl_dt_node_to_map_func(pctl: hw, pin, fnum: func, grp, map, |
524 | reserved_maps, num_maps); |
525 | if (err < 0) |
526 | goto exit; |
527 | |
528 | if (has_config) { |
529 | err = pinctrl_utils_add_map_configs(pctldev, map, |
530 | reserved_maps, |
531 | num_maps, |
532 | group: grp->name, |
533 | configs, |
534 | num_configs, |
535 | type: PIN_MAP_TYPE_CONFIGS_GROUP); |
536 | if (err < 0) |
537 | goto exit; |
538 | } |
539 | } |
540 | |
541 | err = 0; |
542 | |
543 | exit: |
544 | kfree(objp: configs); |
545 | return err; |
546 | } |
547 | |
548 | static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
549 | struct device_node *np_config, |
550 | struct pinctrl_map **map, |
551 | unsigned *num_maps) |
552 | { |
553 | struct device_node *np; |
554 | unsigned reserved_maps; |
555 | int ret; |
556 | |
557 | *map = NULL; |
558 | *num_maps = 0; |
559 | reserved_maps = 0; |
560 | |
561 | for_each_child_of_node(np_config, np) { |
562 | ret = mtk_pctrl_dt_subnode_to_map(pctldev, node: np, map, |
563 | reserved_maps: &reserved_maps, |
564 | num_maps); |
565 | if (ret < 0) { |
566 | pinctrl_utils_free_map(pctldev, map: *map, num_maps: *num_maps); |
567 | of_node_put(node: np); |
568 | return ret; |
569 | } |
570 | } |
571 | |
572 | return 0; |
573 | } |
574 | |
575 | static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
576 | { |
577 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
578 | |
579 | return hw->soc->ngrps; |
580 | } |
581 | |
582 | static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, |
583 | unsigned group) |
584 | { |
585 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
586 | |
587 | return hw->groups[group].name; |
588 | } |
589 | |
590 | static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, |
591 | unsigned group, const unsigned **pins, |
592 | unsigned *num_pins) |
593 | { |
594 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
595 | |
596 | *pins = (unsigned *)&hw->groups[group].pin; |
597 | *num_pins = 1; |
598 | |
599 | return 0; |
600 | } |
601 | |
602 | static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field) |
603 | { |
604 | const struct mtk_pin_desc *desc; |
605 | int value, err; |
606 | |
607 | if (gpio >= hw->soc->npins) |
608 | return -EINVAL; |
609 | |
610 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
611 | |
612 | err = mtk_hw_get_value(hw, desc, field, value: &value); |
613 | if (err) |
614 | return err; |
615 | |
616 | return value; |
617 | } |
618 | |
619 | #define mtk_pctrl_get_pinmux(hw, gpio) \ |
620 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE) |
621 | |
622 | #define mtk_pctrl_get_direction(hw, gpio) \ |
623 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR) |
624 | |
625 | #define mtk_pctrl_get_out(hw, gpio) \ |
626 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO) |
627 | |
628 | #define mtk_pctrl_get_in(hw, gpio) \ |
629 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI) |
630 | |
631 | #define mtk_pctrl_get_smt(hw, gpio) \ |
632 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT) |
633 | |
634 | #define mtk_pctrl_get_ies(hw, gpio) \ |
635 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES) |
636 | |
637 | #define mtk_pctrl_get_driving(hw, gpio) \ |
638 | mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV) |
639 | |
640 | ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, |
641 | unsigned int gpio, char *buf, unsigned int buf_len) |
642 | { |
643 | int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1; |
644 | const struct mtk_pin_desc *desc; |
645 | u32 try_all_type = 0; |
646 | |
647 | if (gpio >= hw->soc->npins) |
648 | return -EINVAL; |
649 | |
650 | if (mtk_is_virt_gpio(hw, gpio_n: gpio)) |
651 | return -EINVAL; |
652 | |
653 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
654 | pinmux = mtk_pctrl_get_pinmux(hw, gpio); |
655 | if (pinmux >= hw->soc->nfuncs) |
656 | pinmux -= hw->soc->nfuncs; |
657 | |
658 | mtk_pinconf_bias_get_combo(hw, desc, pullup: &pullup, enable: &pullen); |
659 | |
660 | if (hw->soc->pull_type) |
661 | try_all_type = hw->soc->pull_type[desc->number]; |
662 | |
663 | if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) { |
664 | rsel = pullen; |
665 | pullen = 1; |
666 | } else { |
667 | /* Case for: R1R0 */ |
668 | if (pullen == MTK_PUPD_SET_R1R0_00) { |
669 | pullen = 0; |
670 | r1 = 0; |
671 | r0 = 0; |
672 | } else if (pullen == MTK_PUPD_SET_R1R0_01) { |
673 | pullen = 1; |
674 | r1 = 0; |
675 | r0 = 1; |
676 | } else if (pullen == MTK_PUPD_SET_R1R0_10) { |
677 | pullen = 1; |
678 | r1 = 1; |
679 | r0 = 0; |
680 | } else if (pullen == MTK_PUPD_SET_R1R0_11) { |
681 | pullen = 1; |
682 | r1 = 1; |
683 | r0 = 1; |
684 | } |
685 | |
686 | /* Case for: RSEL */ |
687 | if (pullen >= MTK_PULL_SET_RSEL_000 && |
688 | pullen <= MTK_PULL_SET_RSEL_111) { |
689 | rsel = pullen - MTK_PULL_SET_RSEL_000; |
690 | pullen = 1; |
691 | } |
692 | } |
693 | len += scnprintf(buf: buf + len, size: buf_len - len, |
694 | fmt: "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d" , |
695 | gpio, |
696 | pinmux, |
697 | mtk_pctrl_get_direction(hw, gpio), |
698 | mtk_pctrl_get_out(hw, gpio), |
699 | mtk_pctrl_get_in(hw, gpio), |
700 | mtk_pctrl_get_driving(hw, gpio), |
701 | mtk_pctrl_get_smt(hw, gpio), |
702 | mtk_pctrl_get_ies(hw, gpio), |
703 | pullen, |
704 | pullup); |
705 | |
706 | if (r1 != -1) |
707 | len += scnprintf(buf: buf + len, size: buf_len - len, fmt: " (%1d %1d)" , r1, r0); |
708 | else if (rsel != -1) |
709 | len += scnprintf(buf: buf + len, size: buf_len - len, fmt: " (%1d)" , rsel); |
710 | |
711 | return len; |
712 | } |
713 | EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin); |
714 | |
715 | #define PIN_DBG_BUF_SZ 96 |
716 | static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
717 | unsigned int gpio) |
718 | { |
719 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
720 | char buf[PIN_DBG_BUF_SZ] = { 0 }; |
721 | |
722 | (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ); |
723 | |
724 | seq_printf(m: s, fmt: "%s" , buf); |
725 | } |
726 | |
727 | static const struct pinctrl_ops mtk_pctlops = { |
728 | .dt_node_to_map = mtk_pctrl_dt_node_to_map, |
729 | .dt_free_map = pinctrl_utils_free_map, |
730 | .get_groups_count = mtk_pctrl_get_groups_count, |
731 | .get_group_name = mtk_pctrl_get_group_name, |
732 | .get_group_pins = mtk_pctrl_get_group_pins, |
733 | .pin_dbg_show = mtk_pctrl_dbg_show, |
734 | }; |
735 | |
736 | static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
737 | { |
738 | return ARRAY_SIZE(mtk_gpio_functions); |
739 | } |
740 | |
741 | static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, |
742 | unsigned selector) |
743 | { |
744 | return mtk_gpio_functions[selector]; |
745 | } |
746 | |
747 | static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
748 | unsigned function, |
749 | const char * const **groups, |
750 | unsigned * const num_groups) |
751 | { |
752 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
753 | |
754 | *groups = hw->grp_names; |
755 | *num_groups = hw->soc->ngrps; |
756 | |
757 | return 0; |
758 | } |
759 | |
760 | static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, |
761 | unsigned function, |
762 | unsigned group) |
763 | { |
764 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
765 | struct mtk_pinctrl_group *grp = hw->groups + group; |
766 | const struct mtk_func_desc *desc_func; |
767 | const struct mtk_pin_desc *desc; |
768 | bool ret; |
769 | |
770 | ret = mtk_pctrl_is_function_valid(hw, pin_num: grp->pin, fnum: function); |
771 | if (!ret) { |
772 | dev_err(hw->dev, "invalid function %d on group %d .\n" , |
773 | function, group); |
774 | return -EINVAL; |
775 | } |
776 | |
777 | desc_func = mtk_pctrl_find_function_by_pin(hw, pin_num: grp->pin, fnum: function); |
778 | if (!desc_func) |
779 | return -EINVAL; |
780 | |
781 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin]; |
782 | return mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_MODE, value: desc_func->muxval); |
783 | } |
784 | |
785 | static const struct pinmux_ops mtk_pmxops = { |
786 | .get_functions_count = mtk_pmx_get_funcs_cnt, |
787 | .get_function_name = mtk_pmx_get_func_name, |
788 | .get_function_groups = mtk_pmx_get_func_groups, |
789 | .set_mux = mtk_pmx_set_mux, |
790 | .gpio_set_direction = mtk_pinmux_gpio_set_direction, |
791 | .gpio_request_enable = mtk_pinmux_gpio_request_enable, |
792 | }; |
793 | |
794 | static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, |
795 | unsigned long *config) |
796 | { |
797 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
798 | struct mtk_pinctrl_group *grp = &hw->groups[group]; |
799 | |
800 | /* One pin per group only */ |
801 | return mtk_pinconf_get(pctldev, pin: grp->pin, config); |
802 | } |
803 | |
804 | static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
805 | unsigned long *configs, unsigned num_configs) |
806 | { |
807 | struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); |
808 | struct mtk_pinctrl_group *grp = &hw->groups[group]; |
809 | bool drive_strength_uA_found = false; |
810 | bool adv_drve_strength_found = false; |
811 | int i, ret; |
812 | |
813 | for (i = 0; i < num_configs; i++) { |
814 | ret = mtk_pinconf_set(pctldev, pin: grp->pin, |
815 | param: pinconf_to_config_param(config: configs[i]), |
816 | arg: pinconf_to_config_argument(config: configs[i])); |
817 | if (ret < 0) |
818 | return ret; |
819 | |
820 | if (pinconf_to_config_param(config: configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA) |
821 | drive_strength_uA_found = true; |
822 | if (pinconf_to_config_param(config: configs[i]) == MTK_PIN_CONFIG_DRV_ADV) |
823 | adv_drve_strength_found = true; |
824 | } |
825 | |
826 | /* |
827 | * Disable advanced drive strength mode if drive-strength-microamp |
828 | * is not set. However, mediatek,drive-strength-adv takes precedence |
829 | * as its value can explicitly request the mode be enabled or not. |
830 | */ |
831 | if (hw->soc->adv_drive_set && !drive_strength_uA_found && |
832 | !adv_drve_strength_found) |
833 | hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0); |
834 | |
835 | return 0; |
836 | } |
837 | |
838 | static const struct pinconf_ops mtk_confops = { |
839 | .pin_config_get = mtk_pinconf_get, |
840 | .pin_config_group_get = mtk_pconf_group_get, |
841 | .pin_config_group_set = mtk_pconf_group_set, |
842 | .is_generic = true, |
843 | }; |
844 | |
845 | static struct pinctrl_desc mtk_desc = { |
846 | .name = PINCTRL_PINCTRL_DEV, |
847 | .pctlops = &mtk_pctlops, |
848 | .pmxops = &mtk_pmxops, |
849 | .confops = &mtk_confops, |
850 | .owner = THIS_MODULE, |
851 | }; |
852 | |
853 | static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) |
854 | { |
855 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
856 | const struct mtk_pin_desc *desc; |
857 | int value, err; |
858 | |
859 | if (gpio >= hw->soc->npins) |
860 | return -EINVAL; |
861 | |
862 | /* |
863 | * "Virtual" GPIOs are always and only used for interrupts |
864 | * Since they are only used for interrupts, they are always inputs |
865 | */ |
866 | if (mtk_is_virt_gpio(hw, gpio_n: gpio)) |
867 | return 1; |
868 | |
869 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
870 | |
871 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_DIR, value: &value); |
872 | if (err) |
873 | return err; |
874 | |
875 | if (value) |
876 | return GPIO_LINE_DIRECTION_OUT; |
877 | |
878 | return GPIO_LINE_DIRECTION_IN; |
879 | } |
880 | |
881 | static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) |
882 | { |
883 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
884 | const struct mtk_pin_desc *desc; |
885 | int value, err; |
886 | |
887 | if (gpio >= hw->soc->npins) |
888 | return -EINVAL; |
889 | |
890 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
891 | |
892 | err = mtk_hw_get_value(hw, desc, field: PINCTRL_PIN_REG_DI, value: &value); |
893 | if (err) |
894 | return err; |
895 | |
896 | return !!value; |
897 | } |
898 | |
899 | static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) |
900 | { |
901 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
902 | const struct mtk_pin_desc *desc; |
903 | |
904 | if (gpio >= hw->soc->npins) |
905 | return; |
906 | |
907 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; |
908 | |
909 | mtk_hw_set_value(hw, desc, field: PINCTRL_PIN_REG_DO, value: !!value); |
910 | } |
911 | |
912 | static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) |
913 | { |
914 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
915 | |
916 | if (gpio >= hw->soc->npins) |
917 | return -EINVAL; |
918 | |
919 | return pinctrl_gpio_direction_input(gc: chip, offset: gpio); |
920 | } |
921 | |
922 | static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, |
923 | int value) |
924 | { |
925 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
926 | |
927 | if (gpio >= hw->soc->npins) |
928 | return -EINVAL; |
929 | |
930 | mtk_gpio_set(chip, gpio, value); |
931 | |
932 | return pinctrl_gpio_direction_output(gc: chip, offset: gpio); |
933 | } |
934 | |
935 | static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) |
936 | { |
937 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
938 | const struct mtk_pin_desc *desc; |
939 | |
940 | if (!hw->eint) |
941 | return -ENOTSUPP; |
942 | |
943 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; |
944 | |
945 | if (desc->eint.eint_n == EINT_NA) |
946 | return -ENOTSUPP; |
947 | |
948 | return mtk_eint_find_irq(eint: hw->eint, eint_n: desc->eint.eint_n); |
949 | } |
950 | |
951 | static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
952 | unsigned long config) |
953 | { |
954 | struct mtk_pinctrl *hw = gpiochip_get_data(gc: chip); |
955 | const struct mtk_pin_desc *desc; |
956 | u32 debounce; |
957 | |
958 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; |
959 | |
960 | if (!hw->eint || |
961 | pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || |
962 | desc->eint.eint_n == EINT_NA) |
963 | return -ENOTSUPP; |
964 | |
965 | debounce = pinconf_to_config_argument(config); |
966 | |
967 | return mtk_eint_set_debounce(eint: hw->eint, eint_n: desc->eint.eint_n, debounce); |
968 | } |
969 | |
970 | static int mtk_build_gpiochip(struct mtk_pinctrl *hw) |
971 | { |
972 | struct gpio_chip *chip = &hw->chip; |
973 | int ret; |
974 | |
975 | chip->label = PINCTRL_PINCTRL_DEV; |
976 | chip->parent = hw->dev; |
977 | chip->request = gpiochip_generic_request; |
978 | chip->free = gpiochip_generic_free; |
979 | chip->get_direction = mtk_gpio_get_direction; |
980 | chip->direction_input = mtk_gpio_direction_input; |
981 | chip->direction_output = mtk_gpio_direction_output; |
982 | chip->get = mtk_gpio_get; |
983 | chip->set = mtk_gpio_set; |
984 | chip->to_irq = mtk_gpio_to_irq; |
985 | chip->set_config = mtk_gpio_set_config; |
986 | chip->base = -1; |
987 | chip->ngpio = hw->soc->npins; |
988 | |
989 | ret = gpiochip_add_data(chip, hw); |
990 | if (ret < 0) |
991 | return ret; |
992 | |
993 | return 0; |
994 | } |
995 | |
996 | static int mtk_pctrl_build_state(struct platform_device *pdev) |
997 | { |
998 | struct mtk_pinctrl *hw = platform_get_drvdata(pdev); |
999 | int i; |
1000 | |
1001 | /* Allocate groups */ |
1002 | hw->groups = devm_kmalloc_array(dev: &pdev->dev, n: hw->soc->ngrps, |
1003 | size: sizeof(*hw->groups), GFP_KERNEL); |
1004 | if (!hw->groups) |
1005 | return -ENOMEM; |
1006 | |
1007 | /* We assume that one pin is one group, use pin name as group name. */ |
1008 | hw->grp_names = devm_kmalloc_array(dev: &pdev->dev, n: hw->soc->ngrps, |
1009 | size: sizeof(*hw->grp_names), GFP_KERNEL); |
1010 | if (!hw->grp_names) |
1011 | return -ENOMEM; |
1012 | |
1013 | for (i = 0; i < hw->soc->npins; i++) { |
1014 | const struct mtk_pin_desc *pin = hw->soc->pins + i; |
1015 | struct mtk_pinctrl_group *group = hw->groups + i; |
1016 | |
1017 | group->name = pin->name; |
1018 | group->pin = pin->number; |
1019 | |
1020 | hw->grp_names[i] = pin->name; |
1021 | } |
1022 | |
1023 | return 0; |
1024 | } |
1025 | |
1026 | int mtk_paris_pinctrl_probe(struct platform_device *pdev) |
1027 | { |
1028 | struct device *dev = &pdev->dev; |
1029 | struct pinctrl_pin_desc *pins; |
1030 | struct mtk_pinctrl *hw; |
1031 | int err, i; |
1032 | |
1033 | hw = devm_kzalloc(dev: &pdev->dev, size: sizeof(*hw), GFP_KERNEL); |
1034 | if (!hw) |
1035 | return -ENOMEM; |
1036 | |
1037 | platform_set_drvdata(pdev, data: hw); |
1038 | |
1039 | hw->soc = device_get_match_data(dev); |
1040 | if (!hw->soc) |
1041 | return -ENOENT; |
1042 | |
1043 | hw->dev = &pdev->dev; |
1044 | |
1045 | if (!hw->soc->nbase_names) |
1046 | return dev_err_probe(dev, err: -EINVAL, |
1047 | fmt: "SoC should be assigned at least one register base\n" ); |
1048 | |
1049 | hw->base = devm_kmalloc_array(dev: &pdev->dev, n: hw->soc->nbase_names, |
1050 | size: sizeof(*hw->base), GFP_KERNEL); |
1051 | if (!hw->base) |
1052 | return -ENOMEM; |
1053 | |
1054 | for (i = 0; i < hw->soc->nbase_names; i++) { |
1055 | hw->base[i] = devm_platform_ioremap_resource_byname(pdev, |
1056 | name: hw->soc->base_names[i]); |
1057 | if (IS_ERR(ptr: hw->base[i])) |
1058 | return PTR_ERR(ptr: hw->base[i]); |
1059 | } |
1060 | |
1061 | hw->nbase = hw->soc->nbase_names; |
1062 | |
1063 | if (of_find_property(np: hw->dev->of_node, |
1064 | name: "mediatek,rsel-resistance-in-si-unit" , NULL)) |
1065 | hw->rsel_si_unit = true; |
1066 | else |
1067 | hw->rsel_si_unit = false; |
1068 | |
1069 | spin_lock_init(&hw->lock); |
1070 | |
1071 | err = mtk_pctrl_build_state(pdev); |
1072 | if (err) |
1073 | return dev_err_probe(dev, err, fmt: "build state failed\n" ); |
1074 | |
1075 | /* Copy from internal struct mtk_pin_desc to register to the core */ |
1076 | pins = devm_kmalloc_array(dev: &pdev->dev, n: hw->soc->npins, size: sizeof(*pins), |
1077 | GFP_KERNEL); |
1078 | if (!pins) |
1079 | return -ENOMEM; |
1080 | |
1081 | for (i = 0; i < hw->soc->npins; i++) { |
1082 | pins[i].number = hw->soc->pins[i].number; |
1083 | pins[i].name = hw->soc->pins[i].name; |
1084 | } |
1085 | |
1086 | /* Setup pins descriptions per SoC types */ |
1087 | mtk_desc.pins = (const struct pinctrl_pin_desc *)pins; |
1088 | mtk_desc.npins = hw->soc->npins; |
1089 | mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); |
1090 | mtk_desc.custom_params = mtk_custom_bindings; |
1091 | #ifdef CONFIG_DEBUG_FS |
1092 | mtk_desc.custom_conf_items = mtk_conf_items; |
1093 | #endif |
1094 | |
1095 | err = devm_pinctrl_register_and_init(dev: &pdev->dev, pctldesc: &mtk_desc, driver_data: hw, |
1096 | pctldev: &hw->pctrl); |
1097 | if (err) |
1098 | return err; |
1099 | |
1100 | err = pinctrl_enable(pctldev: hw->pctrl); |
1101 | if (err) |
1102 | return err; |
1103 | |
1104 | err = mtk_build_eint(hw, pdev); |
1105 | if (err) |
1106 | dev_warn(&pdev->dev, |
1107 | "Failed to add EINT, but pinctrl still can work\n" ); |
1108 | |
1109 | /* Build gpiochip should be after pinctrl_enable is done */ |
1110 | err = mtk_build_gpiochip(hw); |
1111 | if (err) |
1112 | return dev_err_probe(dev, err, fmt: "Failed to add gpio_chip\n" ); |
1113 | |
1114 | platform_set_drvdata(pdev, data: hw); |
1115 | |
1116 | return 0; |
1117 | } |
1118 | EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe); |
1119 | |
1120 | static int mtk_paris_pinctrl_suspend(struct device *device) |
1121 | { |
1122 | struct mtk_pinctrl *pctl = dev_get_drvdata(dev: device); |
1123 | |
1124 | return mtk_eint_do_suspend(eint: pctl->eint); |
1125 | } |
1126 | |
1127 | static int mtk_paris_pinctrl_resume(struct device *device) |
1128 | { |
1129 | struct mtk_pinctrl *pctl = dev_get_drvdata(dev: device); |
1130 | |
1131 | return mtk_eint_do_resume(eint: pctl->eint); |
1132 | } |
1133 | |
1134 | EXPORT_GPL_DEV_SLEEP_PM_OPS(mtk_paris_pinctrl_pm_ops) = { |
1135 | NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_paris_pinctrl_suspend, mtk_paris_pinctrl_resume) |
1136 | }; |
1137 | |
1138 | MODULE_LICENSE("GPL v2" ); |
1139 | MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris" ); |
1140 | |