1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (C) 2014 STMicroelectronics (R&D) Limited |
4 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
5 | */ |
6 | #include <linux/module.h> |
7 | #include <linux/of.h> |
8 | #include <linux/of_platform.h> |
9 | #include <linux/platform_device.h> |
10 | #include <dt-bindings/reset/stih407-resets.h> |
11 | #include "reset-syscfg.h" |
12 | |
13 | /* STiH407 Peripheral powerdown definitions. */ |
14 | static const char stih407_core[] = "st,stih407-core-syscfg" ; |
15 | static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg" ; |
16 | static const char stih407_lpm[] = "st,stih407-lpm-syscfg" ; |
17 | |
18 | #define STIH407_PDN_0(_bit) \ |
19 | _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) |
20 | #define STIH407_PDN_1(_bit) \ |
21 | _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) |
22 | #define STIH407_PDN_ETH(_bit, _stat) \ |
23 | _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) |
24 | |
25 | /* Powerdown requests control 0 */ |
26 | #define SYSCFG_5000 0x0 |
27 | #define SYSSTAT_5500 0x7d0 |
28 | /* Powerdown requests control 1 (High Speed Links) */ |
29 | #define SYSCFG_5001 0x4 |
30 | #define SYSSTAT_5501 0x7d4 |
31 | |
32 | /* Ethernet powerdown/status/reset */ |
33 | #define SYSCFG_4032 0x80 |
34 | #define SYSSTAT_4520 0x820 |
35 | #define SYSCFG_4002 0x8 |
36 | |
37 | static const struct syscfg_reset_channel_data stih407_powerdowns[] = { |
38 | [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), |
39 | [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), |
40 | [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), |
41 | [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), |
42 | [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), |
43 | [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), |
44 | [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), |
45 | [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), |
46 | [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), |
47 | [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), |
48 | }; |
49 | |
50 | /* Reset Generator control 0/1 */ |
51 | #define SYSCFG_5128 0x200 |
52 | #define SYSCFG_5131 0x20c |
53 | #define SYSCFG_5132 0x210 |
54 | |
55 | #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ |
56 | |
57 | #define STIH407_SRST_CORE(_reg, _bit) \ |
58 | _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) |
59 | |
60 | #define STIH407_SRST_SBC(_reg, _bit) \ |
61 | _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) |
62 | |
63 | #define STIH407_SRST_LPM(_reg, _bit) \ |
64 | _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) |
65 | |
66 | static const struct syscfg_reset_channel_data stih407_softresets[] = { |
67 | [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), |
68 | [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), |
69 | [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), |
70 | [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), |
71 | [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), |
72 | [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), |
73 | [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), |
74 | [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), |
75 | [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), |
76 | [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), |
77 | [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), |
78 | [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), |
79 | [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), |
80 | [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), |
81 | [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), |
82 | [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), |
83 | [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), |
84 | [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), |
85 | [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), |
86 | [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), |
87 | [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), |
88 | [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), |
89 | [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), |
90 | [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), |
91 | [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), |
92 | [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), |
93 | [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), |
94 | [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), |
95 | [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), |
96 | [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26), |
97 | [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27), |
98 | [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28), |
99 | [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2), |
100 | }; |
101 | |
102 | /* PicoPHY reset/control */ |
103 | #define SYSCFG_5061 0x0f4 |
104 | |
105 | static const struct syscfg_reset_channel_data stih407_picophyresets[] = { |
106 | [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), |
107 | [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), |
108 | [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), |
109 | }; |
110 | |
111 | static const struct syscfg_reset_controller_data stih407_powerdown_controller = { |
112 | .wait_for_ack = true, |
113 | .nr_channels = ARRAY_SIZE(stih407_powerdowns), |
114 | .channels = stih407_powerdowns, |
115 | }; |
116 | |
117 | static const struct syscfg_reset_controller_data stih407_softreset_controller = { |
118 | .wait_for_ack = false, |
119 | .active_low = true, |
120 | .nr_channels = ARRAY_SIZE(stih407_softresets), |
121 | .channels = stih407_softresets, |
122 | }; |
123 | |
124 | static const struct syscfg_reset_controller_data stih407_picophyreset_controller = { |
125 | .wait_for_ack = false, |
126 | .nr_channels = ARRAY_SIZE(stih407_picophyresets), |
127 | .channels = stih407_picophyresets, |
128 | }; |
129 | |
130 | static const struct of_device_id stih407_reset_match[] = { |
131 | { |
132 | .compatible = "st,stih407-powerdown" , |
133 | .data = &stih407_powerdown_controller, |
134 | }, |
135 | { |
136 | .compatible = "st,stih407-softreset" , |
137 | .data = &stih407_softreset_controller, |
138 | }, |
139 | { |
140 | .compatible = "st,stih407-picophyreset" , |
141 | .data = &stih407_picophyreset_controller, |
142 | }, |
143 | { /* sentinel */ }, |
144 | }; |
145 | |
146 | static struct platform_driver stih407_reset_driver = { |
147 | .probe = syscfg_reset_probe, |
148 | .driver = { |
149 | .name = "reset-stih407" , |
150 | .of_match_table = stih407_reset_match, |
151 | }, |
152 | }; |
153 | |
154 | static int __init stih407_reset_init(void) |
155 | { |
156 | return platform_driver_register(&stih407_reset_driver); |
157 | } |
158 | |
159 | arch_initcall(stih407_reset_init); |
160 | |