1 | /* |
2 | 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux. |
3 | |
4 | Written By: Adam Radford <aradford@gmail.com> |
5 | Modifications By: Tom Couch |
6 | |
7 | Copyright (C) 2004-2009 Applied Micro Circuits Corporation. |
8 | Copyright (C) 2010 LSI Corporation. |
9 | |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by |
12 | the Free Software Foundation; version 2 of the License. |
13 | |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | GNU General Public License for more details. |
18 | |
19 | NO WARRANTY |
20 | THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR |
21 | CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT |
22 | LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, |
23 | MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is |
24 | solely responsible for determining the appropriateness of using and |
25 | distributing the Program and assumes all risks associated with its |
26 | exercise of rights under this Agreement, including but not limited to |
27 | the risks and costs of program errors, damage to or loss of data, |
28 | programs or equipment, and unavailability or interruption of operations. |
29 | |
30 | DISCLAIMER OF LIABILITY |
31 | NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY |
32 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
33 | DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND |
34 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
35 | TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
36 | USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED |
37 | HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES |
38 | |
39 | You should have received a copy of the GNU General Public License |
40 | along with this program; if not, write to the Free Software |
41 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
42 | |
43 | Bugs/Comments/Suggestions should be mailed to: |
44 | aradford@gmail.com |
45 | */ |
46 | |
47 | #ifndef _3W_9XXX_H |
48 | #define _3W_9XXX_H |
49 | |
50 | /* AEN string type */ |
51 | typedef struct TAG_twa_message_type { |
52 | unsigned int code; |
53 | char *text; |
54 | } twa_message_type; |
55 | |
56 | /* AEN strings */ |
57 | static twa_message_type twa_aen_table[] = { |
58 | {0x0000, "AEN queue empty" }, |
59 | {0x0001, "Controller reset occurred" }, |
60 | {0x0002, "Degraded unit detected" }, |
61 | {0x0003, "Controller error occurred" }, |
62 | {0x0004, "Background rebuild failed" }, |
63 | {0x0005, "Background rebuild done" }, |
64 | {0x0006, "Incomplete unit detected" }, |
65 | {0x0007, "Background initialize done" }, |
66 | {0x0008, "Unclean shutdown detected" }, |
67 | {0x0009, "Drive timeout detected" }, |
68 | {0x000A, "Drive error detected" }, |
69 | {0x000B, "Rebuild started" }, |
70 | {0x000C, "Background initialize started" }, |
71 | {0x000D, "Entire logical unit was deleted" }, |
72 | {0x000E, "Background initialize failed" }, |
73 | {0x000F, "SMART attribute exceeded threshold" }, |
74 | {0x0010, "Power supply reported AC under range" }, |
75 | {0x0011, "Power supply reported DC out of range" }, |
76 | {0x0012, "Power supply reported a malfunction" }, |
77 | {0x0013, "Power supply predicted malfunction" }, |
78 | {0x0014, "Battery charge is below threshold" }, |
79 | {0x0015, "Fan speed is below threshold" }, |
80 | {0x0016, "Temperature sensor is above threshold" }, |
81 | {0x0017, "Power supply was removed" }, |
82 | {0x0018, "Power supply was inserted" }, |
83 | {0x0019, "Drive was removed from a bay" }, |
84 | {0x001A, "Drive was inserted into a bay" }, |
85 | {0x001B, "Drive bay cover door was opened" }, |
86 | {0x001C, "Drive bay cover door was closed" }, |
87 | {0x001D, "Product case was opened" }, |
88 | {0x0020, "Prepare for shutdown (power-off)" }, |
89 | {0x0021, "Downgrade UDMA mode to lower speed" }, |
90 | {0x0022, "Upgrade UDMA mode to higher speed" }, |
91 | {0x0023, "Sector repair completed" }, |
92 | {0x0024, "Sbuf memory test failed" }, |
93 | {0x0025, "Error flushing cached write data to array" }, |
94 | {0x0026, "Drive reported data ECC error" }, |
95 | {0x0027, "DCB has checksum error" }, |
96 | {0x0028, "DCB version is unsupported" }, |
97 | {0x0029, "Background verify started" }, |
98 | {0x002A, "Background verify failed" }, |
99 | {0x002B, "Background verify done" }, |
100 | {0x002C, "Bad sector overwritten during rebuild" }, |
101 | {0x002D, "Background rebuild error on source drive" }, |
102 | {0x002E, "Replace failed because replacement drive too small" }, |
103 | {0x002F, "Verify failed because array was never initialized" }, |
104 | {0x0030, "Unsupported ATA drive" }, |
105 | {0x0031, "Synchronize host/controller time" }, |
106 | {0x0032, "Spare capacity is inadequate for some units" }, |
107 | {0x0033, "Background migration started" }, |
108 | {0x0034, "Background migration failed" }, |
109 | {0x0035, "Background migration done" }, |
110 | {0x0036, "Verify detected and fixed data/parity mismatch" }, |
111 | {0x0037, "SO-DIMM incompatible" }, |
112 | {0x0038, "SO-DIMM not detected" }, |
113 | {0x0039, "Corrected Sbuf ECC error" }, |
114 | {0x003A, "Drive power on reset detected" }, |
115 | {0x003B, "Background rebuild paused" }, |
116 | {0x003C, "Background initialize paused" }, |
117 | {0x003D, "Background verify paused" }, |
118 | {0x003E, "Background migration paused" }, |
119 | {0x003F, "Corrupt flash file system detected" }, |
120 | {0x0040, "Flash file system repaired" }, |
121 | {0x0041, "Unit number assignments were lost" }, |
122 | {0x0042, "Error during read of primary DCB" }, |
123 | {0x0043, "Latent error found in backup DCB" }, |
124 | {0x00FC, "Recovered/finished array membership update" }, |
125 | {0x00FD, "Handler lockup" }, |
126 | {0x00FE, "Retrying PCI transfer" }, |
127 | {0x00FF, "AEN queue is full" }, |
128 | {0xFFFFFFFF, (char*) 0} |
129 | }; |
130 | |
131 | /* AEN severity table */ |
132 | static char *twa_aen_severity_table[] = |
133 | { |
134 | "None" , "ERROR" , "WARNING" , "INFO" , "DEBUG" , (char*) 0 |
135 | }; |
136 | |
137 | /* Error strings */ |
138 | static twa_message_type twa_error_table[] = { |
139 | {0x0100, "SGL entry contains zero data" }, |
140 | {0x0101, "Invalid command opcode" }, |
141 | {0x0102, "SGL entry has unaligned address" }, |
142 | {0x0103, "SGL size does not match command" }, |
143 | {0x0104, "SGL entry has illegal length" }, |
144 | {0x0105, "Command packet is not aligned" }, |
145 | {0x0106, "Invalid request ID" }, |
146 | {0x0107, "Duplicate request ID" }, |
147 | {0x0108, "ID not locked" }, |
148 | {0x0109, "LBA out of range" }, |
149 | {0x010A, "Logical unit not supported" }, |
150 | {0x010B, "Parameter table does not exist" }, |
151 | {0x010C, "Parameter index does not exist" }, |
152 | {0x010D, "Invalid field in CDB" }, |
153 | {0x010E, "Specified port has invalid drive" }, |
154 | {0x010F, "Parameter item size mismatch" }, |
155 | {0x0110, "Failed memory allocation" }, |
156 | {0x0111, "Memory request too large" }, |
157 | {0x0112, "Out of memory segments" }, |
158 | {0x0113, "Invalid address to deallocate" }, |
159 | {0x0114, "Out of memory" }, |
160 | {0x0115, "Out of heap" }, |
161 | {0x0120, "Double degrade" }, |
162 | {0x0121, "Drive not degraded" }, |
163 | {0x0122, "Reconstruct error" }, |
164 | {0x0123, "Replace not accepted" }, |
165 | {0x0124, "Replace drive capacity too small" }, |
166 | {0x0125, "Sector count not allowed" }, |
167 | {0x0126, "No spares left" }, |
168 | {0x0127, "Reconstruct error" }, |
169 | {0x0128, "Unit is offline" }, |
170 | {0x0129, "Cannot update status to DCB" }, |
171 | {0x0130, "Invalid stripe handle" }, |
172 | {0x0131, "Handle that was not locked" }, |
173 | {0x0132, "Handle that was not empty" }, |
174 | {0x0133, "Handle has different owner" }, |
175 | {0x0140, "IPR has parent" }, |
176 | {0x0150, "Illegal Pbuf address alignment" }, |
177 | {0x0151, "Illegal Pbuf transfer length" }, |
178 | {0x0152, "Illegal Sbuf address alignment" }, |
179 | {0x0153, "Illegal Sbuf transfer length" }, |
180 | {0x0160, "Command packet too large" }, |
181 | {0x0161, "SGL exceeds maximum length" }, |
182 | {0x0162, "SGL has too many entries" }, |
183 | {0x0170, "Insufficient resources for rebuilder" }, |
184 | {0x0171, "Verify error (data != parity)" }, |
185 | {0x0180, "Requested segment not in directory of this DCB" }, |
186 | {0x0181, "DCB segment has unsupported version" }, |
187 | {0x0182, "DCB segment has checksum error" }, |
188 | {0x0183, "DCB support (settings) segment invalid" }, |
189 | {0x0184, "DCB UDB (unit descriptor block) segment invalid" }, |
190 | {0x0185, "DCB GUID (globally unique identifier) segment invalid" }, |
191 | {0x01A0, "Could not clear Sbuf" }, |
192 | {0x01C0, "Flash identify failed" }, |
193 | {0x01C1, "Flash out of bounds" }, |
194 | {0x01C2, "Flash verify error" }, |
195 | {0x01C3, "Flash file object not found" }, |
196 | {0x01C4, "Flash file already present" }, |
197 | {0x01C5, "Flash file system full" }, |
198 | {0x01C6, "Flash file not present" }, |
199 | {0x01C7, "Flash file size error" }, |
200 | {0x01C8, "Bad flash file checksum" }, |
201 | {0x01CA, "Corrupt flash file system detected" }, |
202 | {0x01D0, "Invalid field in parameter list" }, |
203 | {0x01D1, "Parameter list length error" }, |
204 | {0x01D2, "Parameter item is not changeable" }, |
205 | {0x01D3, "Parameter item is not saveable" }, |
206 | {0x0200, "UDMA CRC error" }, |
207 | {0x0201, "Internal CRC error" }, |
208 | {0x0202, "Data ECC error" }, |
209 | {0x0203, "ADP level 1 error" }, |
210 | {0x0204, "Port timeout" }, |
211 | {0x0205, "Drive power on reset" }, |
212 | {0x0206, "ADP level 2 error" }, |
213 | {0x0207, "Soft reset failed" }, |
214 | {0x0208, "Drive not ready" }, |
215 | {0x0209, "Unclassified port error" }, |
216 | {0x020A, "Drive aborted command" }, |
217 | {0x0210, "Internal CRC error" }, |
218 | {0x0211, "PCI abort error" }, |
219 | {0x0212, "PCI parity error" }, |
220 | {0x0213, "Port handler error" }, |
221 | {0x0214, "Token interrupt count error" }, |
222 | {0x0215, "Timeout waiting for PCI transfer" }, |
223 | {0x0216, "Corrected buffer ECC" }, |
224 | {0x0217, "Uncorrected buffer ECC" }, |
225 | {0x0230, "Unsupported command during flash recovery" }, |
226 | {0x0231, "Next image buffer expected" }, |
227 | {0x0232, "Binary image architecture incompatible" }, |
228 | {0x0233, "Binary image has no signature" }, |
229 | {0x0234, "Binary image has bad checksum" }, |
230 | {0x0235, "Image downloaded overflowed buffer" }, |
231 | {0x0240, "I2C device not found" }, |
232 | {0x0241, "I2C transaction aborted" }, |
233 | {0x0242, "SO-DIMM parameter(s) incompatible using defaults" }, |
234 | {0x0243, "SO-DIMM unsupported" }, |
235 | {0x0248, "SPI transfer status error" }, |
236 | {0x0249, "SPI transfer timeout error" }, |
237 | {0x0250, "Invalid unit descriptor size in CreateUnit" }, |
238 | {0x0251, "Unit descriptor size exceeds data buffer in CreateUnit" }, |
239 | {0x0252, "Invalid value in CreateUnit descriptor" }, |
240 | {0x0253, "Inadequate disk space to support descriptor in CreateUnit" }, |
241 | {0x0254, "Unable to create data channel for this unit descriptor" }, |
242 | {0x0255, "CreateUnit descriptor specifies a drive already in use" }, |
243 | {0x0256, "Unable to write configuration to all disks during CreateUnit" }, |
244 | {0x0257, "CreateUnit does not support this descriptor version" }, |
245 | {0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit" }, |
246 | {0x0259, "Too many descriptors in CreateUnit" }, |
247 | {0x025A, "Invalid configuration specified in CreateUnit descriptor" }, |
248 | {0x025B, "Invalid LBA offset specified in CreateUnit descriptor" }, |
249 | {0x025C, "Invalid stripelet size specified in CreateUnit descriptor" }, |
250 | {0x0260, "SMART attribute exceeded threshold" }, |
251 | {0xFFFFFFFF, (char*) 0} |
252 | }; |
253 | |
254 | /* Control register bit definitions */ |
255 | #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 |
256 | #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 |
257 | #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 |
258 | #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 |
259 | #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 |
260 | #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 |
261 | #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200 |
262 | #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100 |
263 | #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080 |
264 | #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040 |
265 | #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 |
266 | #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 |
267 | #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 |
268 | #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 |
269 | |
270 | /* Status register bit definitions */ |
271 | #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 |
272 | #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000 |
273 | #define TW_STATUS_PCI_PARITY_ERROR 0x00800000 |
274 | #define TW_STATUS_QUEUE_ERROR 0x00400000 |
275 | #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000 |
276 | #define TW_STATUS_PCI_ABORT 0x00100000 |
277 | #define TW_STATUS_HOST_INTERRUPT 0x00080000 |
278 | #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000 |
279 | #define TW_STATUS_COMMAND_INTERRUPT 0x00020000 |
280 | #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000 |
281 | #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000 |
282 | #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 |
283 | #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 |
284 | #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 |
285 | #define TW_STATUS_EXPECTED_BITS 0x00002000 |
286 | #define TW_STATUS_UNEXPECTED_BITS 0x00F00000 |
287 | #define TW_STATUS_VALID_INTERRUPT 0x00DF0000 |
288 | |
289 | /* PCI related defines */ |
290 | #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100 |
291 | #define TW_PCI_CLEAR_PCI_ABORT 0x2000 |
292 | |
293 | /* Command packet opcodes used by the driver */ |
294 | #define TW_OP_INIT_CONNECTION 0x1 |
295 | #define TW_OP_GET_PARAM 0x12 |
296 | #define TW_OP_SET_PARAM 0x13 |
297 | #define TW_OP_EXECUTE_SCSI 0x10 |
298 | #define TW_OP_DOWNLOAD_FIRMWARE 0x16 |
299 | #define TW_OP_RESET 0x1C |
300 | |
301 | /* Asynchronous Event Notification (AEN) codes used by the driver */ |
302 | #define TW_AEN_QUEUE_EMPTY 0x0000 |
303 | #define TW_AEN_SOFT_RESET 0x0001 |
304 | #define TW_AEN_SYNC_TIME_WITH_HOST 0x031 |
305 | #define TW_AEN_SEVERITY_ERROR 0x1 |
306 | #define TW_AEN_SEVERITY_DEBUG 0x4 |
307 | #define TW_AEN_NOT_RETRIEVED 0x1 |
308 | #define TW_AEN_RETRIEVED 0x2 |
309 | |
310 | /* Command state defines */ |
311 | #define TW_S_INITIAL 0x1 /* Initial state */ |
312 | #define TW_S_STARTED 0x2 /* Id in use */ |
313 | #define TW_S_POSTED 0x4 /* Posted to the controller */ |
314 | #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */ |
315 | #define TW_S_COMPLETED 0x10 /* Completed by isr */ |
316 | #define TW_S_FINISHED 0x20 /* I/O completely done */ |
317 | |
318 | /* Compatibility defines */ |
319 | #define TW_9000_ARCH_ID 0x5 |
320 | #define TW_CURRENT_DRIVER_SRL 35 |
321 | #define TW_CURRENT_DRIVER_BUILD 0 |
322 | #define TW_CURRENT_DRIVER_BRANCH 0 |
323 | |
324 | /* Misc defines */ |
325 | #define TW_9550SX_DRAIN_COMPLETED 0xFFFF |
326 | #define TW_SECTOR_SIZE 512 |
327 | #define TW_ALIGNMENT_9000 4 /* 4 bytes */ |
328 | #define TW_ALIGNMENT_9000_SGL 0x3 |
329 | #define TW_MAX_UNITS 16 |
330 | #define TW_MAX_UNITS_9650SE 32 |
331 | #define TW_INIT_MESSAGE_CREDITS 0x100 |
332 | #define TW_INIT_COMMAND_PACKET_SIZE 0x3 |
333 | #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6 |
334 | #define TW_EXTENDED_INIT_CONNECT 0x2 |
335 | #define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4 |
336 | #define TW_CTLR_FW_RECOMMENDS_FLASH 0x8 |
337 | #define TW_CTLR_FW_COMPATIBLE 0x2 |
338 | #define TW_BASE_FW_SRL 24 |
339 | #define TW_BASE_FW_BRANCH 0 |
340 | #define TW_BASE_FW_BUILD 1 |
341 | #define TW_FW_SRL_LUNS_SUPPORTED 28 |
342 | #define TW_Q_LENGTH 256 |
343 | #define TW_Q_START 0 |
344 | #define TW_MAX_SLOT 32 |
345 | #define TW_MAX_RESET_TRIES 2 |
346 | #define TW_MAX_CMDS_PER_LUN 254 |
347 | #define TW_MAX_RESPONSE_DRAIN 256 |
348 | #define TW_MAX_AEN_DRAIN 255 |
349 | #define TW_IN_RESET 2 |
350 | #define TW_USING_MSI 3 |
351 | #define TW_IN_ATTENTION_LOOP 4 |
352 | #define TW_MAX_SECTORS 256 |
353 | #define TW_AEN_WAIT_TIME 1000 |
354 | #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ |
355 | #define TW_MAX_CDB_LEN 16 |
356 | #define TW_ISR_DONT_COMPLETE 2 |
357 | #define TW_ISR_DONT_RESULT 3 |
358 | #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ |
359 | #define TW_IOCTL_CHRDEV_FREE -1 |
360 | #define TW_COMMAND_OFFSET 128 /* 128 bytes */ |
361 | #define TW_VERSION_TABLE 0x0402 |
362 | #define TW_TIMEKEEP_TABLE 0x040A |
363 | #define TW_INFORMATION_TABLE 0x0403 |
364 | #define TW_PARAM_FWVER 3 |
365 | #define TW_PARAM_FWVER_LENGTH 16 |
366 | #define TW_PARAM_BIOSVER 4 |
367 | #define TW_PARAM_BIOSVER_LENGTH 16 |
368 | #define TW_PARAM_PORTCOUNT 3 |
369 | #define TW_PARAM_PORTCOUNT_LENGTH 1 |
370 | #define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */ |
371 | #define TW_MAX_SENSE_LENGTH 256 |
372 | #define TW_EVENT_SOURCE_AEN 0x1000 |
373 | #define TW_EVENT_SOURCE_COMMAND 0x1001 |
374 | #define TW_EVENT_SOURCE_PCHIP 0x1002 |
375 | #define TW_EVENT_SOURCE_DRIVER 0x1003 |
376 | #define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101 |
377 | #define TW_IOCTL_GET_LAST_EVENT 0x102 |
378 | #define TW_IOCTL_GET_FIRST_EVENT 0x103 |
379 | #define TW_IOCTL_GET_NEXT_EVENT 0x104 |
380 | #define TW_IOCTL_GET_PREVIOUS_EVENT 0x105 |
381 | #define TW_IOCTL_GET_LOCK 0x106 |
382 | #define TW_IOCTL_RELEASE_LOCK 0x107 |
383 | #define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 |
384 | #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked |
385 | #define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked |
386 | #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events |
387 | #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred |
388 | #define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address |
389 | #define TW_IOCTL_ERROR_OS_EINTR -EINTR // Interrupted system call |
390 | #define TW_IOCTL_ERROR_OS_EINVAL -EINVAL // Invalid argument |
391 | #define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM // Out of memory |
392 | #define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS // Restart system call |
393 | #define TW_IOCTL_ERROR_OS_EIO -EIO // I/O error |
394 | #define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY // Not a typewriter |
395 | #define TW_IOCTL_ERROR_OS_ENODEV -ENODEV // No such device |
396 | #define TW_ALLOCATION_LENGTH 128 |
397 | #define TW_SENSE_DATA_LENGTH 18 |
398 | #define TW_STATUS_CHECK_CONDITION 2 |
399 | #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a |
400 | #define TW_ERROR_UNIT_OFFLINE 0x128 |
401 | #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3 |
402 | #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4 |
403 | #define TW_MESSAGE_SOURCE_LINUX_DRIVER 6 |
404 | #define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER |
405 | #define TW_MESSAGE_SOURCE_LINUX_OS 9 |
406 | #define TW_OS TW_MESSAGE_SOURCE_LINUX_OS |
407 | #ifndef PCI_DEVICE_ID_3WARE_9000 |
408 | #define PCI_DEVICE_ID_3WARE_9000 0x1002 |
409 | #endif |
410 | #ifndef PCI_DEVICE_ID_3WARE_9550SX |
411 | #define PCI_DEVICE_ID_3WARE_9550SX 0x1003 |
412 | #endif |
413 | #ifndef PCI_DEVICE_ID_3WARE_9650SE |
414 | #define PCI_DEVICE_ID_3WARE_9650SE 0x1004 |
415 | #endif |
416 | #ifndef PCI_DEVICE_ID_3WARE_9690SA |
417 | #define PCI_DEVICE_ID_3WARE_9690SA 0x1005 |
418 | #endif |
419 | |
420 | /* Bitmask macros to eliminate bitfields */ |
421 | |
422 | /* opcode: 5, reserved: 3 */ |
423 | #define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f)) |
424 | #define TW_OP_OUT(x) (x & 0x1f) |
425 | |
426 | /* opcode: 5, sgloffset: 3 */ |
427 | #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f)) |
428 | #define TW_SGL_OUT(x) ((x >> 5) & 0x7) |
429 | |
430 | /* severity: 3, reserved: 5 */ |
431 | #define TW_SEV_OUT(x) (x & 0x7) |
432 | |
433 | /* reserved_1: 4, response_id: 8, reserved_2: 20 */ |
434 | #define TW_RESID_OUT(x) ((x >> 4) & 0xff) |
435 | |
436 | /* request_id: 12, lun: 4 */ |
437 | #define TW_REQ_LUN_IN(lun, request_id) \ |
438 | cpu_to_le16(((lun << 12) & 0xf000) | (request_id & 0xfff)) |
439 | #define TW_LUN_OUT(lun) ((le16_to_cpu(lun) >> 12) & 0xf) |
440 | |
441 | /* Macros */ |
442 | #define TW_CONTROL_REG_ADDR(x) (x->base_addr) |
443 | #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) |
444 | #define TW_COMMAND_QUEUE_REG_ADDR(x) \ |
445 | (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) |
446 | #define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) \ |
447 | ((unsigned char __iomem *)x->base_addr + 0x20) |
448 | #define TW_RESPONSE_QUEUE_REG_ADDR(x) \ |
449 | ((unsigned char __iomem *)x->base_addr + 0xC) |
450 | #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) \ |
451 | ((unsigned char __iomem *)x->base_addr + 0x30) |
452 | #define TW_CLEAR_ALL_INTERRUPTS(x) \ |
453 | (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
454 | #define TW_CLEAR_ATTENTION_INTERRUPT(x) \ |
455 | (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
456 | #define TW_CLEAR_HOST_INTERRUPT(x) \ |
457 | (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
458 | #define TW_DISABLE_INTERRUPTS(x) \ |
459 | (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) |
460 | #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) \ |
461 | (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ |
462 | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | \ |
463 | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) |
464 | #define TW_MASK_COMMAND_INTERRUPT(x) \ |
465 | (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
466 | #define TW_UNMASK_COMMAND_INTERRUPT(x) \ |
467 | (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) |
468 | #define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \ |
469 | TW_CONTROL_CLEAR_HOST_INTERRUPT | \ |
470 | TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ |
471 | TW_CONTROL_MASK_COMMAND_INTERRUPT | \ |
472 | TW_CONTROL_MASK_RESPONSE_INTERRUPT | \ |
473 | TW_CONTROL_CLEAR_ERROR_STATUS | \ |
474 | TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) |
475 | #define TW_PRINTK(h,a,b,c) { \ |
476 | if (h) \ |
477 | printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \ |
478 | else \ |
479 | printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \ |
480 | } |
481 | #define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16) |
482 | #define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4) |
483 | #define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109) |
484 | #define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62) |
485 | #define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0) |
486 | |
487 | #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) |
488 | typedef __le64 twa_addr_t; |
489 | #define TW_CPU_TO_SGL(x) cpu_to_le64(x) |
490 | #else |
491 | typedef __le32 twa_addr_t; |
492 | #define TW_CPU_TO_SGL(x) cpu_to_le32(x) |
493 | #endif |
494 | |
495 | /* Scatter Gather List Entry */ |
496 | typedef struct TAG_TW_SG_Entry { |
497 | twa_addr_t address; |
498 | __le32 length; |
499 | } __packed TW_SG_Entry; |
500 | |
501 | /* Command Packet */ |
502 | typedef struct TW_Command { |
503 | u8 opcode__sgloffset; |
504 | u8 size; |
505 | u8 request_id; |
506 | u8 unit__hostid; |
507 | /* Second DWORD */ |
508 | u8 status; |
509 | u8 flags; |
510 | union { |
511 | __le16 block_count; |
512 | __le16 parameter_count; |
513 | } byte6_offset; |
514 | union { |
515 | struct { |
516 | __le32 lba; |
517 | TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; |
518 | twa_addr_t padding; |
519 | } io; |
520 | struct { |
521 | TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; |
522 | __le32 padding; |
523 | twa_addr_t padding2; |
524 | } param; |
525 | } byte8_offset; |
526 | } TW_Command; |
527 | |
528 | /* Command Packet for 9000+ controllers */ |
529 | typedef struct TAG_TW_Command_Apache { |
530 | u8 opcode__reserved; |
531 | u8 unit; |
532 | __le16 request_id__lunl; |
533 | u8 status; |
534 | u8 sgl_offset; |
535 | __le16 sgl_entries__lunh; |
536 | u8 cdb[16]; |
537 | TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH]; |
538 | u8 padding[TW_PADDING_LENGTH]; |
539 | } TW_Command_Apache; |
540 | |
541 | /* New command packet header */ |
542 | typedef struct TAG_TW_Command_Apache_Header { |
543 | unsigned char sense_data[TW_SENSE_DATA_LENGTH]; |
544 | struct { |
545 | u8 reserved[4]; |
546 | __le16 error; |
547 | u8 padding; |
548 | u8 severity__reserved; |
549 | } status_block; |
550 | unsigned char err_specific_desc[98]; |
551 | struct { |
552 | u8 size_header; |
553 | u8 reserved[2]; |
554 | u8 size_sense; |
555 | } header_desc; |
556 | } TW_Command_Apache_Header; |
557 | |
558 | /* This struct is a union of the 2 command packets */ |
559 | typedef struct TAG_TW_Command_Full { |
560 | TW_Command_Apache_Header header; |
561 | union { |
562 | TW_Command oldcommand; |
563 | TW_Command_Apache newcommand; |
564 | } command; |
565 | } TW_Command_Full; |
566 | |
567 | /* Initconnection structure */ |
568 | typedef struct TAG_TW_Initconnect { |
569 | u8 opcode__reserved; |
570 | u8 size; |
571 | u8 request_id; |
572 | u8 res2; |
573 | u8 status; |
574 | u8 flags; |
575 | __le16 message_credits; |
576 | __le32 features; |
577 | __le16 fw_srl; |
578 | __le16 fw_arch_id; |
579 | __le16 fw_branch; |
580 | __le16 fw_build; |
581 | __le32 result; |
582 | } TW_Initconnect; |
583 | |
584 | /* Event info structure */ |
585 | typedef struct TAG_TW_Event |
586 | { |
587 | unsigned int sequence_id; |
588 | unsigned int time_stamp_sec; |
589 | unsigned short aen_code; |
590 | unsigned char severity; |
591 | unsigned char retrieved; |
592 | unsigned char repeat_count; |
593 | unsigned char parameter_len; |
594 | unsigned char parameter_data[98]; |
595 | } TW_Event; |
596 | |
597 | typedef struct TAG_TW_Ioctl_Driver_Command { |
598 | unsigned int control_code; |
599 | unsigned int status; |
600 | unsigned int unique_id; |
601 | unsigned int sequence_id; |
602 | unsigned int os_specific; |
603 | unsigned int buffer_length; |
604 | } TW_Ioctl_Driver_Command; |
605 | |
606 | typedef struct TAG_TW_Ioctl_Apache { |
607 | TW_Ioctl_Driver_Command driver_command; |
608 | char padding[488]; |
609 | TW_Command_Full firmware_command; |
610 | char data_buffer[]; |
611 | } TW_Ioctl_Buf_Apache; |
612 | |
613 | /* Lock structure for ioctl get/release lock */ |
614 | typedef struct TAG_TW_Lock { |
615 | unsigned long timeout_msec; |
616 | unsigned long time_remaining_msec; |
617 | unsigned long force_flag; |
618 | } TW_Lock; |
619 | |
620 | /* GetParam descriptor */ |
621 | typedef struct { |
622 | __le16 table_id; |
623 | __le16 parameter_id; |
624 | __le16 parameter_size_bytes; |
625 | __le16 actual_parameter_size_bytes; |
626 | u8 data[]; |
627 | } TW_Param_Apache, *PTW_Param_Apache; |
628 | |
629 | /* Response queue */ |
630 | typedef union TAG_TW_Response_Queue { |
631 | u32 response_id; |
632 | u32 value; |
633 | } TW_Response_Queue; |
634 | |
635 | /* Compatibility information structure */ |
636 | typedef struct TAG_TW_Compatibility_Info |
637 | { |
638 | char driver_version[32]; |
639 | unsigned short working_srl; |
640 | unsigned short working_branch; |
641 | unsigned short working_build; |
642 | unsigned short driver_srl_high; |
643 | unsigned short driver_branch_high; |
644 | unsigned short driver_build_high; |
645 | unsigned short driver_srl_low; |
646 | unsigned short driver_branch_low; |
647 | unsigned short driver_build_low; |
648 | unsigned short fw_on_ctlr_srl; |
649 | unsigned short fw_on_ctlr_branch; |
650 | unsigned short fw_on_ctlr_build; |
651 | } TW_Compatibility_Info; |
652 | |
653 | typedef struct TAG_TW_Device_Extension { |
654 | u32 __iomem *base_addr; |
655 | unsigned long *generic_buffer_virt[TW_Q_LENGTH]; |
656 | dma_addr_t generic_buffer_phys[TW_Q_LENGTH]; |
657 | TW_Command_Full *command_packet_virt[TW_Q_LENGTH]; |
658 | dma_addr_t command_packet_phys[TW_Q_LENGTH]; |
659 | struct pci_dev *tw_pci_dev; |
660 | struct scsi_cmnd *srb[TW_Q_LENGTH]; |
661 | unsigned char free_queue[TW_Q_LENGTH]; |
662 | unsigned char free_head; |
663 | unsigned char free_tail; |
664 | unsigned char pending_queue[TW_Q_LENGTH]; |
665 | unsigned char pending_head; |
666 | unsigned char pending_tail; |
667 | int state[TW_Q_LENGTH]; |
668 | unsigned int posted_request_count; |
669 | unsigned int max_posted_request_count; |
670 | unsigned int pending_request_count; |
671 | unsigned int max_pending_request_count; |
672 | unsigned int max_sgl_entries; |
673 | unsigned int sgl_entries; |
674 | unsigned int num_resets; |
675 | unsigned int sector_count; |
676 | unsigned int max_sector_count; |
677 | unsigned int aen_count; |
678 | struct Scsi_Host *host; |
679 | long flags; |
680 | int reset_print; |
681 | TW_Event *event_queue[TW_Q_LENGTH]; |
682 | unsigned char error_index; |
683 | unsigned char event_queue_wrapped; |
684 | unsigned int error_sequence_id; |
685 | int ioctl_sem_lock; |
686 | ktime_t ioctl_time; |
687 | int chrdev_request_id; |
688 | wait_queue_head_t ioctl_wqueue; |
689 | struct mutex ioctl_lock; |
690 | char aen_clobber; |
691 | TW_Compatibility_Info tw_compat_info; |
692 | } TW_Device_Extension; |
693 | |
694 | #endif /* _3W_9XXX_H */ |
695 | |
696 | |