1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /****************************************************************************** |
3 | * QLOGIC LINUX SOFTWARE |
4 | * |
5 | * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver |
6 | * Copyright (C) 2000 Qlogic Corporation |
7 | * (www.qlogic.com) |
8 | * |
9 | ******************************************************************************/ |
10 | |
11 | #ifndef _QLA1280_H |
12 | #define _QLA1280_H |
13 | |
14 | /* |
15 | * Data bit definitions. |
16 | */ |
17 | #define BIT_0 0x1 |
18 | #define BIT_1 0x2 |
19 | #define BIT_2 0x4 |
20 | #define BIT_3 0x8 |
21 | #define BIT_4 0x10 |
22 | #define BIT_5 0x20 |
23 | #define BIT_6 0x40 |
24 | #define BIT_7 0x80 |
25 | #define BIT_8 0x100 |
26 | #define BIT_9 0x200 |
27 | #define BIT_10 0x400 |
28 | #define BIT_11 0x800 |
29 | #define BIT_12 0x1000 |
30 | #define BIT_13 0x2000 |
31 | #define BIT_14 0x4000 |
32 | #define BIT_15 0x8000 |
33 | #define BIT_16 0x10000 |
34 | #define BIT_17 0x20000 |
35 | #define BIT_18 0x40000 |
36 | #define BIT_19 0x80000 |
37 | #define BIT_20 0x100000 |
38 | #define BIT_21 0x200000 |
39 | #define BIT_22 0x400000 |
40 | #define BIT_23 0x800000 |
41 | #define BIT_24 0x1000000 |
42 | #define BIT_25 0x2000000 |
43 | #define BIT_26 0x4000000 |
44 | #define BIT_27 0x8000000 |
45 | #define BIT_28 0x10000000 |
46 | #define BIT_29 0x20000000 |
47 | #define BIT_30 0x40000000 |
48 | #define BIT_31 0x80000000 |
49 | |
50 | #if MEMORY_MAPPED_IO |
51 | #define RD_REG_WORD(addr) readw_relaxed(addr) |
52 | #define RD_REG_WORD_dmasync(addr) readw(addr) |
53 | #define WRT_REG_WORD(addr, data) writew(data, addr) |
54 | #else /* MEMORY_MAPPED_IO */ |
55 | #define RD_REG_WORD(addr) inw((unsigned long)addr) |
56 | #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr) |
57 | #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr) |
58 | #endif /* MEMORY_MAPPED_IO */ |
59 | |
60 | /* |
61 | * Host adapter default definitions. |
62 | */ |
63 | #define MAX_BUSES 2 /* 2 */ |
64 | #define MAX_B_BITS 1 |
65 | |
66 | #define MAX_TARGETS 16 /* 16 */ |
67 | #define MAX_T_BITS 4 /* 4 */ |
68 | |
69 | #define MAX_LUNS 8 /* 32 */ |
70 | #define MAX_L_BITS 3 /* 5 */ |
71 | |
72 | /* |
73 | * Watchdog time quantum |
74 | */ |
75 | #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ |
76 | |
77 | /* Command retry count (0-65535) */ |
78 | #define COMMAND_RETRY_COUNT 255 |
79 | |
80 | /* Maximum outstanding commands in ISP queues */ |
81 | #define MAX_OUTSTANDING_COMMANDS 512 |
82 | #define COMPLETED_HANDLE ((unsigned char *) \ |
83 | (MAX_OUTSTANDING_COMMANDS + 2)) |
84 | |
85 | /* ISP request and response entry counts (37-65535) */ |
86 | #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */ |
87 | #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */ |
88 | |
89 | /* |
90 | * SCSI Request Block structure (sp) that occurs after each struct scsi_cmnd. |
91 | */ |
92 | struct srb { |
93 | struct list_head list; /* (8/16) LU queue */ |
94 | struct scsi_cmnd *cmd; /* (4/8) SCSI command block */ |
95 | /* NOTE: the sp->cmd will be NULL when this completion is |
96 | * called, so you should know the scsi_cmnd when using this */ |
97 | struct completion *wait; |
98 | dma_addr_t saved_dma_handle; /* for unmap of single transfers */ |
99 | uint8_t flags; /* (1) Status flags. */ |
100 | uint8_t dir; /* direction of transfer */ |
101 | }; |
102 | |
103 | /* |
104 | * SRB flag definitions |
105 | */ |
106 | #define SRB_TIMEOUT (1 << 0) /* Command timed out */ |
107 | #define SRB_SENT (1 << 1) /* Command sent to ISP */ |
108 | #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */ |
109 | #define SRB_ABORTED (1 << 3) /* Command aborted command already */ |
110 | |
111 | /* |
112 | * ISP I/O Register Set structure definitions. |
113 | */ |
114 | struct device_reg { |
115 | uint16_t id_l; /* ID low */ |
116 | uint16_t id_h; /* ID high */ |
117 | uint16_t cfg_0; /* Configuration 0 */ |
118 | #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */ |
119 | #define ISP_CFG0_1020 BIT_0 /* ISP1020 */ |
120 | #define ISP_CFG0_1020A BIT_1 /* ISP1020A */ |
121 | #define ISP_CFG0_1040 BIT_2 /* ISP1040 */ |
122 | #define ISP_CFG0_1040A BIT_3 /* ISP1040A */ |
123 | #define ISP_CFG0_1040B BIT_4 /* ISP1040B */ |
124 | #define ISP_CFG0_1040C BIT_5 /* ISP1040C */ |
125 | uint16_t cfg_1; /* Configuration 1 */ |
126 | #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */ |
127 | #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */ |
128 | #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */ |
129 | #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */ |
130 | #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */ |
131 | #define ISP_CFG1_SXP BIT_0 /* SXP register select */ |
132 | uint16_t ictrl; /* Interface control */ |
133 | #define ISP_RESET BIT_0 /* ISP soft reset */ |
134 | #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ |
135 | #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ |
136 | #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */ |
137 | #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */ |
138 | uint16_t istatus; /* Interface status */ |
139 | #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ |
140 | #define RISC_INT BIT_2 /* RISC interrupt */ |
141 | #define PCI_INT BIT_1 /* PCI interrupt */ |
142 | uint16_t semaphore; /* Semaphore */ |
143 | uint16_t nvram; /* NVRAM register. */ |
144 | #define NV_DESELECT 0 |
145 | #define NV_CLOCK BIT_0 |
146 | #define NV_SELECT BIT_1 |
147 | #define NV_DATA_OUT BIT_2 |
148 | #define NV_DATA_IN BIT_3 |
149 | uint16_t flash_data; /* Flash BIOS data */ |
150 | uint16_t flash_address; /* Flash BIOS address */ |
151 | |
152 | uint16_t unused_1[0x06]; |
153 | |
154 | /* cdma_* and ddma_* are 1040 only */ |
155 | uint16_t cdma_cfg; |
156 | #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ |
157 | #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ |
158 | #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */ |
159 | #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ |
160 | uint16_t cdma_ctrl; |
161 | uint16_t cdma_status; |
162 | uint16_t cdma_fifo_status; |
163 | uint16_t cdma_count; |
164 | uint16_t cdma_reserved; |
165 | uint16_t cdma_address_count_0; |
166 | uint16_t cdma_address_count_1; |
167 | uint16_t cdma_address_count_2; |
168 | uint16_t cdma_address_count_3; |
169 | |
170 | uint16_t unused_2[0x06]; |
171 | |
172 | uint16_t ddma_cfg; |
173 | #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ |
174 | #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ |
175 | #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */ |
176 | #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ |
177 | uint16_t ddma_ctrl; |
178 | uint16_t ddma_status; |
179 | uint16_t ddma_fifo_status; |
180 | uint16_t ddma_xfer_count_low; |
181 | uint16_t ddma_xfer_count_high; |
182 | uint16_t ddma_addr_count_0; |
183 | uint16_t ddma_addr_count_1; |
184 | uint16_t ddma_addr_count_2; |
185 | uint16_t ddma_addr_count_3; |
186 | |
187 | uint16_t unused_3[0x0e]; |
188 | |
189 | uint16_t mailbox0; /* Mailbox 0 */ |
190 | uint16_t mailbox1; /* Mailbox 1 */ |
191 | uint16_t mailbox2; /* Mailbox 2 */ |
192 | uint16_t mailbox3; /* Mailbox 3 */ |
193 | uint16_t mailbox4; /* Mailbox 4 */ |
194 | uint16_t mailbox5; /* Mailbox 5 */ |
195 | uint16_t mailbox6; /* Mailbox 6 */ |
196 | uint16_t mailbox7; /* Mailbox 7 */ |
197 | |
198 | uint16_t unused_4[0x20];/* 0x80-0xbf Gap */ |
199 | |
200 | uint16_t host_cmd; /* Host command and control */ |
201 | #define HOST_INT BIT_7 /* host interrupt bit */ |
202 | #define BIOS_ENABLE BIT_0 |
203 | |
204 | uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */ |
205 | |
206 | uint16_t gpio_data; |
207 | uint16_t gpio_enable; |
208 | |
209 | uint16_t unused_6[0x11]; /* d0-f0 */ |
210 | uint16_t scsiControlPins; /* f2 */ |
211 | }; |
212 | |
213 | #define MAILBOX_REGISTER_COUNT 8 |
214 | |
215 | /* |
216 | * ISP product identification definitions in mailboxes after reset. |
217 | */ |
218 | #define PROD_ID_1 0x4953 |
219 | #define PROD_ID_2 0x0000 |
220 | #define PROD_ID_2a 0x5020 |
221 | #define PROD_ID_3 0x2020 |
222 | #define PROD_ID_4 0x1 |
223 | |
224 | /* |
225 | * ISP host command and control register command definitions |
226 | */ |
227 | #define HC_RESET_RISC 0x1000 /* Reset RISC */ |
228 | #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ |
229 | #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ |
230 | #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ |
231 | #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ |
232 | #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ |
233 | #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ |
234 | |
235 | /* |
236 | * ISP mailbox Self-Test status codes |
237 | */ |
238 | #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ |
239 | #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ |
240 | #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ |
241 | #define MBS_BUSY 4 /* Busy. */ |
242 | |
243 | /* |
244 | * ISP mailbox command complete status codes |
245 | */ |
246 | #define MBS_CMD_CMP 0x4000 /* Command Complete. */ |
247 | #define MBS_INV_CMD 0x4001 /* Invalid Command. */ |
248 | #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ |
249 | #define MBS_TEST_FAILED 0x4003 /* Test Failed. */ |
250 | #define MBS_CMD_ERR 0x4005 /* Command Error. */ |
251 | #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ |
252 | |
253 | /* |
254 | * ISP mailbox asynchronous event status codes |
255 | */ |
256 | #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ |
257 | #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ |
258 | #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ |
259 | #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ |
260 | #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ |
261 | #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ |
262 | #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ |
263 | #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ |
264 | #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ |
265 | #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ |
266 | |
267 | /* |
268 | * ISP mailbox commands |
269 | */ |
270 | #define MBC_NOP 0 /* No Operation */ |
271 | #define MBC_LOAD_RAM 1 /* Load RAM */ |
272 | #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */ |
273 | #define MBC_DUMP_RAM 3 /* Dump RAM contents */ |
274 | #define MBC_WRITE_RAM_WORD 4 /* Write ram word */ |
275 | #define MBC_READ_RAM_WORD 5 /* Read ram word */ |
276 | #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ |
277 | #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */ |
278 | #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */ |
279 | #define MBC_LOAD_RAM_A64_ROM 9 /* Load RAM 64bit ROM version */ |
280 | #define MBC_DUMP_RAM_A64_ROM 0x0a /* Dump RAM 64bit ROM version */ |
281 | #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ |
282 | #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ |
283 | #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */ |
284 | #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */ |
285 | #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */ |
286 | #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */ |
287 | #define MBC_BUS_RESET 0x18 /* SCSI bus reset */ |
288 | #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ |
289 | #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ |
290 | #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ |
291 | #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ |
292 | #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ |
293 | #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ |
294 | #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */ |
295 | #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ |
296 | #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ |
297 | #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ |
298 | #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ |
299 | #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ |
300 | #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ |
301 | #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ |
302 | #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ |
303 | #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ |
304 | #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ |
305 | #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ |
306 | #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ |
307 | |
308 | /* |
309 | * ISP Get/Set Target Parameters mailbox command control flags. |
310 | */ |
311 | #define TP_PPR BIT_5 /* PPR */ |
312 | #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ |
313 | #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ |
314 | #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ |
315 | #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ |
316 | #define TP_SYNC BIT_12 /* Synchronous data transfers. */ |
317 | #define TP_WIDE BIT_13 /* Wide data transfers. */ |
318 | #define TP_PARITY BIT_14 /* Parity checking. */ |
319 | #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */ |
320 | |
321 | /* |
322 | * NVRAM Command values. |
323 | */ |
324 | #define NV_START_BIT BIT_2 |
325 | #define NV_WRITE_OP (BIT_26 | BIT_24) |
326 | #define NV_READ_OP (BIT_26 | BIT_25) |
327 | #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24) |
328 | #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24) |
329 | #define NV_DELAY_COUNT 10 |
330 | |
331 | /* |
332 | * QLogic ISP1280/ISP12160 NVRAM structure definition. |
333 | */ |
334 | struct nvram { |
335 | uint8_t id0; /* 0 */ |
336 | uint8_t id1; /* 1 */ |
337 | uint8_t id2; /* 2 */ |
338 | uint8_t id3; /* 3 */ |
339 | uint8_t version; /* 4 */ |
340 | |
341 | struct { |
342 | uint8_t bios_configuration_mode:2; |
343 | uint8_t bios_disable:1; |
344 | uint8_t selectable_scsi_boot_enable:1; |
345 | uint8_t cd_rom_boot_enable:1; |
346 | uint8_t disable_loading_risc_code:1; |
347 | uint8_t enable_64bit_addressing:1; |
348 | uint8_t unused_7:1; |
349 | } cntr_flags_1; /* 5 */ |
350 | |
351 | struct { |
352 | uint8_t boot_lun_number:5; |
353 | uint8_t scsi_bus_number:1; |
354 | uint8_t unused_6:1; |
355 | uint8_t unused_7:1; |
356 | } cntr_flags_2l; /* 7 */ |
357 | |
358 | struct { |
359 | uint8_t boot_target_number:4; |
360 | uint8_t unused_12:1; |
361 | uint8_t unused_13:1; |
362 | uint8_t unused_14:1; |
363 | uint8_t unused_15:1; |
364 | } cntr_flags_2h; /* 8 */ |
365 | |
366 | uint16_t unused_8; /* 8, 9 */ |
367 | uint16_t unused_10; /* 10, 11 */ |
368 | uint16_t unused_12; /* 12, 13 */ |
369 | uint16_t unused_14; /* 14, 15 */ |
370 | |
371 | struct { |
372 | uint8_t reserved:2; |
373 | uint8_t burst_enable:1; |
374 | uint8_t reserved_1:1; |
375 | uint8_t fifo_threshold:4; |
376 | } isp_config; /* 16 */ |
377 | |
378 | /* Termination |
379 | * 0 = Disable, 1 = high only, 3 = Auto term |
380 | */ |
381 | struct { |
382 | uint8_t scsi_bus_1_control:2; |
383 | uint8_t scsi_bus_0_control:2; |
384 | uint8_t unused_0:1; |
385 | uint8_t unused_1:1; |
386 | uint8_t unused_2:1; |
387 | uint8_t auto_term_support:1; |
388 | } termination; /* 17 */ |
389 | |
390 | uint16_t isp_parameter; /* 18, 19 */ |
391 | |
392 | union { |
393 | uint16_t w; |
394 | struct { |
395 | uint16_t enable_fast_posting:1; |
396 | uint16_t report_lvd_bus_transition:1; |
397 | uint16_t unused_2:1; |
398 | uint16_t unused_3:1; |
399 | uint16_t disable_iosbs_with_bus_reset_status:1; |
400 | uint16_t disable_synchronous_backoff:1; |
401 | uint16_t unused_6:1; |
402 | uint16_t synchronous_backoff_reporting:1; |
403 | uint16_t disable_reselection_fairness:1; |
404 | uint16_t unused_9:1; |
405 | uint16_t unused_10:1; |
406 | uint16_t unused_11:1; |
407 | uint16_t unused_12:1; |
408 | uint16_t unused_13:1; |
409 | uint16_t unused_14:1; |
410 | uint16_t unused_15:1; |
411 | } f; |
412 | } firmware_feature; /* 20, 21 */ |
413 | |
414 | uint16_t unused_22; /* 22, 23 */ |
415 | |
416 | struct { |
417 | struct { |
418 | uint8_t initiator_id:4; |
419 | uint8_t scsi_reset_disable:1; |
420 | uint8_t scsi_bus_size:1; |
421 | uint8_t scsi_bus_type:1; |
422 | uint8_t unused_7:1; |
423 | } config_1; /* 24 */ |
424 | |
425 | uint8_t bus_reset_delay; /* 25 */ |
426 | uint8_t retry_count; /* 26 */ |
427 | uint8_t retry_delay; /* 27 */ |
428 | |
429 | struct { |
430 | uint8_t async_data_setup_time:4; |
431 | uint8_t req_ack_active_negation:1; |
432 | uint8_t data_line_active_negation:1; |
433 | uint8_t unused_6:1; |
434 | uint8_t unused_7:1; |
435 | } config_2; /* 28 */ |
436 | |
437 | uint8_t unused_29; /* 29 */ |
438 | |
439 | uint16_t selection_timeout; /* 30, 31 */ |
440 | uint16_t max_queue_depth; /* 32, 33 */ |
441 | |
442 | uint16_t unused_34; /* 34, 35 */ |
443 | uint16_t unused_36; /* 36, 37 */ |
444 | uint16_t unused_38; /* 38, 39 */ |
445 | |
446 | struct { |
447 | struct { |
448 | uint8_t renegotiate_on_error:1; |
449 | uint8_t stop_queue_on_check:1; |
450 | uint8_t auto_request_sense:1; |
451 | uint8_t tag_queuing:1; |
452 | uint8_t enable_sync:1; |
453 | uint8_t enable_wide:1; |
454 | uint8_t parity_checking:1; |
455 | uint8_t disconnect_allowed:1; |
456 | } parameter; /* 40 */ |
457 | |
458 | uint8_t execution_throttle; /* 41 */ |
459 | uint8_t sync_period; /* 42 */ |
460 | |
461 | union { /* 43 */ |
462 | uint8_t flags_43; |
463 | struct { |
464 | uint8_t sync_offset:4; |
465 | uint8_t device_enable:1; |
466 | uint8_t lun_disable:1; |
467 | uint8_t unused_6:1; |
468 | uint8_t unused_7:1; |
469 | } flags1x80; |
470 | struct { |
471 | uint8_t sync_offset:5; |
472 | uint8_t device_enable:1; |
473 | uint8_t unused_6:1; |
474 | uint8_t unused_7:1; |
475 | } flags1x160; |
476 | } flags; |
477 | union { /* PPR flags for the 1x160 controllers */ |
478 | uint8_t unused_44; |
479 | struct { |
480 | uint8_t ppr_options:4; |
481 | uint8_t ppr_bus_width:2; |
482 | uint8_t unused_8:1; |
483 | uint8_t enable_ppr:1; |
484 | } flags; /* 44 */ |
485 | } ppr_1x160; |
486 | uint8_t unused_45; /* 45 */ |
487 | } target[MAX_TARGETS]; |
488 | } bus[MAX_BUSES]; |
489 | |
490 | uint16_t unused_248; /* 248, 249 */ |
491 | |
492 | uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ |
493 | |
494 | union { /* 254 */ |
495 | uint8_t unused_254; |
496 | uint8_t system_id_pointer; |
497 | } sysid_1x160; |
498 | |
499 | uint8_t chksum; /* 255 */ |
500 | }; |
501 | |
502 | /* |
503 | * ISP queue - command entry structure definition. |
504 | */ |
505 | #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */ |
506 | struct cmd_entry { |
507 | uint8_t entry_type; /* Entry type. */ |
508 | #define COMMAND_TYPE 1 /* Command entry */ |
509 | uint8_t entry_count; /* Entry count. */ |
510 | uint8_t sys_define; /* System defined. */ |
511 | uint8_t entry_status; /* Entry Status. */ |
512 | __le32 handle; /* System handle. */ |
513 | uint8_t lun; /* SCSI LUN */ |
514 | uint8_t target; /* SCSI ID */ |
515 | __le16 cdb_len; /* SCSI command length. */ |
516 | __le16 control_flags; /* Control flags. */ |
517 | __le16 reserved; |
518 | __le16 timeout; /* Command timeout. */ |
519 | __le16 dseg_count; /* Data segment count. */ |
520 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ |
521 | __le32 dseg_0_address; /* Data segment 0 address. */ |
522 | __le32 dseg_0_length; /* Data segment 0 length. */ |
523 | __le32 dseg_1_address; /* Data segment 1 address. */ |
524 | __le32 dseg_1_length; /* Data segment 1 length. */ |
525 | __le32 dseg_2_address; /* Data segment 2 address. */ |
526 | __le32 dseg_2_length; /* Data segment 2 length. */ |
527 | __le32 dseg_3_address; /* Data segment 3 address. */ |
528 | __le32 dseg_3_length; /* Data segment 3 length. */ |
529 | }; |
530 | |
531 | /* |
532 | * ISP queue - continuation entry structure definition. |
533 | */ |
534 | struct cont_entry { |
535 | uint8_t entry_type; /* Entry type. */ |
536 | #define CONTINUE_TYPE 2 /* Continuation entry. */ |
537 | uint8_t entry_count; /* Entry count. */ |
538 | uint8_t sys_define; /* System defined. */ |
539 | uint8_t entry_status; /* Entry Status. */ |
540 | __le32 reserved; /* Reserved */ |
541 | __le32 dseg_0_address; /* Data segment 0 address. */ |
542 | __le32 dseg_0_length; /* Data segment 0 length. */ |
543 | __le32 dseg_1_address; /* Data segment 1 address. */ |
544 | __le32 dseg_1_length; /* Data segment 1 length. */ |
545 | __le32 dseg_2_address; /* Data segment 2 address. */ |
546 | __le32 dseg_2_length; /* Data segment 2 length. */ |
547 | __le32 dseg_3_address; /* Data segment 3 address. */ |
548 | __le32 dseg_3_length; /* Data segment 3 length. */ |
549 | __le32 dseg_4_address; /* Data segment 4 address. */ |
550 | __le32 dseg_4_length; /* Data segment 4 length. */ |
551 | __le32 dseg_5_address; /* Data segment 5 address. */ |
552 | __le32 dseg_5_length; /* Data segment 5 length. */ |
553 | __le32 dseg_6_address; /* Data segment 6 address. */ |
554 | __le32 dseg_6_length; /* Data segment 6 length. */ |
555 | }; |
556 | |
557 | /* |
558 | * ISP queue - status entry structure definition. |
559 | */ |
560 | struct response { |
561 | uint8_t entry_type; /* Entry type. */ |
562 | #define STATUS_TYPE 3 /* Status entry. */ |
563 | uint8_t entry_count; /* Entry count. */ |
564 | uint8_t sys_define; /* System defined. */ |
565 | uint8_t entry_status; /* Entry Status. */ |
566 | #define RF_CONT BIT_0 /* Continuation. */ |
567 | #define RF_FULL BIT_1 /* Full */ |
568 | #define BIT_2 /* Bad header. */ |
569 | #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ |
570 | __le32 handle; /* System handle. */ |
571 | __le16 scsi_status; /* SCSI status. */ |
572 | __le16 comp_status; /* Completion status. */ |
573 | __le16 state_flags; /* State flags. */ |
574 | #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ |
575 | #define SF_GOT_SENSE BIT_13 /* Got Sense */ |
576 | #define SF_GOT_STATUS BIT_12 /* Got Status */ |
577 | #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ |
578 | #define SF_SENT_CDB BIT_10 /* Send CDB */ |
579 | #define SF_GOT_TARGET BIT_9 /* */ |
580 | #define SF_GOT_BUS BIT_8 /* */ |
581 | __le16 status_flags; /* Status flags. */ |
582 | __le16 time; /* Time. */ |
583 | __le16 req_sense_length;/* Request sense data length. */ |
584 | __le32 residual_length; /* Residual transfer length. */ |
585 | __le16 reserved[4]; |
586 | uint8_t req_sense_data[32]; /* Request sense data. */ |
587 | }; |
588 | |
589 | /* |
590 | * ISP queue - marker entry structure definition. |
591 | */ |
592 | struct mrk_entry { |
593 | uint8_t entry_type; /* Entry type. */ |
594 | #define MARKER_TYPE 4 /* Marker entry. */ |
595 | uint8_t entry_count; /* Entry count. */ |
596 | uint8_t sys_define; /* System defined. */ |
597 | uint8_t entry_status; /* Entry Status. */ |
598 | __le32 reserved; |
599 | uint8_t lun; /* SCSI LUN */ |
600 | uint8_t target; /* SCSI ID */ |
601 | uint8_t modifier; /* Modifier (7-0). */ |
602 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ |
603 | #define MK_SYNC_ID 1 /* Synchronize ID */ |
604 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ |
605 | uint8_t reserved_1[53]; |
606 | }; |
607 | |
608 | /* |
609 | * ISP queue - extended command entry structure definition. |
610 | * |
611 | * Unused by the driver! |
612 | */ |
613 | struct ecmd_entry { |
614 | uint8_t entry_type; /* Entry type. */ |
615 | #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */ |
616 | uint8_t entry_count; /* Entry count. */ |
617 | uint8_t sys_define; /* System defined. */ |
618 | uint8_t entry_status; /* Entry Status. */ |
619 | uint32_t handle; /* System handle. */ |
620 | uint8_t lun; /* SCSI LUN */ |
621 | uint8_t target; /* SCSI ID */ |
622 | __le16 cdb_len; /* SCSI command length. */ |
623 | __le16 control_flags; /* Control flags. */ |
624 | __le16 reserved; |
625 | __le16 timeout; /* Command timeout. */ |
626 | __le16 dseg_count; /* Data segment count. */ |
627 | uint8_t scsi_cdb[88]; /* SCSI command words. */ |
628 | }; |
629 | |
630 | /* |
631 | * ISP queue - 64-Bit addressing, command entry structure definition. |
632 | */ |
633 | typedef struct { |
634 | uint8_t entry_type; /* Entry type. */ |
635 | #define COMMAND_A64_TYPE 9 /* Command A64 entry */ |
636 | uint8_t entry_count; /* Entry count. */ |
637 | uint8_t sys_define; /* System defined. */ |
638 | uint8_t entry_status; /* Entry Status. */ |
639 | __le32 handle; /* System handle. */ |
640 | uint8_t lun; /* SCSI LUN */ |
641 | uint8_t target; /* SCSI ID */ |
642 | __le16 cdb_len; /* SCSI command length. */ |
643 | __le16 control_flags; /* Control flags. */ |
644 | __le16 reserved; |
645 | __le16 timeout; /* Command timeout. */ |
646 | __le16 dseg_count; /* Data segment count. */ |
647 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ |
648 | __le32 reserved_1[2]; /* unused */ |
649 | __le32 dseg_0_address[2]; /* Data segment 0 address. */ |
650 | __le32 dseg_0_length; /* Data segment 0 length. */ |
651 | __le32 dseg_1_address[2]; /* Data segment 1 address. */ |
652 | __le32 dseg_1_length; /* Data segment 1 length. */ |
653 | } cmd_a64_entry_t, request_t; |
654 | |
655 | /* |
656 | * ISP queue - 64-Bit addressing, continuation entry structure definition. |
657 | */ |
658 | struct cont_a64_entry { |
659 | uint8_t entry_type; /* Entry type. */ |
660 | #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ |
661 | uint8_t entry_count; /* Entry count. */ |
662 | uint8_t sys_define; /* System defined. */ |
663 | uint8_t entry_status; /* Entry Status. */ |
664 | __le32 dseg_0_address[2]; /* Data segment 0 address. */ |
665 | __le32 dseg_0_length; /* Data segment 0 length. */ |
666 | __le32 dseg_1_address[2]; /* Data segment 1 address. */ |
667 | __le32 dseg_1_length; /* Data segment 1 length. */ |
668 | __le32 dseg_2_address[2]; /* Data segment 2 address. */ |
669 | __le32 dseg_2_length; /* Data segment 2 length. */ |
670 | __le32 dseg_3_address[2]; /* Data segment 3 address. */ |
671 | __le32 dseg_3_length; /* Data segment 3 length. */ |
672 | __le32 dseg_4_address[2]; /* Data segment 4 address. */ |
673 | __le32 dseg_4_length; /* Data segment 4 length. */ |
674 | }; |
675 | |
676 | /* |
677 | * ISP queue - enable LUN entry structure definition. |
678 | */ |
679 | struct elun_entry { |
680 | uint8_t entry_type; /* Entry type. */ |
681 | #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ |
682 | uint8_t entry_count; /* Entry count. */ |
683 | uint8_t reserved_1; |
684 | uint8_t entry_status; /* Entry Status not used. */ |
685 | __le32 reserved_2; |
686 | __le16 lun; /* Bit 15 is bus number. */ |
687 | __le16 reserved_4; |
688 | __le32 option_flags; |
689 | uint8_t status; |
690 | uint8_t reserved_5; |
691 | uint8_t command_count; /* Number of ATIOs allocated. */ |
692 | uint8_t immed_notify_count; /* Number of Immediate Notify */ |
693 | /* entries allocated. */ |
694 | uint8_t group_6_length; /* SCSI CDB length for group 6 */ |
695 | /* commands (2-26). */ |
696 | uint8_t group_7_length; /* SCSI CDB length for group 7 */ |
697 | /* commands (2-26). */ |
698 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
699 | __le16 reserved_6[20]; |
700 | }; |
701 | |
702 | /* |
703 | * ISP queue - modify LUN entry structure definition. |
704 | * |
705 | * Unused by the driver! |
706 | */ |
707 | struct modify_lun_entry { |
708 | uint8_t entry_type; /* Entry type. */ |
709 | #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ |
710 | uint8_t entry_count; /* Entry count. */ |
711 | uint8_t reserved_1; |
712 | uint8_t entry_status; /* Entry Status. */ |
713 | __le32 reserved_2; |
714 | uint8_t lun; /* SCSI LUN */ |
715 | uint8_t reserved_3; |
716 | uint8_t operators; |
717 | uint8_t reserved_4; |
718 | __le32 option_flags; |
719 | uint8_t status; |
720 | uint8_t reserved_5; |
721 | uint8_t command_count; /* Number of ATIOs allocated. */ |
722 | uint8_t immed_notify_count; /* Number of Immediate Notify */ |
723 | /* entries allocated. */ |
724 | __le16 reserved_6; |
725 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
726 | __le16 reserved_7[20]; |
727 | }; |
728 | |
729 | /* |
730 | * ISP queue - immediate notify entry structure definition. |
731 | */ |
732 | struct notify_entry { |
733 | uint8_t entry_type; /* Entry type. */ |
734 | #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ |
735 | uint8_t entry_count; /* Entry count. */ |
736 | uint8_t reserved_1; |
737 | uint8_t entry_status; /* Entry Status. */ |
738 | __le32 reserved_2; |
739 | uint8_t lun; |
740 | uint8_t initiator_id; |
741 | uint8_t reserved_3; |
742 | uint8_t target_id; |
743 | __le32 option_flags; |
744 | uint8_t status; |
745 | uint8_t reserved_4; |
746 | uint8_t tag_value; /* Received queue tag message value */ |
747 | uint8_t tag_type; /* Received queue tag message type */ |
748 | /* entries allocated. */ |
749 | __le16 seq_id; |
750 | uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ |
751 | __le16 reserved_5[8]; |
752 | uint8_t sense_data[18]; |
753 | }; |
754 | |
755 | /* |
756 | * ISP queue - notify acknowledge entry structure definition. |
757 | */ |
758 | struct nack_entry { |
759 | uint8_t entry_type; /* Entry type. */ |
760 | #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ |
761 | uint8_t entry_count; /* Entry count. */ |
762 | uint8_t reserved_1; |
763 | uint8_t entry_status; /* Entry Status. */ |
764 | __le32 reserved_2; |
765 | uint8_t lun; |
766 | uint8_t initiator_id; |
767 | uint8_t reserved_3; |
768 | uint8_t target_id; |
769 | __le32 option_flags; |
770 | uint8_t status; |
771 | uint8_t event; |
772 | __le16 seq_id; |
773 | __le16 reserved_4[22]; |
774 | }; |
775 | |
776 | /* |
777 | * ISP queue - Accept Target I/O (ATIO) entry structure definition. |
778 | */ |
779 | struct atio_entry { |
780 | uint8_t entry_type; /* Entry type. */ |
781 | #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ |
782 | uint8_t entry_count; /* Entry count. */ |
783 | uint8_t reserved_1; |
784 | uint8_t entry_status; /* Entry Status. */ |
785 | __le32 reserved_2; |
786 | uint8_t lun; |
787 | uint8_t initiator_id; |
788 | uint8_t cdb_len; |
789 | uint8_t target_id; |
790 | __le32 option_flags; |
791 | uint8_t status; |
792 | uint8_t scsi_status; |
793 | uint8_t tag_value; /* Received queue tag message value */ |
794 | uint8_t tag_type; /* Received queue tag message type */ |
795 | uint8_t cdb[26]; |
796 | uint8_t sense_data[18]; |
797 | }; |
798 | |
799 | /* |
800 | * ISP queue - Continue Target I/O (CTIO) entry structure definition. |
801 | */ |
802 | struct ctio_entry { |
803 | uint8_t entry_type; /* Entry type. */ |
804 | #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ |
805 | uint8_t entry_count; /* Entry count. */ |
806 | uint8_t reserved_1; |
807 | uint8_t entry_status; /* Entry Status. */ |
808 | __le32 reserved_2; |
809 | uint8_t lun; /* SCSI LUN */ |
810 | uint8_t initiator_id; |
811 | uint8_t reserved_3; |
812 | uint8_t target_id; |
813 | __le32 option_flags; |
814 | uint8_t status; |
815 | uint8_t scsi_status; |
816 | uint8_t tag_value; /* Received queue tag message value */ |
817 | uint8_t tag_type; /* Received queue tag message type */ |
818 | __le32 transfer_length; |
819 | __le32 residual; |
820 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
821 | __le16 dseg_count; /* Data segment count. */ |
822 | __le32 dseg_0_address; /* Data segment 0 address. */ |
823 | __le32 dseg_0_length; /* Data segment 0 length. */ |
824 | __le32 dseg_1_address; /* Data segment 1 address. */ |
825 | __le32 dseg_1_length; /* Data segment 1 length. */ |
826 | __le32 dseg_2_address; /* Data segment 2 address. */ |
827 | __le32 dseg_2_length; /* Data segment 2 length. */ |
828 | __le32 dseg_3_address; /* Data segment 3 address. */ |
829 | __le32 dseg_3_length; /* Data segment 3 length. */ |
830 | }; |
831 | |
832 | /* |
833 | * ISP queue - CTIO returned entry structure definition. |
834 | */ |
835 | struct ctio_ret_entry { |
836 | uint8_t entry_type; /* Entry type. */ |
837 | #define CTIO_RET_TYPE 7 /* CTIO return entry */ |
838 | uint8_t entry_count; /* Entry count. */ |
839 | uint8_t reserved_1; |
840 | uint8_t entry_status; /* Entry Status. */ |
841 | __le32 reserved_2; |
842 | uint8_t lun; /* SCSI LUN */ |
843 | uint8_t initiator_id; |
844 | uint8_t reserved_3; |
845 | uint8_t target_id; |
846 | __le32 option_flags; |
847 | uint8_t status; |
848 | uint8_t scsi_status; |
849 | uint8_t tag_value; /* Received queue tag message value */ |
850 | uint8_t tag_type; /* Received queue tag message type */ |
851 | __le32 transfer_length; |
852 | __le32 residual; |
853 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
854 | __le16 dseg_count; /* Data segment count. */ |
855 | __le32 dseg_0_address; /* Data segment 0 address. */ |
856 | __le32 dseg_0_length; /* Data segment 0 length. */ |
857 | __le32 dseg_1_address; /* Data segment 1 address. */ |
858 | __le16 dseg_1_length; /* Data segment 1 length. */ |
859 | uint8_t sense_data[18]; |
860 | }; |
861 | |
862 | /* |
863 | * ISP queue - CTIO A64 entry structure definition. |
864 | */ |
865 | struct ctio_a64_entry { |
866 | uint8_t entry_type; /* Entry type. */ |
867 | #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */ |
868 | uint8_t entry_count; /* Entry count. */ |
869 | uint8_t reserved_1; |
870 | uint8_t entry_status; /* Entry Status. */ |
871 | __le32 reserved_2; |
872 | uint8_t lun; /* SCSI LUN */ |
873 | uint8_t initiator_id; |
874 | uint8_t reserved_3; |
875 | uint8_t target_id; |
876 | __le32 option_flags; |
877 | uint8_t status; |
878 | uint8_t scsi_status; |
879 | uint8_t tag_value; /* Received queue tag message value */ |
880 | uint8_t tag_type; /* Received queue tag message type */ |
881 | __le32 transfer_length; |
882 | __le32 residual; |
883 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
884 | __le16 dseg_count; /* Data segment count. */ |
885 | __le32 reserved_4[2]; |
886 | __le32 dseg_0_address[2];/* Data segment 0 address. */ |
887 | __le32 dseg_0_length; /* Data segment 0 length. */ |
888 | __le32 dseg_1_address[2];/* Data segment 1 address. */ |
889 | __le32 dseg_1_length; /* Data segment 1 length. */ |
890 | }; |
891 | |
892 | /* |
893 | * ISP queue - CTIO returned entry structure definition. |
894 | */ |
895 | struct ctio_a64_ret_entry { |
896 | uint8_t entry_type; /* Entry type. */ |
897 | #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ |
898 | uint8_t entry_count; /* Entry count. */ |
899 | uint8_t reserved_1; |
900 | uint8_t entry_status; /* Entry Status. */ |
901 | __le32 reserved_2; |
902 | uint8_t lun; /* SCSI LUN */ |
903 | uint8_t initiator_id; |
904 | uint8_t reserved_3; |
905 | uint8_t target_id; |
906 | __le32 option_flags; |
907 | uint8_t status; |
908 | uint8_t scsi_status; |
909 | uint8_t tag_value; /* Received queue tag message value */ |
910 | uint8_t tag_type; /* Received queue tag message type */ |
911 | __le32 transfer_length; |
912 | __le32 residual; |
913 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
914 | __le16 dseg_count; /* Data segment count. */ |
915 | __le16 reserved_4[7]; |
916 | uint8_t sense_data[18]; |
917 | }; |
918 | |
919 | /* |
920 | * ISP request and response queue entry sizes |
921 | */ |
922 | #define RESPONSE_ENTRY_SIZE (sizeof(struct response)) |
923 | #define REQUEST_ENTRY_SIZE (sizeof(request_t)) |
924 | |
925 | /* |
926 | * ISP status entry - completion status definitions. |
927 | */ |
928 | #define CS_COMPLETE 0x0 /* No errors */ |
929 | #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ |
930 | #define CS_DMA 0x2 /* A DMA direction error. */ |
931 | #define CS_TRANSPORT 0x3 /* Transport error. */ |
932 | #define CS_RESET 0x4 /* SCSI bus reset occurred */ |
933 | #define CS_ABORTED 0x5 /* System aborted command. */ |
934 | #define CS_TIMEOUT 0x6 /* Timeout error. */ |
935 | #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ |
936 | #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ |
937 | #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ |
938 | #define CS_BAD_MSG 0xA /* Bad msg after status phase. */ |
939 | #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ |
940 | #define CS_EXTENDED_ID 0xC /* Extended ID failed. */ |
941 | #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */ |
942 | #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ |
943 | #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ |
944 | #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ |
945 | #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ |
946 | #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ |
947 | #define CS_ID_MSG 0x13 /* Target rejected ID msg. */ |
948 | #define CS_FREE 0x14 /* Unexpected bus free. */ |
949 | #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ |
950 | #define CS_TRANACTION_1 0x18 /* Transaction error 1 */ |
951 | #define CS_TRANACTION_2 0x19 /* Transaction error 2 */ |
952 | #define CS_TRANACTION_3 0x1a /* Transaction error 3 */ |
953 | #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ |
954 | #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ |
955 | #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ |
956 | #define CS_ARS_FAILED 0x1e /* ARS failed */ |
957 | #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ |
958 | #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ |
959 | #define CS_UNKNOWN 0x81 /* Driver defined */ |
960 | #define CS_RETRY 0x82 /* Driver defined */ |
961 | |
962 | /* |
963 | * ISP target entries - Option flags bit definitions. |
964 | */ |
965 | #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ |
966 | #define OF_DATA_IN BIT_6 /* Data in to initiator */ |
967 | /* (data from target to initiator) */ |
968 | #define OF_DATA_OUT BIT_7 /* Data out from initiator */ |
969 | /* (data from initiator to target) */ |
970 | #define OF_NO_DATA (BIT_7 | BIT_6) |
971 | #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ |
972 | #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ |
973 | #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ |
974 | #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ |
975 | #define OF_SSTS BIT_31 /* Send SCSI status */ |
976 | |
977 | |
978 | /* |
979 | * BUS parameters/settings structure - UNUSED |
980 | */ |
981 | struct bus_param { |
982 | uint8_t id; /* Host adapter SCSI id */ |
983 | uint8_t bus_reset_delay; /* SCSI bus reset delay. */ |
984 | uint8_t failed_reset_count; /* number of time reset failed */ |
985 | uint8_t unused; |
986 | uint16_t device_enables; /* Device enable bits. */ |
987 | uint16_t lun_disables; /* LUN disable bits. */ |
988 | uint16_t qtag_enables; /* Tag queue enables. */ |
989 | uint16_t hiwat; /* High water mark per device. */ |
990 | uint8_t reset_marker:1; |
991 | uint8_t disable_scsi_reset:1; |
992 | uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */ |
993 | }; |
994 | |
995 | |
996 | struct qla_driver_setup { |
997 | uint32_t no_sync:1; |
998 | uint32_t no_wide:1; |
999 | uint32_t no_ppr:1; |
1000 | uint32_t no_nvram:1; |
1001 | uint16_t sync_mask; |
1002 | uint16_t wide_mask; |
1003 | uint16_t ppr_mask; |
1004 | }; |
1005 | |
1006 | |
1007 | /* |
1008 | * Linux Host Adapter structure |
1009 | */ |
1010 | struct scsi_qla_host { |
1011 | /* Linux adapter configuration data */ |
1012 | struct Scsi_Host *host; /* pointer to host data */ |
1013 | struct scsi_qla_host *next; |
1014 | struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */ |
1015 | |
1016 | unsigned char __iomem *mmpbase; /* memory mapped address */ |
1017 | unsigned long host_no; |
1018 | struct pci_dev *pdev; |
1019 | uint8_t devnum; |
1020 | uint8_t revision; |
1021 | uint8_t ports; |
1022 | |
1023 | unsigned long actthreads; |
1024 | unsigned long isr_count; /* Interrupt count */ |
1025 | unsigned long spurious_int; |
1026 | |
1027 | /* Outstandings ISP commands. */ |
1028 | struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; |
1029 | |
1030 | /* BUS configuration data */ |
1031 | struct bus_param bus_settings[MAX_BUSES]; |
1032 | |
1033 | /* Received ISP mailbox data. */ |
1034 | volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; |
1035 | |
1036 | dma_addr_t request_dma; /* Physical Address */ |
1037 | request_t *request_ring; /* Base virtual address */ |
1038 | request_t *request_ring_ptr; /* Current address. */ |
1039 | uint16_t req_ring_index; /* Current index. */ |
1040 | uint16_t req_q_cnt; /* Number of available entries. */ |
1041 | |
1042 | dma_addr_t response_dma; /* Physical address. */ |
1043 | struct response *response_ring; /* Base virtual address */ |
1044 | struct response *response_ring_ptr; /* Current address. */ |
1045 | uint16_t rsp_ring_index; /* Current index. */ |
1046 | |
1047 | struct list_head done_q; /* Done queue */ |
1048 | |
1049 | struct completion *mailbox_wait; |
1050 | struct timer_list mailbox_timer; |
1051 | |
1052 | volatile struct { |
1053 | uint32_t online:1; /* 0 */ |
1054 | uint32_t reset_marker:1; /* 1 */ |
1055 | uint32_t disable_host_adapter:1; /* 2 */ |
1056 | uint32_t reset_active:1; /* 3 */ |
1057 | uint32_t abort_isp_active:1; /* 4 */ |
1058 | uint32_t disable_risc_code_load:1; /* 5 */ |
1059 | } flags; |
1060 | |
1061 | struct nvram nvram; |
1062 | int nvram_valid; |
1063 | |
1064 | /* Firmware Info */ |
1065 | unsigned short fwstart; /* start address for F/W */ |
1066 | unsigned char fwver1; /* F/W version first char */ |
1067 | unsigned char fwver2; /* F/W version second char */ |
1068 | unsigned char fwver3; /* F/W version third char */ |
1069 | }; |
1070 | |
1071 | #endif /* _QLA1280_H */ |
1072 | |