1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H
4#define __SOC_MEDIATEK_MT8173_MMSYS_H
5
6#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
7#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
8#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
9#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
10#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
11#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
12#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
13#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN 0x08c
14#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x0a0
15#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN 0x0a4
16#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
17#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x0b0
18#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
19#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN 0x0bc
20
21#define MT8173_AAL_SEL_IN_MERGE BIT(0)
22#define MT8173_COLOR0_SEL_IN_OVL0 BIT(0)
23#define MT8173_COLOR0_SOUT_MERGE BIT(0)
24#define MT8173_DPI0_SEL_IN_MASK GENMASK(1, 0)
25#define MT8173_DPI0_SEL_IN_RDMA1 BIT(0)
26#define MT8173_DSI0_SEL_IN_UFOE BIT(0)
27#define MT8173_GAMMA_MOUT_EN_RDMA1 BIT(0)
28#define MT8173_OD0_MOUT_EN_RDMA0 BIT(0)
29#define MT8173_OVL0_MOUT_EN_COLOR0 BIT(0)
30#define MT8173_OVL1_MOUT_EN_COLOR1 BIT(0)
31#define MT8173_UFOE_MOUT_EN_DSI0 BIT(0)
32#define MT8173_UFOE_SEL_IN_RDMA0 BIT(0)
33#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
34
35static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
36 {
37 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
38 MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
39 MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
40 }, {
41 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
42 MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
43 MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
44 }, {
45 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
46 MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
47 MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
48 }, {
49 DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
50 MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
51 MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
52 }, {
53 DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
54 MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
55 MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
56 }, {
57 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
58 MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
59 MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
60 }, {
61 DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
62 MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
63 MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
64 }, {
65 DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
66 MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
67 MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
68 }, {
69 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
70 MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
71 MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
72 }, {
73 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
74 MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
75 MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
76 }, {
77 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
78 MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
79 MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
80 }, {
81 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
82 MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
83 RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
84 }, {
85 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
86 MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
87 COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
88 }, {
89 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
90 MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
91 MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
92 }
93};
94
95#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
96

source code of linux/drivers/soc/mediatek/mt8173-mmsys.h