1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Author: James Liao <jamesjj.liao@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/delay.h> |
8 | #include <linux/device.h> |
9 | #include <linux/io.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/reset-controller.h> |
14 | #include <linux/soc/mediatek/mtk-mmsys.h> |
15 | |
16 | #include "mtk-mmsys.h" |
17 | #include "mt8167-mmsys.h" |
18 | #include "mt8173-mmsys.h" |
19 | #include "mt8183-mmsys.h" |
20 | #include "mt8186-mmsys.h" |
21 | #include "mt8188-mmsys.h" |
22 | #include "mt8192-mmsys.h" |
23 | #include "mt8195-mmsys.h" |
24 | #include "mt8365-mmsys.h" |
25 | |
26 | #define MMSYS_SW_RESET_PER_REG 32 |
27 | |
28 | static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { |
29 | .clk_driver = "clk-mt2701-mm" , |
30 | .routes = mmsys_default_routing_table, |
31 | .num_routes = ARRAY_SIZE(mmsys_default_routing_table), |
32 | }; |
33 | |
34 | static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { |
35 | .clk_driver = "clk-mt2712-mm" , |
36 | .routes = mmsys_default_routing_table, |
37 | .num_routes = ARRAY_SIZE(mmsys_default_routing_table), |
38 | }; |
39 | |
40 | static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { |
41 | .clk_driver = "clk-mt6779-mm" , |
42 | }; |
43 | |
44 | static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = { |
45 | .clk_driver = "clk-mt6795-mm" , |
46 | .routes = mt8173_mmsys_routing_table, |
47 | .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), |
48 | .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, |
49 | .num_resets = 64, |
50 | }; |
51 | |
52 | static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { |
53 | .clk_driver = "clk-mt6797-mm" , |
54 | }; |
55 | |
56 | static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { |
57 | .clk_driver = "clk-mt8167-mm" , |
58 | .routes = mt8167_mmsys_routing_table, |
59 | .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), |
60 | }; |
61 | |
62 | static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { |
63 | .clk_driver = "clk-mt8173-mm" , |
64 | .routes = mt8173_mmsys_routing_table, |
65 | .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), |
66 | .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, |
67 | .num_resets = 64, |
68 | }; |
69 | |
70 | static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { |
71 | .clk_driver = "clk-mt8183-mm" , |
72 | .routes = mmsys_mt8183_routing_table, |
73 | .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), |
74 | .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, |
75 | .num_resets = 32, |
76 | }; |
77 | |
78 | static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { |
79 | .clk_driver = "clk-mt8186-mm" , |
80 | .routes = mmsys_mt8186_routing_table, |
81 | .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), |
82 | .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, |
83 | .num_resets = 32, |
84 | }; |
85 | |
86 | static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { |
87 | .clk_driver = "clk-mt8188-vdo0" , |
88 | .routes = mmsys_mt8188_routing_table, |
89 | .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), |
90 | }; |
91 | |
92 | static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { |
93 | .clk_driver = "clk-mt8192-mm" , |
94 | .routes = mmsys_mt8192_routing_table, |
95 | .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), |
96 | .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, |
97 | .num_resets = 32, |
98 | }; |
99 | |
100 | static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { |
101 | .clk_driver = "clk-mt8195-vdo0" , |
102 | .routes = mmsys_mt8195_routing_table, |
103 | .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), |
104 | }; |
105 | |
106 | static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { |
107 | .clk_driver = "clk-mt8195-vdo1" , |
108 | .routes = mmsys_mt8195_vdo1_routing_table, |
109 | .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), |
110 | .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, |
111 | .num_resets = 64, |
112 | }; |
113 | |
114 | static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { |
115 | .clk_driver = "clk-mt8195-vpp0" , |
116 | .is_vppsys = true, |
117 | }; |
118 | |
119 | static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { |
120 | .clk_driver = "clk-mt8195-vpp1" , |
121 | .is_vppsys = true, |
122 | }; |
123 | |
124 | static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { |
125 | .clk_driver = "clk-mt8365-mm" , |
126 | .routes = mt8365_mmsys_routing_table, |
127 | .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), |
128 | }; |
129 | |
130 | struct mtk_mmsys { |
131 | void __iomem *regs; |
132 | const struct mtk_mmsys_driver_data *data; |
133 | struct platform_device *clks_pdev; |
134 | struct platform_device *drm_pdev; |
135 | spinlock_t lock; /* protects mmsys_sw_rst_b reg */ |
136 | struct reset_controller_dev rcdev; |
137 | struct cmdq_client_reg cmdq_base; |
138 | }; |
139 | |
140 | static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, |
141 | struct cmdq_pkt *cmdq_pkt) |
142 | { |
143 | int ret; |
144 | u32 tmp; |
145 | |
146 | if (mmsys->cmdq_base.size && cmdq_pkt) { |
147 | ret = cmdq_pkt_write_mask(pkt: cmdq_pkt, subsys: mmsys->cmdq_base.subsys, |
148 | offset: mmsys->cmdq_base.offset + offset, value: val, |
149 | mask); |
150 | if (ret) |
151 | pr_debug("CMDQ unavailable: using CPU write\n" ); |
152 | else |
153 | return; |
154 | } |
155 | tmp = readl_relaxed(mmsys->regs + offset); |
156 | tmp = (tmp & ~mask) | (val & mask); |
157 | writel_relaxed(tmp, mmsys->regs + offset); |
158 | } |
159 | |
160 | void mtk_mmsys_ddp_connect(struct device *dev, |
161 | enum mtk_ddp_comp_id cur, |
162 | enum mtk_ddp_comp_id next) |
163 | { |
164 | struct mtk_mmsys *mmsys = dev_get_drvdata(dev); |
165 | const struct mtk_mmsys_routes *routes = mmsys->data->routes; |
166 | int i; |
167 | |
168 | for (i = 0; i < mmsys->data->num_routes; i++) |
169 | if (cur == routes[i].from_comp && next == routes[i].to_comp) |
170 | mtk_mmsys_update_bits(mmsys, offset: routes[i].addr, mask: routes[i].mask, |
171 | val: routes[i].val, NULL); |
172 | } |
173 | EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); |
174 | |
175 | void mtk_mmsys_ddp_disconnect(struct device *dev, |
176 | enum mtk_ddp_comp_id cur, |
177 | enum mtk_ddp_comp_id next) |
178 | { |
179 | struct mtk_mmsys *mmsys = dev_get_drvdata(dev); |
180 | const struct mtk_mmsys_routes *routes = mmsys->data->routes; |
181 | int i; |
182 | |
183 | for (i = 0; i < mmsys->data->num_routes; i++) |
184 | if (cur == routes[i].from_comp && next == routes[i].to_comp) |
185 | mtk_mmsys_update_bits(mmsys, offset: routes[i].addr, mask: routes[i].mask, val: 0, NULL); |
186 | } |
187 | EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); |
188 | |
189 | void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height, |
190 | struct cmdq_pkt *cmdq_pkt) |
191 | { |
192 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, |
193 | mask: ~0, val: height << 16 | width, cmdq_pkt); |
194 | } |
195 | EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); |
196 | |
197 | void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, |
198 | struct cmdq_pkt *cmdq_pkt) |
199 | { |
200 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, mask: ~0, |
201 | val: be_height << 16 | be_width, cmdq_pkt); |
202 | } |
203 | EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); |
204 | |
205 | void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, |
206 | u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) |
207 | { |
208 | struct mtk_mmsys *mmsys = dev_get_drvdata(dev); |
209 | |
210 | mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, mask: ~0, |
211 | val: alpha << 16 | alpha, cmdq_pkt); |
212 | mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), |
213 | val: alpha_sel << (19 + idx), cmdq_pkt); |
214 | mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, |
215 | GENMASK(31, 16) | GENMASK(1, 0), val: biwidth << 16 | mode, cmdq_pkt); |
216 | } |
217 | EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); |
218 | |
219 | void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, |
220 | struct cmdq_pkt *cmdq_pkt) |
221 | { |
222 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, |
223 | BIT(4), val: channel_swap << 4, cmdq_pkt); |
224 | } |
225 | EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); |
226 | |
227 | void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) |
228 | { |
229 | struct mtk_mmsys *mmsys = dev_get_drvdata(dev); |
230 | |
231 | switch (val) { |
232 | case MTK_DPI_RGB888_SDR_CON: |
233 | mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, |
234 | MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL); |
235 | break; |
236 | case MTK_DPI_RGB565_SDR_CON: |
237 | mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, |
238 | MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL); |
239 | break; |
240 | case MTK_DPI_RGB565_DDR_CON: |
241 | mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, |
242 | MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL); |
243 | break; |
244 | case MTK_DPI_RGB888_DDR_CON: |
245 | default: |
246 | mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, |
247 | MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL); |
248 | break; |
249 | } |
250 | } |
251 | EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); |
252 | |
253 | void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable, |
254 | struct cmdq_pkt *cmdq_pkt) |
255 | { |
256 | u32 reg; |
257 | |
258 | switch (id) { |
259 | case 2: |
260 | reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH; |
261 | break; |
262 | case 3: |
263 | reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH; |
264 | break; |
265 | default: |
266 | dev_err(dev, "Invalid id %d\n" , id); |
267 | return; |
268 | } |
269 | |
270 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), offset: reg, mask: ~0, val: enable, cmdq_pkt); |
271 | } |
272 | EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config); |
273 | |
274 | void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable, |
275 | struct cmdq_pkt *cmdq_pkt) |
276 | { |
277 | u32 client; |
278 | |
279 | client = MT8195_SVPP1_MDP_RSZ; |
280 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), |
281 | MT8195_VPP1_HW_DCM_1ST_DIS0, mask: client, |
282 | val: ((enable) ? client : 0), cmdq_pkt); |
283 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), |
284 | MT8195_VPP1_HW_DCM_2ND_DIS0, mask: client, |
285 | val: ((enable) ? client : 0), cmdq_pkt); |
286 | |
287 | client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ; |
288 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), |
289 | MT8195_VPP1_HW_DCM_1ST_DIS1, mask: client, |
290 | val: ((enable) ? client : 0), cmdq_pkt); |
291 | mtk_mmsys_update_bits(mmsys: dev_get_drvdata(dev), |
292 | MT8195_VPP1_HW_DCM_2ND_DIS1, mask: client, |
293 | val: ((enable) ? client : 0), cmdq_pkt); |
294 | } |
295 | EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config); |
296 | |
297 | static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, |
298 | bool assert) |
299 | { |
300 | struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); |
301 | unsigned long flags; |
302 | u32 offset; |
303 | u32 reg; |
304 | |
305 | offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); |
306 | id = id % MMSYS_SW_RESET_PER_REG; |
307 | reg = mmsys->data->sw0_rst_offset + offset; |
308 | |
309 | spin_lock_irqsave(&mmsys->lock, flags); |
310 | |
311 | if (assert) |
312 | mtk_mmsys_update_bits(mmsys, offset: reg, BIT(id), val: 0, NULL); |
313 | else |
314 | mtk_mmsys_update_bits(mmsys, offset: reg, BIT(id), BIT(id), NULL); |
315 | |
316 | spin_unlock_irqrestore(lock: &mmsys->lock, flags); |
317 | |
318 | return 0; |
319 | } |
320 | |
321 | static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) |
322 | { |
323 | return mtk_mmsys_reset_update(rcdev, id, assert: true); |
324 | } |
325 | |
326 | static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) |
327 | { |
328 | return mtk_mmsys_reset_update(rcdev, id, assert: false); |
329 | } |
330 | |
331 | static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) |
332 | { |
333 | int ret; |
334 | |
335 | ret = mtk_mmsys_reset_assert(rcdev, id); |
336 | if (ret) |
337 | return ret; |
338 | |
339 | usleep_range(min: 1000, max: 1100); |
340 | |
341 | return mtk_mmsys_reset_deassert(rcdev, id); |
342 | } |
343 | |
344 | static const struct reset_control_ops mtk_mmsys_reset_ops = { |
345 | .assert = mtk_mmsys_reset_assert, |
346 | .deassert = mtk_mmsys_reset_deassert, |
347 | .reset = mtk_mmsys_reset, |
348 | }; |
349 | |
350 | static int mtk_mmsys_probe(struct platform_device *pdev) |
351 | { |
352 | struct device *dev = &pdev->dev; |
353 | struct platform_device *clks; |
354 | struct platform_device *drm; |
355 | struct mtk_mmsys *mmsys; |
356 | int ret; |
357 | |
358 | mmsys = devm_kzalloc(dev, size: sizeof(*mmsys), GFP_KERNEL); |
359 | if (!mmsys) |
360 | return -ENOMEM; |
361 | |
362 | mmsys->regs = devm_platform_ioremap_resource(pdev, index: 0); |
363 | if (IS_ERR(ptr: mmsys->regs)) { |
364 | ret = PTR_ERR(ptr: mmsys->regs); |
365 | dev_err(dev, "Failed to ioremap mmsys registers: %d\n" , ret); |
366 | return ret; |
367 | } |
368 | |
369 | mmsys->data = of_device_get_match_data(dev: &pdev->dev); |
370 | |
371 | if (mmsys->data->num_resets > 0) { |
372 | spin_lock_init(&mmsys->lock); |
373 | |
374 | mmsys->rcdev.owner = THIS_MODULE; |
375 | mmsys->rcdev.nr_resets = mmsys->data->num_resets; |
376 | mmsys->rcdev.ops = &mtk_mmsys_reset_ops; |
377 | mmsys->rcdev.of_node = pdev->dev.of_node; |
378 | ret = devm_reset_controller_register(dev: &pdev->dev, rcdev: &mmsys->rcdev); |
379 | if (ret) { |
380 | dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n" , ret); |
381 | return ret; |
382 | } |
383 | } |
384 | |
385 | /* CMDQ is optional */ |
386 | ret = cmdq_dev_get_client_reg(dev, client_reg: &mmsys->cmdq_base, idx: 0); |
387 | if (ret) |
388 | dev_dbg(dev, "No mediatek,gce-client-reg!\n" ); |
389 | |
390 | platform_set_drvdata(pdev, data: mmsys); |
391 | |
392 | clks = platform_device_register_data(parent: &pdev->dev, name: mmsys->data->clk_driver, |
393 | PLATFORM_DEVID_AUTO, NULL, size: 0); |
394 | if (IS_ERR(ptr: clks)) |
395 | return PTR_ERR(ptr: clks); |
396 | mmsys->clks_pdev = clks; |
397 | |
398 | if (mmsys->data->is_vppsys) |
399 | goto out_probe_done; |
400 | |
401 | drm = platform_device_register_data(parent: &pdev->dev, name: "mediatek-drm" , |
402 | PLATFORM_DEVID_AUTO, NULL, size: 0); |
403 | if (IS_ERR(ptr: drm)) { |
404 | platform_device_unregister(clks); |
405 | return PTR_ERR(ptr: drm); |
406 | } |
407 | mmsys->drm_pdev = drm; |
408 | |
409 | out_probe_done: |
410 | return 0; |
411 | } |
412 | |
413 | static void mtk_mmsys_remove(struct platform_device *pdev) |
414 | { |
415 | struct mtk_mmsys *mmsys = platform_get_drvdata(pdev); |
416 | |
417 | platform_device_unregister(mmsys->drm_pdev); |
418 | platform_device_unregister(mmsys->clks_pdev); |
419 | } |
420 | |
421 | static const struct of_device_id of_match_mtk_mmsys[] = { |
422 | { .compatible = "mediatek,mt2701-mmsys" , .data = &mt2701_mmsys_driver_data }, |
423 | { .compatible = "mediatek,mt2712-mmsys" , .data = &mt2712_mmsys_driver_data }, |
424 | { .compatible = "mediatek,mt6779-mmsys" , .data = &mt6779_mmsys_driver_data }, |
425 | { .compatible = "mediatek,mt6795-mmsys" , .data = &mt6795_mmsys_driver_data }, |
426 | { .compatible = "mediatek,mt6797-mmsys" , .data = &mt6797_mmsys_driver_data }, |
427 | { .compatible = "mediatek,mt8167-mmsys" , .data = &mt8167_mmsys_driver_data }, |
428 | { .compatible = "mediatek,mt8173-mmsys" , .data = &mt8173_mmsys_driver_data }, |
429 | { .compatible = "mediatek,mt8183-mmsys" , .data = &mt8183_mmsys_driver_data }, |
430 | { .compatible = "mediatek,mt8186-mmsys" , .data = &mt8186_mmsys_driver_data }, |
431 | { .compatible = "mediatek,mt8188-vdosys0" , .data = &mt8188_vdosys0_driver_data }, |
432 | { .compatible = "mediatek,mt8192-mmsys" , .data = &mt8192_mmsys_driver_data }, |
433 | /* "mediatek,mt8195-mmsys" compatible is deprecated */ |
434 | { .compatible = "mediatek,mt8195-mmsys" , .data = &mt8195_vdosys0_driver_data }, |
435 | { .compatible = "mediatek,mt8195-vdosys0" , .data = &mt8195_vdosys0_driver_data }, |
436 | { .compatible = "mediatek,mt8195-vdosys1" , .data = &mt8195_vdosys1_driver_data }, |
437 | { .compatible = "mediatek,mt8195-vppsys0" , .data = &mt8195_vppsys0_driver_data }, |
438 | { .compatible = "mediatek,mt8195-vppsys1" , .data = &mt8195_vppsys1_driver_data }, |
439 | { .compatible = "mediatek,mt8365-mmsys" , .data = &mt8365_mmsys_driver_data }, |
440 | { /* sentinel */ } |
441 | }; |
442 | MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys); |
443 | |
444 | static struct platform_driver mtk_mmsys_drv = { |
445 | .driver = { |
446 | .name = "mtk-mmsys" , |
447 | .of_match_table = of_match_mtk_mmsys, |
448 | }, |
449 | .probe = mtk_mmsys_probe, |
450 | .remove_new = mtk_mmsys_remove, |
451 | }; |
452 | module_platform_driver(mtk_mmsys_drv); |
453 | |
454 | MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>" ); |
455 | MODULE_DESCRIPTION("MediaTek SoC MMSYS driver" ); |
456 | MODULE_LICENSE("GPL" ); |
457 | |