1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | |
3 | #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H |
4 | #define __SOC_MEDIATEK_MT8365_MMSYS_H |
5 | |
6 | #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c |
7 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c |
8 | #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50 |
9 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54 |
10 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 |
11 | #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 |
12 | #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 |
13 | #define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0 |
14 | #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8 |
15 | #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc |
16 | |
17 | #define MT8365_RDMA0_SOUT_COLOR0 0x1 |
18 | #define MT8365_DITHER_MOUT_EN_DSI0 0x1 |
19 | #define MT8365_DSI0_SEL_IN_DITHER 0x1 |
20 | #define MT8365_RDMA0_SEL_IN_OVL0 0x0 |
21 | #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 |
22 | #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 |
23 | #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) |
24 | #define MT8365_RDMA1_SOUT_DPI0 0x1 |
25 | #define MT8365_DPI0_SEL_IN_RDMA1 0x0 |
26 | #define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1 |
27 | #define MT8365_DPI0_SEL_IN_RDMA1 0x0 |
28 | |
29 | static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { |
30 | { |
31 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
32 | MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, |
33 | MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL |
34 | }, |
35 | { |
36 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
37 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, |
38 | MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0 |
39 | }, |
40 | { |
41 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, |
42 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, |
43 | MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0 |
44 | }, |
45 | { |
46 | DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR, |
47 | MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, |
48 | MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 |
49 | }, |
50 | { |
51 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
52 | MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, |
53 | MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 |
54 | }, |
55 | { |
56 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
57 | MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, |
58 | MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER |
59 | }, |
60 | { |
61 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, |
62 | MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, |
63 | MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 |
64 | }, |
65 | { |
66 | DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, |
67 | MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00, |
68 | MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK |
69 | }, |
70 | { |
71 | DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, |
72 | MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, |
73 | MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1 |
74 | }, |
75 | { |
76 | DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, |
77 | MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL, |
78 | MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0 |
79 | }, |
80 | }; |
81 | |
82 | #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */ |
83 | |