1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | |
3 | #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H |
4 | #define __SOC_MEDIATEK_MT8188_MMSYS_H |
5 | |
6 | #define MT8188_VDO0_OVL_MOUT_EN 0xf14 |
7 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) |
8 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) |
9 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) |
10 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) |
11 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) |
12 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) |
13 | |
14 | #define MT8188_VDO0_SEL_IN 0xf34 |
15 | #define MT8188_VDO0_SEL_OUT 0xf38 |
16 | |
17 | #define MT8188_VDO0_DISP_RDMA_SEL 0xf40 |
18 | #define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0) |
19 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0) |
20 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0) |
21 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0) |
22 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8) |
23 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8) |
24 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8) |
25 | |
26 | |
27 | #define MT8188_VDO0_DSI0_SEL_IN 0xf44 |
28 | #define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0) |
29 | #define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0) |
30 | #define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0) |
31 | |
32 | #define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C |
33 | #define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0) |
34 | #define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0) |
35 | #define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0) |
36 | #define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0) |
37 | |
38 | #define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58 |
39 | #define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0) |
40 | #define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) |
41 | #define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) |
42 | #define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0) |
43 | #define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0) |
44 | |
45 | #define MT8188_VDO0_VPP_MERGE_SEL 0xf60 |
46 | #define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) |
47 | #define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) |
48 | #define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0) |
49 | |
50 | #define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4) |
51 | #define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4) |
52 | #define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4) |
53 | #define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4) |
54 | #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4) |
55 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4) |
56 | #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4) |
57 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) |
58 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) |
59 | |
60 | #define MT8188_VDO0_DSC_WARP_SEL 0xf64 |
61 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0) |
62 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0) |
63 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0) |
64 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16) |
65 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16) |
66 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17) |
67 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) |
68 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) |
69 | |
70 | static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { |
71 | { |
72 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
73 | MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, |
74 | MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 |
75 | }, { |
76 | DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, |
77 | MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, |
78 | MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 |
79 | }, { |
80 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
81 | MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, |
82 | MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 |
83 | }, { |
84 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
85 | MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, |
86 | MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 |
87 | }, { |
88 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, |
89 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, |
90 | MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT |
91 | }, { |
92 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, |
93 | MT8188_VDO0_DSC_WARP_SEL, |
94 | MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, |
95 | MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 |
96 | }, { |
97 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, |
98 | MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, |
99 | MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 |
100 | }, { |
101 | DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
102 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, |
103 | MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT |
104 | }, { |
105 | DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
106 | MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, |
107 | MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT |
108 | }, { |
109 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, |
110 | MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, |
111 | MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 |
112 | }, { |
113 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
114 | MT8188_VDO0_DISP_DITHER0_SEL_OUT, |
115 | MT8188_SOUT_DISP_DITHER0_TO_MASK, |
116 | MT8188_SOUT_DISP_DITHER0_TO_DSI0 |
117 | }, { |
118 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, |
119 | MT8188_VDO0_DISP_DITHER0_SEL_OUT, |
120 | MT8188_SOUT_DISP_DITHER0_TO_MASK, |
121 | MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 |
122 | }, { |
123 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, |
124 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
125 | MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 |
126 | }, { |
127 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, |
128 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
129 | MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 |
130 | }, { |
131 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, |
132 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
133 | MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 |
134 | }, { |
135 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, |
136 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
137 | MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN |
138 | }, { |
139 | DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
140 | MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, |
141 | MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 |
142 | }, { |
143 | DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
144 | MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, |
145 | MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE |
146 | }, |
147 | }; |
148 | |
149 | #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ |
150 | |