1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
4#define __SOC_MEDIATEK_MT8195_MMSYS_H
5
6#define MT8195_VDO0_OVL_MOUT_EN 0xf14
7#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
8#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
9#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
10#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
11#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
12#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
13
14#define MT8195_VDO0_SEL_IN 0xf34
15#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
16#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
17#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
18#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
19#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
20#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
21#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
22#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
23#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
24#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
25#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
26#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
27#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
28#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
29#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
30#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
31#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
32#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
33#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
34#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
35#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
36#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
37#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
38#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
39#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
40#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
41#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
42#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
43#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
44#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
45#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
46#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
47#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
48
49#define MT8195_VDO0_SEL_OUT 0xf38
50#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
51#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
52#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
53#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
54#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
55#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
56#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
57#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
58#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
59#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
60#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
61#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
62#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
63#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
64#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
65#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
66#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
67#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
68#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
69#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
70#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
71#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
72#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
73#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
74#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
75#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
76#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
77
78#define MT8195_VDO1_SW0_RST_B 0x1d0
79#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
80#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
81#define MT8195_VDO1_HDR_TOP_CFG 0xd00
82#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
83#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
84
85#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
86#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
87
88#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
89#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
90
91#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
92#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
93
94#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
95#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
96
97#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
98#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
99#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
100
101#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
102#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
103
104#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
105#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
106
107#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
108#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
109
110#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
111#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
112
113#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
114#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
115
116#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
117#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
118
119#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
120#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
121
122#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
123#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
124
125#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
126#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
127
128#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
129#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
130
131#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
132#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
133
134#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
135#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0
136
137#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
138#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0
139
140#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
141#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0
142
143#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
144#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0
145
146#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
147#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
148
149/* VPPSYS1 */
150#define MT8195_VPP1_HW_DCM_1ST_DIS0 0x150
151#define MT8195_VPP1_HW_DCM_1ST_DIS1 0x160
152#define MT8195_VPP1_HW_DCM_2ND_DIS0 0x1a0
153#define MT8195_VPP1_HW_DCM_2ND_DIS1 0x1b0
154#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH 0xf48
155#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH 0xf74
156
157/* VPPSYS1 HW DCM client*/
158#define MT8195_SVPP1_MDP_RSZ BIT(25)
159#define MT8195_SVPP2_MDP_RSZ BIT(4)
160#define MT8195_SVPP3_MDP_RSZ BIT(5)
161
162static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
163 {
164 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
165 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
166 MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
167 }, {
168 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
169 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
170 MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
171 }, {
172 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
173 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
174 MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
175 }, {
176 DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
177 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
178 MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
179 }, {
180 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
181 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
182 MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
183 }, {
184 DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
185 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
186 MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
187 }, {
188 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
189 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
190 MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
191 }, {
192 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
193 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
194 MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
195 }, {
196 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
197 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
198 MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
199 }, {
200 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
201 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
202 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
203 }, {
204 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
205 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
206 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
207 }, {
208 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
209 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
210 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
211 }, {
212 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
213 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
214 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
215 }, {
216 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
217 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
218 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
219 }, {
220 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
221 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
222 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
223 }, {
224 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
225 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
226 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
227 }, {
228 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
229 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
230 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
231 }, {
232 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
233 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
234 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
235 }, {
236 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
237 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
238 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
239 }, {
240 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
241 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
242 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
243 }, {
244 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
245 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
246 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
247 }, {
248 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
249 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
250 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
251 }, {
252 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
253 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
254 MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
255 }, {
256 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
257 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
258 MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
259 }, {
260 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
261 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
262 MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
263 }, {
264 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
265 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
266 MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
267 }, {
268 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
269 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
270 MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
271 }, {
272 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
273 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
274 MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
275 }, {
276 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
277 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
278 MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
279 }, {
280 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
281 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
282 MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
283 }, {
284 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
285 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
286 MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
287 }, {
288 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
289 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
290 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
291 }, {
292 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
293 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
294 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
295 }, {
296 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
297 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
298 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
299 }, {
300 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
301 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
302 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
303 }, {
304 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
305 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
306 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
307 }, {
308 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
309 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
310 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
311 }, {
312 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
313 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
314 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
315 }, {
316 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
317 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
318 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
319 }, {
320 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
321 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
322 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
323 }, {
324 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
325 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
326 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
327 }, {
328 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
329 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
330 MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
331 }, {
332 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
333 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
334 MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
335 }, {
336 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
337 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
338 MT8195_SOUT_DISP_DITHER0_TO_DSI0
339 }, {
340 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
341 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
342 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
343 }, {
344 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
345 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
346 MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
347 }, {
348 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
349 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
350 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
351 }, {
352 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
353 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
354 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
355 }, {
356 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
357 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
358 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
359 }, {
360 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
361 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
362 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
363 }, {
364 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
365 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
366 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
367 }, {
368 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
369 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
370 MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
371 }, {
372 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
373 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
374 MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
375 }, {
376 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
377 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
378 MT8195_SOUT_VPP_MERGE_TO_DSI1
379 }, {
380 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
381 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
382 MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
383 }, {
384 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
385 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
386 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
387 }, {
388 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
389 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
390 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
391 }, {
392 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
393 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
394 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
395 }, {
396 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
397 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
398 MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
399 }, {
400 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
401 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
402 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
403 }, {
404 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
405 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
406 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
407 }, {
408 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
409 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
410 MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
411 }, {
412 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
413 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
414 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
415 }, {
416 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
417 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
418 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
419 }, {
420 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
421 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
422 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
423 }, {
424 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
425 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
426 MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
427 }, {
428 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
429 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
430 MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
431 }, {
432 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
433 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
434 MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
435 }, {
436 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
437 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
438 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
439 }, {
440 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
441 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
442 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
443 }, {
444 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
445 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
446 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
447 }, {
448 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
449 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
450 MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
451 }
452};
453
454static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
455 {
456 DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
457 MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
458 MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
459 }, {
460 DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
461 MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
462 MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
463 }, {
464 DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
465 MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
466 MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
467 }, {
468 DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
469 MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
470 MT8195_SOUT_TO_MIXER_IN1_SEL
471 }, {
472 DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
473 MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
474 MT8195_SOUT_TO_MIXER_IN2_SEL
475 }, {
476 DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
477 MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
478 MT8195_SOUT_TO_MIXER_IN3_SEL
479 }, {
480 DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
481 MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
482 MT8195_SOUT_TO_MIXER_IN4_SEL
483 }, {
484 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
485 MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
486 MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
487 }, {
488 DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
489 MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
490 MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
491 }, {
492 DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
493 MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
494 MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
495 }, {
496 DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
497 MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
498 MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
499 }, {
500 DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
501 MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
502 MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
503 }, {
504 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
505 MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
506 MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
507 }, {
508 DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
509 MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
510 MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
511 }, {
512 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
513 MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
514 MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
515 }, {
516 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
517 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
518 MT8195_MERGE4_SOUT_TO_DPI1_SEL
519 }, {
520 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
521 MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
522 MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
523 }, {
524 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
525 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
526 MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
527 }
528};
529#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
530

source code of linux/drivers/soc/mediatek/mt8195-mmsys.h