1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. |
4 | * |
5 | * Contact Information: wlanfae <wlanfae@realtek.com> |
6 | */ |
7 | #include "rtl_core.h" |
8 | #include "r8192E_phyreg.h" |
9 | #include "r8192E_phy.h" |
10 | #include "r8190P_rtl8256.h" |
11 | |
12 | void rtl92e_set_bandwidth(struct net_device *dev, |
13 | enum ht_channel_width bandwidth) |
14 | { |
15 | u8 eRFPath; |
16 | struct r8192_priv *priv = rtllib_priv(dev); |
17 | |
18 | if (priv->card_8192_version != VERSION_8190_BD && |
19 | priv->card_8192_version != VERSION_8190_BE) { |
20 | netdev_warn(dev, format: "%s(): Unknown HW version.\n" , __func__); |
21 | return; |
22 | } |
23 | |
24 | for (eRFPath = 0; eRFPath < priv->num_total_rf_path; eRFPath++) { |
25 | switch (bandwidth) { |
26 | case HT_CHANNEL_WIDTH_20: |
27 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
28 | RegAddr: 0x0b, bMask12Bits, Data: 0x100); |
29 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
30 | RegAddr: 0x2c, bMask12Bits, Data: 0x3d7); |
31 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
32 | RegAddr: 0x0e, bMask12Bits, Data: 0x021); |
33 | break; |
34 | case HT_CHANNEL_WIDTH_20_40: |
35 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
36 | RegAddr: 0x0b, bMask12Bits, Data: 0x300); |
37 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
38 | RegAddr: 0x2c, bMask12Bits, Data: 0x3ff); |
39 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, |
40 | RegAddr: 0x0e, bMask12Bits, Data: 0x0e1); |
41 | break; |
42 | default: |
43 | netdev_err(dev, format: "%s(): Unknown bandwidth: %#X\n" , |
44 | __func__, bandwidth); |
45 | break; |
46 | } |
47 | } |
48 | } |
49 | |
50 | bool rtl92e_config_rf(struct net_device *dev) |
51 | { |
52 | u32 u4RegValue = 0; |
53 | u8 eRFPath; |
54 | bool rtStatus = true; |
55 | struct bb_reg_definition *pPhyReg; |
56 | struct r8192_priv *priv = rtllib_priv(dev); |
57 | u32 RegOffSetToBeCheck = 0x3; |
58 | u32 RegValueToBeCheck = 0x7f1; |
59 | u32 RF3_Final_Value = 0; |
60 | u8 ConstRetryTimes = 5, RetryTimes = 5; |
61 | u8 ret = 0; |
62 | |
63 | priv->num_total_rf_path = RTL819X_TOTAL_RF_PATH; |
64 | |
65 | for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; |
66 | eRFPath < priv->num_total_rf_path; eRFPath++) { |
67 | pPhyReg = &priv->phy_reg_def[eRFPath]; |
68 | |
69 | switch (eRFPath) { |
70 | case RF90_PATH_A: |
71 | u4RegValue = rtl92e_get_bb_reg(dev, dwRegAddr: pPhyReg->rfintfs, |
72 | bRFSI_RFENV); |
73 | break; |
74 | case RF90_PATH_B: |
75 | u4RegValue = rtl92e_get_bb_reg(dev, dwRegAddr: pPhyReg->rfintfs, |
76 | bRFSI_RFENV << 16); |
77 | break; |
78 | } |
79 | |
80 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfintfe, bRFSI_RFENV << 16, dwData: 0x1); |
81 | |
82 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfintfo, bRFSI_RFENV, dwData: 0x1); |
83 | |
84 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfHSSIPara2, |
85 | b3WireAddressLength, dwData: 0x0); |
86 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfHSSIPara2, |
87 | b3WireDataLength, dwData: 0x0); |
88 | |
89 | rtl92e_set_rf_reg(dev, eRFPath: (enum rf90_radio_path)eRFPath, RegAddr: 0x0, |
90 | bMask12Bits, Data: 0xbf); |
91 | |
92 | rtStatus = rtl92e_check_bb_and_rf(dev, CheckBlock: HW90_BLOCK_RF, |
93 | eRFPath: (enum rf90_radio_path)eRFPath); |
94 | if (!rtStatus) { |
95 | netdev_err(dev, format: "%s(): Failed to check RF Path %d.\n" , |
96 | __func__, eRFPath); |
97 | goto fail; |
98 | } |
99 | |
100 | RetryTimes = ConstRetryTimes; |
101 | RF3_Final_Value = 0; |
102 | while (RF3_Final_Value != RegValueToBeCheck && |
103 | RetryTimes != 0) { |
104 | ret = rtl92e_config_rf_path(dev, |
105 | eRFPath: (enum rf90_radio_path)eRFPath); |
106 | RF3_Final_Value = rtl92e_get_rf_reg(dev, |
107 | eRFPath: (enum rf90_radio_path)eRFPath, |
108 | RegAddr: RegOffSetToBeCheck, |
109 | bMask12Bits); |
110 | RetryTimes--; |
111 | } |
112 | |
113 | switch (eRFPath) { |
114 | case RF90_PATH_A: |
115 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfintfs, bRFSI_RFENV, |
116 | dwData: u4RegValue); |
117 | break; |
118 | case RF90_PATH_B: |
119 | rtl92e_set_bb_reg(dev, dwRegAddr: pPhyReg->rfintfs, |
120 | bRFSI_RFENV << 16, dwData: u4RegValue); |
121 | break; |
122 | } |
123 | |
124 | if (ret) { |
125 | netdev_err(dev, |
126 | format: "%s(): Failed to initialize RF Path %d.\n" , |
127 | __func__, eRFPath); |
128 | goto fail; |
129 | } |
130 | } |
131 | return true; |
132 | |
133 | fail: |
134 | return false; |
135 | } |
136 | |
137 | void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel) |
138 | { |
139 | u32 TxAGC = 0; |
140 | struct r8192_priv *priv = rtllib_priv(dev); |
141 | |
142 | TxAGC = powerlevel; |
143 | if (priv->dynamic_tx_low_pwr) { |
144 | if (priv->customer_id == RT_CID_819X_NETCORE) |
145 | TxAGC = 0x22; |
146 | else |
147 | TxAGC += priv->cck_pwr_enl; |
148 | } |
149 | if (TxAGC > 0x24) |
150 | TxAGC = 0x24; |
151 | rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, dwData: TxAGC); |
152 | } |
153 | |
154 | void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel) |
155 | { |
156 | struct r8192_priv *priv = rtllib_priv(dev); |
157 | u32 writeVal, powerBase0, powerBase1, writeVal_tmp; |
158 | u8 index = 0; |
159 | u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; |
160 | u8 byte0, byte1, byte2, byte3; |
161 | |
162 | powerBase0 = powerlevel + priv->legacy_ht_tx_pwr_diff; |
163 | powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | |
164 | (powerBase0 << 8) | powerBase0; |
165 | powerBase1 = powerlevel; |
166 | powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | |
167 | (powerBase1 << 8) | powerBase1; |
168 | |
169 | for (index = 0; index < 6; index++) { |
170 | writeVal = (u32)(priv->mcs_tx_pwr_level_org_offset[index] + |
171 | ((index < 2) ? powerBase0 : powerBase1)); |
172 | byte0 = writeVal & 0x7f; |
173 | byte1 = (writeVal & 0x7f00) >> 8; |
174 | byte2 = (writeVal & 0x7f0000) >> 16; |
175 | byte3 = (writeVal & 0x7f000000) >> 24; |
176 | if (byte0 > 0x24) |
177 | byte0 = 0x24; |
178 | if (byte1 > 0x24) |
179 | byte1 = 0x24; |
180 | if (byte2 > 0x24) |
181 | byte2 = 0x24; |
182 | if (byte3 > 0x24) |
183 | byte3 = 0x24; |
184 | |
185 | if (index == 3) { |
186 | writeVal_tmp = (byte3 << 24) | (byte2 << 16) | |
187 | (byte1 << 8) | byte0; |
188 | priv->pwr_track = writeVal_tmp; |
189 | } |
190 | |
191 | if (priv->dynamic_tx_high_pwr) |
192 | writeVal = 0x03030303; |
193 | else |
194 | writeVal = (byte3 << 24) | (byte2 << 16) | |
195 | (byte1 << 8) | byte0; |
196 | rtl92e_set_bb_reg(dev, dwRegAddr: RegOffset[index], dwBitMask: 0x7f7f7f7f, dwData: writeVal); |
197 | } |
198 | } |
199 | |